1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
13 static __checkReturn efx_rc_t
21 #if EFSYS_OPT_RX_SCATTER
22 static __checkReturn efx_rc_t
23 siena_rx_scatter_enable(
25 __in unsigned int buf_size);
26 #endif /* EFSYS_OPT_RX_SCATTER */
28 #if EFSYS_OPT_RX_SCALE
29 static __checkReturn efx_rc_t
30 siena_rx_scale_mode_set(
32 __in uint32_t rss_context,
33 __in efx_rx_hash_alg_t alg,
34 __in efx_rx_hash_type_t type,
35 __in boolean_t insert);
37 static __checkReturn efx_rc_t
38 siena_rx_scale_key_set(
40 __in uint32_t rss_context,
41 __in_ecount(n) uint8_t *key,
44 static __checkReturn efx_rc_t
45 siena_rx_scale_tbl_set(
47 __in uint32_t rss_context,
48 __in_ecount(n) unsigned int *table,
51 static __checkReturn uint32_t
54 __in efx_rx_hash_alg_t func,
55 __in uint8_t *buffer);
57 #endif /* EFSYS_OPT_RX_SCALE */
59 static __checkReturn efx_rc_t
60 siena_rx_prefix_pktlen(
63 __out uint16_t *lengthp);
68 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
70 __in unsigned int ndescs,
71 __in unsigned int completed,
72 __in unsigned int added);
77 __in unsigned int added,
78 __inout unsigned int *pushedp);
80 #if EFSYS_OPT_RX_PACKED_STREAM
82 siena_rx_qpush_ps_credits(
85 static __checkReturn uint8_t *
86 siena_rx_qps_packet_info(
89 __in uint32_t buffer_length,
90 __in uint32_t current_offset,
91 __out uint16_t *lengthp,
92 __out uint32_t *next_offsetp,
93 __out uint32_t *timestamp);
96 static __checkReturn efx_rc_t
102 __in efx_rxq_t *erp);
104 static __checkReturn efx_rc_t
107 __in unsigned int index,
108 __in unsigned int label,
109 __in efx_rxq_type_t type,
110 __in const efx_rxq_type_data_t *type_data,
111 __in efsys_mem_t *esmp,
114 __in unsigned int flags,
116 __in efx_rxq_t *erp);
120 __in efx_rxq_t *erp);
122 #endif /* EFSYS_OPT_SIENA */
126 static const efx_rx_ops_t __efx_rx_siena_ops = {
127 siena_rx_init, /* erxo_init */
128 siena_rx_fini, /* erxo_fini */
129 #if EFSYS_OPT_RX_SCATTER
130 siena_rx_scatter_enable, /* erxo_scatter_enable */
132 #if EFSYS_OPT_RX_SCALE
133 NULL, /* erxo_scale_context_alloc */
134 NULL, /* erxo_scale_context_free */
135 siena_rx_scale_mode_set, /* erxo_scale_mode_set */
136 siena_rx_scale_key_set, /* erxo_scale_key_set */
137 siena_rx_scale_tbl_set, /* erxo_scale_tbl_set */
138 siena_rx_prefix_hash, /* erxo_prefix_hash */
140 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
141 siena_rx_qpost, /* erxo_qpost */
142 siena_rx_qpush, /* erxo_qpush */
143 #if EFSYS_OPT_RX_PACKED_STREAM
144 siena_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
145 siena_rx_qps_packet_info, /* erxo_qps_packet_info */
147 siena_rx_qflush, /* erxo_qflush */
148 siena_rx_qenable, /* erxo_qenable */
149 siena_rx_qcreate, /* erxo_qcreate */
150 siena_rx_qdestroy, /* erxo_qdestroy */
152 #endif /* EFSYS_OPT_SIENA */
154 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
155 static const efx_rx_ops_t __efx_rx_ef10_ops = {
156 ef10_rx_init, /* erxo_init */
157 ef10_rx_fini, /* erxo_fini */
158 #if EFSYS_OPT_RX_SCATTER
159 ef10_rx_scatter_enable, /* erxo_scatter_enable */
161 #if EFSYS_OPT_RX_SCALE
162 ef10_rx_scale_context_alloc, /* erxo_scale_context_alloc */
163 ef10_rx_scale_context_free, /* erxo_scale_context_free */
164 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */
165 ef10_rx_scale_key_set, /* erxo_scale_key_set */
166 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */
167 ef10_rx_prefix_hash, /* erxo_prefix_hash */
169 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
170 ef10_rx_qpost, /* erxo_qpost */
171 ef10_rx_qpush, /* erxo_qpush */
172 #if EFSYS_OPT_RX_PACKED_STREAM
173 ef10_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
174 ef10_rx_qps_packet_info, /* erxo_qps_packet_info */
176 ef10_rx_qflush, /* erxo_qflush */
177 ef10_rx_qenable, /* erxo_qenable */
178 ef10_rx_qcreate, /* erxo_qcreate */
179 ef10_rx_qdestroy, /* erxo_qdestroy */
181 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
184 __checkReturn efx_rc_t
186 __inout efx_nic_t *enp)
188 const efx_rx_ops_t *erxop;
191 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
192 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
194 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
199 if (enp->en_mod_flags & EFX_MOD_RX) {
204 switch (enp->en_family) {
206 case EFX_FAMILY_SIENA:
207 erxop = &__efx_rx_siena_ops;
209 #endif /* EFSYS_OPT_SIENA */
211 #if EFSYS_OPT_HUNTINGTON
212 case EFX_FAMILY_HUNTINGTON:
213 erxop = &__efx_rx_ef10_ops;
215 #endif /* EFSYS_OPT_HUNTINGTON */
217 #if EFSYS_OPT_MEDFORD
218 case EFX_FAMILY_MEDFORD:
219 erxop = &__efx_rx_ef10_ops;
221 #endif /* EFSYS_OPT_MEDFORD */
223 #if EFSYS_OPT_MEDFORD2
224 case EFX_FAMILY_MEDFORD2:
225 erxop = &__efx_rx_ef10_ops;
227 #endif /* EFSYS_OPT_MEDFORD2 */
235 if ((rc = erxop->erxo_init(enp)) != 0)
238 enp->en_erxop = erxop;
239 enp->en_mod_flags |= EFX_MOD_RX;
249 EFSYS_PROBE1(fail1, efx_rc_t, rc);
251 enp->en_erxop = NULL;
252 enp->en_mod_flags &= ~EFX_MOD_RX;
260 const efx_rx_ops_t *erxop = enp->en_erxop;
262 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
263 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
264 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
265 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
267 erxop->erxo_fini(enp);
269 enp->en_erxop = NULL;
270 enp->en_mod_flags &= ~EFX_MOD_RX;
273 #if EFSYS_OPT_RX_SCATTER
274 __checkReturn efx_rc_t
275 efx_rx_scatter_enable(
277 __in unsigned int buf_size)
279 const efx_rx_ops_t *erxop = enp->en_erxop;
282 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
283 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
285 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
291 EFSYS_PROBE1(fail1, efx_rc_t, rc);
294 #endif /* EFSYS_OPT_RX_SCATTER */
296 #if EFSYS_OPT_RX_SCALE
297 __checkReturn efx_rc_t
298 efx_rx_scale_hash_flags_get(
300 __in efx_rx_hash_alg_t hash_alg,
301 __inout_ecount(EFX_RX_HASH_NFLAGS) unsigned int *flags,
302 __out unsigned int *nflagsp)
304 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
306 boolean_t additional_modes;
307 unsigned int *entryp = flags;
310 if (flags == NULL || nflagsp == NULL) {
315 l4 = encp->enc_rx_scale_l4_hash_supported;
316 additional_modes = encp->enc_rx_scale_additional_modes_supported;
318 #define LIST_FLAGS(_entryp, _class, _l4_hashing, _additional_modes) \
321 *(_entryp++) = EFX_RX_HASH(_class, 4TUPLE); \
323 if (_additional_modes) { \
325 EFX_RX_HASH(_class, 2TUPLE_DST); \
327 EFX_RX_HASH(_class, 2TUPLE_SRC); \
331 *(_entryp++) = EFX_RX_HASH(_class, 2TUPLE); \
333 if (_additional_modes) { \
334 *(_entryp++) = EFX_RX_HASH(_class, 1TUPLE_DST); \
335 *(_entryp++) = EFX_RX_HASH(_class, 1TUPLE_SRC); \
338 *(_entryp++) = EFX_RX_HASH(_class, DISABLE); \
340 _NOTE(CONSTANTCONDITION) \
344 case EFX_RX_HASHALG_PACKED_STREAM:
345 if ((encp->enc_rx_scale_hash_alg_mask & (1U << hash_alg)) == 0)
348 case EFX_RX_HASHALG_TOEPLITZ:
349 if ((encp->enc_rx_scale_hash_alg_mask & (1U << hash_alg)) == 0)
352 LIST_FLAGS(entryp, IPV4_TCP, l4, additional_modes);
353 LIST_FLAGS(entryp, IPV6_TCP, l4, additional_modes);
355 if (additional_modes) {
356 LIST_FLAGS(entryp, IPV4_UDP, l4, additional_modes);
357 LIST_FLAGS(entryp, IPV6_UDP, l4, additional_modes);
360 LIST_FLAGS(entryp, IPV4, B_FALSE, additional_modes);
361 LIST_FLAGS(entryp, IPV6, B_FALSE, additional_modes);
371 *nflagsp = (unsigned int)(entryp - flags);
372 EFSYS_ASSERT3U(*nflagsp, <=, EFX_RX_HASH_NFLAGS);
380 EFSYS_PROBE1(fail1, efx_rc_t, rc);
385 __checkReturn efx_rc_t
386 efx_rx_hash_default_support_get(
388 __out efx_rx_hash_support_t *supportp)
392 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
393 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
395 if (supportp == NULL) {
401 * Report the hashing support the client gets by default if it
402 * does not allocate an RSS context itself.
404 *supportp = enp->en_hash_support;
409 EFSYS_PROBE1(fail1, efx_rc_t, rc);
414 __checkReturn efx_rc_t
415 efx_rx_scale_default_support_get(
417 __out efx_rx_scale_context_type_t *typep)
421 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
422 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
430 * Report the RSS support the client gets by default if it
431 * does not allocate an RSS context itself.
433 *typep = enp->en_rss_context_type;
438 EFSYS_PROBE1(fail1, efx_rc_t, rc);
442 #endif /* EFSYS_OPT_RX_SCALE */
444 #if EFSYS_OPT_RX_SCALE
445 __checkReturn efx_rc_t
446 efx_rx_scale_context_alloc(
448 __in efx_rx_scale_context_type_t type,
449 __in uint32_t num_queues,
450 __out uint32_t *rss_contextp)
452 const efx_rx_ops_t *erxop = enp->en_erxop;
455 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
456 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
458 if (erxop->erxo_scale_context_alloc == NULL) {
462 if ((rc = erxop->erxo_scale_context_alloc(enp, type,
463 num_queues, rss_contextp)) != 0) {
472 EFSYS_PROBE1(fail1, efx_rc_t, rc);
475 #endif /* EFSYS_OPT_RX_SCALE */
477 #if EFSYS_OPT_RX_SCALE
478 __checkReturn efx_rc_t
479 efx_rx_scale_context_free(
481 __in uint32_t rss_context)
483 const efx_rx_ops_t *erxop = enp->en_erxop;
486 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
487 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
489 if (erxop->erxo_scale_context_free == NULL) {
493 if ((rc = erxop->erxo_scale_context_free(enp, rss_context)) != 0)
501 EFSYS_PROBE1(fail1, efx_rc_t, rc);
504 #endif /* EFSYS_OPT_RX_SCALE */
506 #if EFSYS_OPT_RX_SCALE
507 __checkReturn efx_rc_t
508 efx_rx_scale_mode_set(
510 __in uint32_t rss_context,
511 __in efx_rx_hash_alg_t alg,
512 __in efx_rx_hash_type_t type,
513 __in boolean_t insert)
515 const efx_rx_ops_t *erxop = enp->en_erxop;
516 unsigned int type_flags[EFX_RX_HASH_NFLAGS];
517 unsigned int type_nflags;
518 efx_rx_hash_type_t type_check;
522 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
523 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
526 * Legacy flags and modern bits cannot be
527 * used at the same time in the hash type.
529 if ((type & EFX_RX_HASH_LEGACY_MASK) &&
530 (type & ~EFX_RX_HASH_LEGACY_MASK)) {
536 * Translate legacy flags to the new representation
537 * so that chip-specific handlers will consider the
540 if (type & EFX_RX_HASH_IPV4) {
541 type |= EFX_RX_HASH(IPV4, 2TUPLE);
542 type |= EFX_RX_HASH(IPV4_TCP, 2TUPLE);
543 type |= EFX_RX_HASH(IPV4_UDP, 2TUPLE);
546 if (type & EFX_RX_HASH_TCPIPV4)
547 type |= EFX_RX_HASH(IPV4_TCP, 4TUPLE);
549 if (type & EFX_RX_HASH_IPV6) {
550 type |= EFX_RX_HASH(IPV6, 2TUPLE);
551 type |= EFX_RX_HASH(IPV6_TCP, 2TUPLE);
552 type |= EFX_RX_HASH(IPV6_UDP, 2TUPLE);
555 if (type & EFX_RX_HASH_TCPIPV6)
556 type |= EFX_RX_HASH(IPV6_TCP, 4TUPLE);
558 type &= ~EFX_RX_HASH_LEGACY_MASK;
562 * Get the list of supported hash flags and sanitise the input.
564 rc = efx_rx_scale_hash_flags_get(enp, alg, type_flags, &type_nflags);
568 for (i = 0; i < type_nflags; ++i) {
569 if ((type_check & type_flags[i]) == type_flags[i])
570 type_check &= ~(type_flags[i]);
573 if (type_check != 0) {
578 if (erxop->erxo_scale_mode_set != NULL) {
579 if ((rc = erxop->erxo_scale_mode_set(enp, rss_context, alg,
593 EFSYS_PROBE1(fail1, efx_rc_t, rc);
596 #endif /* EFSYS_OPT_RX_SCALE */
598 #if EFSYS_OPT_RX_SCALE
599 __checkReturn efx_rc_t
600 efx_rx_scale_key_set(
602 __in uint32_t rss_context,
603 __in_ecount(n) uint8_t *key,
606 const efx_rx_ops_t *erxop = enp->en_erxop;
609 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
610 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
612 if ((rc = erxop->erxo_scale_key_set(enp, rss_context, key, n)) != 0)
618 EFSYS_PROBE1(fail1, efx_rc_t, rc);
622 #endif /* EFSYS_OPT_RX_SCALE */
624 #if EFSYS_OPT_RX_SCALE
625 __checkReturn efx_rc_t
626 efx_rx_scale_tbl_set(
628 __in uint32_t rss_context,
629 __in_ecount(n) unsigned int *table,
632 const efx_rx_ops_t *erxop = enp->en_erxop;
635 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
636 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
638 if ((rc = erxop->erxo_scale_tbl_set(enp, rss_context, table, n)) != 0)
644 EFSYS_PROBE1(fail1, efx_rc_t, rc);
648 #endif /* EFSYS_OPT_RX_SCALE */
653 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
655 __in unsigned int ndescs,
656 __in unsigned int completed,
657 __in unsigned int added)
659 efx_nic_t *enp = erp->er_enp;
660 const efx_rx_ops_t *erxop = enp->en_erxop;
662 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
664 erxop->erxo_qpost(erp, addrp, size, ndescs, completed, added);
667 #if EFSYS_OPT_RX_PACKED_STREAM
670 efx_rx_qpush_ps_credits(
673 efx_nic_t *enp = erp->er_enp;
674 const efx_rx_ops_t *erxop = enp->en_erxop;
676 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
678 erxop->erxo_qpush_ps_credits(erp);
681 __checkReturn uint8_t *
682 efx_rx_qps_packet_info(
684 __in uint8_t *buffer,
685 __in uint32_t buffer_length,
686 __in uint32_t current_offset,
687 __out uint16_t *lengthp,
688 __out uint32_t *next_offsetp,
689 __out uint32_t *timestamp)
691 efx_nic_t *enp = erp->er_enp;
692 const efx_rx_ops_t *erxop = enp->en_erxop;
694 return (erxop->erxo_qps_packet_info(erp, buffer,
695 buffer_length, current_offset, lengthp,
696 next_offsetp, timestamp));
699 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
704 __in unsigned int added,
705 __inout unsigned int *pushedp)
707 efx_nic_t *enp = erp->er_enp;
708 const efx_rx_ops_t *erxop = enp->en_erxop;
710 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
712 erxop->erxo_qpush(erp, added, pushedp);
715 __checkReturn efx_rc_t
719 efx_nic_t *enp = erp->er_enp;
720 const efx_rx_ops_t *erxop = enp->en_erxop;
723 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
725 if ((rc = erxop->erxo_qflush(erp)) != 0)
731 EFSYS_PROBE1(fail1, efx_rc_t, rc);
740 efx_nic_t *enp = erp->er_enp;
741 const efx_rx_ops_t *erxop = enp->en_erxop;
743 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
745 erxop->erxo_qenable(erp);
748 static __checkReturn efx_rc_t
749 efx_rx_qcreate_internal(
751 __in unsigned int index,
752 __in unsigned int label,
753 __in efx_rxq_type_t type,
754 __in const efx_rxq_type_data_t *type_data,
755 __in efsys_mem_t *esmp,
758 __in unsigned int flags,
760 __deref_out efx_rxq_t **erpp)
762 const efx_rx_ops_t *erxop = enp->en_erxop;
766 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
767 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
769 /* Allocate an RXQ object */
770 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
777 erp->er_magic = EFX_RXQ_MAGIC;
779 erp->er_index = index;
780 erp->er_mask = ndescs - 1;
783 if ((rc = erxop->erxo_qcreate(enp, index, label, type, type_data, esmp,
784 ndescs, id, flags, eep, erp)) != 0)
795 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
797 EFSYS_PROBE1(fail1, efx_rc_t, rc);
802 __checkReturn efx_rc_t
805 __in unsigned int index,
806 __in unsigned int label,
807 __in efx_rxq_type_t type,
808 __in efsys_mem_t *esmp,
811 __in unsigned int flags,
813 __deref_out efx_rxq_t **erpp)
815 return efx_rx_qcreate_internal(enp, index, label, type, NULL,
816 esmp, ndescs, id, flags, eep, erpp);
819 #if EFSYS_OPT_RX_PACKED_STREAM
821 __checkReturn efx_rc_t
822 efx_rx_qcreate_packed_stream(
824 __in unsigned int index,
825 __in unsigned int label,
826 __in uint32_t ps_buf_size,
827 __in efsys_mem_t *esmp,
830 __deref_out efx_rxq_t **erpp)
832 efx_rxq_type_data_t type_data;
834 memset(&type_data, 0, sizeof (type_data));
836 type_data.ertd_packed_stream.eps_buf_size = ps_buf_size;
838 return efx_rx_qcreate_internal(enp, index, label,
839 EFX_RXQ_TYPE_PACKED_STREAM, &type_data, esmp, ndescs,
840 0 /* id unused on EF10 */, EFX_RXQ_FLAG_NONE, eep, erpp);
845 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
847 __checkReturn efx_rc_t
848 efx_rx_qcreate_es_super_buffer(
850 __in unsigned int index,
851 __in unsigned int label,
852 __in uint32_t n_bufs_per_desc,
853 __in uint32_t max_dma_len,
854 __in uint32_t buf_stride,
855 __in uint32_t hol_block_timeout,
856 __in efsys_mem_t *esmp,
858 __in unsigned int flags,
860 __deref_out efx_rxq_t **erpp)
863 efx_rxq_type_data_t type_data;
865 if (hol_block_timeout > EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX) {
870 memset(&type_data, 0, sizeof (type_data));
872 type_data.ertd_es_super_buffer.eessb_bufs_per_desc = n_bufs_per_desc;
873 type_data.ertd_es_super_buffer.eessb_max_dma_len = max_dma_len;
874 type_data.ertd_es_super_buffer.eessb_buf_stride = buf_stride;
875 type_data.ertd_es_super_buffer.eessb_hol_block_timeout =
878 rc = efx_rx_qcreate_internal(enp, index, label,
879 EFX_RXQ_TYPE_ES_SUPER_BUFFER, &type_data, esmp, ndescs,
880 0 /* id unused on EF10 */, flags, eep, erpp);
889 EFSYS_PROBE1(fail1, efx_rc_t, rc);
901 efx_nic_t *enp = erp->er_enp;
902 const efx_rx_ops_t *erxop = enp->en_erxop;
904 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
906 erxop->erxo_qdestroy(erp);
909 __checkReturn efx_rc_t
910 efx_pseudo_hdr_pkt_length_get(
912 __in uint8_t *buffer,
913 __out uint16_t *lengthp)
915 efx_nic_t *enp = erp->er_enp;
916 const efx_rx_ops_t *erxop = enp->en_erxop;
918 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
920 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
923 #if EFSYS_OPT_RX_SCALE
924 __checkReturn uint32_t
925 efx_pseudo_hdr_hash_get(
927 __in efx_rx_hash_alg_t func,
928 __in uint8_t *buffer)
930 efx_nic_t *enp = erp->er_enp;
931 const efx_rx_ops_t *erxop = enp->en_erxop;
933 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
935 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
936 return (erxop->erxo_prefix_hash(enp, func, buffer));
938 #endif /* EFSYS_OPT_RX_SCALE */
942 static __checkReturn efx_rc_t
949 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
951 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
952 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
953 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
954 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
955 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
956 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
957 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
959 /* Zero the RSS table */
960 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
962 EFX_ZERO_OWORD(oword);
963 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
964 index, &oword, B_TRUE);
967 #if EFSYS_OPT_RX_SCALE
968 /* The RSS key and indirection table are writable. */
969 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
971 /* Hardware can insert RX hash with/without RSS */
972 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
973 #endif /* EFSYS_OPT_RX_SCALE */
978 #if EFSYS_OPT_RX_SCATTER
979 static __checkReturn efx_rc_t
980 siena_rx_scatter_enable(
982 __in unsigned int buf_size)
988 nbuf32 = buf_size / 32;
990 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
991 ((buf_size % 32) != 0)) {
996 if (enp->en_rx_qcount > 0) {
1001 /* Set scatter buffer size */
1002 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
1003 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
1004 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
1006 /* Enable scatter for packets not matching a filter */
1007 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
1008 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
1009 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
1016 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1020 #endif /* EFSYS_OPT_RX_SCATTER */
1023 #define EFX_RX_LFSR_HASH(_enp, _insert) \
1025 efx_oword_t oword; \
1027 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1028 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
1029 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
1030 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
1031 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
1032 (_insert) ? 1 : 0); \
1033 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1035 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
1036 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
1038 EFX_SET_OWORD_FIELD(oword, \
1039 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
1040 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
1044 _NOTE(CONSTANTCONDITION) \
1047 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
1049 efx_oword_t oword; \
1051 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1052 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
1053 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
1055 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
1057 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
1058 (_insert) ? 1 : 0); \
1059 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1061 _NOTE(CONSTANTCONDITION) \
1064 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
1066 efx_oword_t oword; \
1068 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1069 EFX_SET_OWORD_FIELD(oword, \
1070 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
1071 EFX_SET_OWORD_FIELD(oword, \
1072 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
1073 EFX_SET_OWORD_FIELD(oword, \
1074 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
1075 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1079 _NOTE(CONSTANTCONDITION) \
1083 #if EFSYS_OPT_RX_SCALE
1085 static __checkReturn efx_rc_t
1086 siena_rx_scale_mode_set(
1087 __in efx_nic_t *enp,
1088 __in uint32_t rss_context,
1089 __in efx_rx_hash_alg_t alg,
1090 __in efx_rx_hash_type_t type,
1091 __in boolean_t insert)
1093 efx_rx_hash_type_t type_ipv4 = EFX_RX_HASH(IPV4, 2TUPLE);
1094 efx_rx_hash_type_t type_ipv4_tcp = EFX_RX_HASH(IPV4_TCP, 4TUPLE);
1095 efx_rx_hash_type_t type_ipv6 = EFX_RX_HASH(IPV6, 2TUPLE);
1096 efx_rx_hash_type_t type_ipv6_tcp = EFX_RX_HASH(IPV6_TCP, 4TUPLE);
1099 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1105 case EFX_RX_HASHALG_LFSR:
1106 EFX_RX_LFSR_HASH(enp, insert);
1109 case EFX_RX_HASHALG_TOEPLITZ:
1110 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
1111 (type & type_ipv4) == type_ipv4,
1112 (type & type_ipv4_tcp) == type_ipv4_tcp);
1114 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
1115 (type & type_ipv6) == type_ipv6,
1116 (type & type_ipv6_tcp) == type_ipv6_tcp,
1135 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1137 EFX_RX_LFSR_HASH(enp, B_FALSE);
1143 #if EFSYS_OPT_RX_SCALE
1144 static __checkReturn efx_rc_t
1145 siena_rx_scale_key_set(
1146 __in efx_nic_t *enp,
1147 __in uint32_t rss_context,
1148 __in_ecount(n) uint8_t *key,
1153 unsigned int offset;
1156 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1163 /* Write Toeplitz IPv4 hash key */
1164 EFX_ZERO_OWORD(oword);
1165 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1166 offset > 0 && byte < n;
1168 oword.eo_u8[offset - 1] = key[byte++];
1170 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1174 /* Verify Toeplitz IPv4 hash key */
1175 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1176 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1177 offset > 0 && byte < n;
1179 if (oword.eo_u8[offset - 1] != key[byte++]) {
1185 if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
1190 /* Write Toeplitz IPv6 hash key 3 */
1191 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1192 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1193 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1194 offset > 0 && byte < n;
1196 oword.eo_u8[offset - 1] = key[byte++];
1198 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1200 /* Write Toeplitz IPv6 hash key 2 */
1201 EFX_ZERO_OWORD(oword);
1202 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1203 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1204 offset > 0 && byte < n;
1206 oword.eo_u8[offset - 1] = key[byte++];
1208 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1210 /* Write Toeplitz IPv6 hash key 1 */
1211 EFX_ZERO_OWORD(oword);
1212 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1213 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1214 offset > 0 && byte < n;
1216 oword.eo_u8[offset - 1] = key[byte++];
1218 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1222 /* Verify Toeplitz IPv6 hash key 3 */
1223 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1224 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1225 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1226 offset > 0 && byte < n;
1228 if (oword.eo_u8[offset - 1] != key[byte++]) {
1234 /* Verify Toeplitz IPv6 hash key 2 */
1235 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1236 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1237 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1238 offset > 0 && byte < n;
1240 if (oword.eo_u8[offset - 1] != key[byte++]) {
1246 /* Verify Toeplitz IPv6 hash key 1 */
1247 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1248 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1249 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1250 offset > 0 && byte < n;
1252 if (oword.eo_u8[offset - 1] != key[byte++]) {
1270 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1276 #if EFSYS_OPT_RX_SCALE
1277 static __checkReturn efx_rc_t
1278 siena_rx_scale_tbl_set(
1279 __in efx_nic_t *enp,
1280 __in uint32_t rss_context,
1281 __in_ecount(n) unsigned int *table,
1288 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
1289 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
1291 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1296 if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
1301 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
1304 /* Calculate the entry to place in the table */
1305 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1307 EFSYS_PROBE2(table, int, index, uint32_t, byte);
1309 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
1311 /* Write the table */
1312 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1313 index, &oword, B_TRUE);
1316 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
1319 /* Determine if we're starting a new batch */
1320 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1322 /* Read the table */
1323 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
1324 index, &oword, B_TRUE);
1326 /* Verify the entry */
1327 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1340 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1347 * Falcon/Siena pseudo-header
1348 * --------------------------
1350 * Receive packets are prefixed by an optional 16 byte pseudo-header.
1351 * The pseudo-header is a byte array of one of the forms:
1353 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1354 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1355 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1358 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
1359 * LL.LL LFSR hash (16-bit big-endian)
1362 #if EFSYS_OPT_RX_SCALE
1363 static __checkReturn uint32_t
1364 siena_rx_prefix_hash(
1365 __in efx_nic_t *enp,
1366 __in efx_rx_hash_alg_t func,
1367 __in uint8_t *buffer)
1369 _NOTE(ARGUNUSED(enp))
1372 case EFX_RX_HASHALG_TOEPLITZ:
1373 return ((buffer[12] << 24) |
1374 (buffer[13] << 16) |
1378 case EFX_RX_HASHALG_LFSR:
1379 return ((buffer[14] << 8) | buffer[15]);
1386 #endif /* EFSYS_OPT_RX_SCALE */
1388 static __checkReturn efx_rc_t
1389 siena_rx_prefix_pktlen(
1390 __in efx_nic_t *enp,
1391 __in uint8_t *buffer,
1392 __out uint16_t *lengthp)
1394 _NOTE(ARGUNUSED(enp, buffer, lengthp))
1396 /* Not supported by Falcon/Siena hardware */
1404 __in efx_rxq_t *erp,
1405 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1407 __in unsigned int ndescs,
1408 __in unsigned int completed,
1409 __in unsigned int added)
1413 unsigned int offset;
1416 /* The client driver must not overfill the queue */
1417 EFSYS_ASSERT3U(added - completed + ndescs, <=,
1418 EFX_RXQ_LIMIT(erp->er_mask + 1));
1420 id = added & (erp->er_mask);
1421 for (i = 0; i < ndescs; i++) {
1422 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1423 unsigned int, id, efsys_dma_addr_t, addrp[i],
1426 EFX_POPULATE_QWORD_3(qword,
1427 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1428 FSF_AZ_RX_KER_BUF_ADDR_DW0,
1429 (uint32_t)(addrp[i] & 0xffffffff),
1430 FSF_AZ_RX_KER_BUF_ADDR_DW1,
1431 (uint32_t)(addrp[i] >> 32));
1433 offset = id * sizeof (efx_qword_t);
1434 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1436 id = (id + 1) & (erp->er_mask);
1442 __in efx_rxq_t *erp,
1443 __in unsigned int added,
1444 __inout unsigned int *pushedp)
1446 efx_nic_t *enp = erp->er_enp;
1447 unsigned int pushed = *pushedp;
1452 /* All descriptors are pushed */
1455 /* Push the populated descriptors out */
1456 wptr = added & erp->er_mask;
1458 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1460 /* Only write the third DWORD */
1461 EFX_POPULATE_DWORD_1(dword,
1462 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1464 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1465 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1466 wptr, pushed & erp->er_mask);
1467 EFSYS_PIO_WRITE_BARRIER();
1468 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1469 erp->er_index, &dword, B_FALSE);
1472 #if EFSYS_OPT_RX_PACKED_STREAM
1474 siena_rx_qpush_ps_credits(
1475 __in efx_rxq_t *erp)
1477 /* Not supported by Siena hardware */
1482 siena_rx_qps_packet_info(
1483 __in efx_rxq_t *erp,
1484 __in uint8_t *buffer,
1485 __in uint32_t buffer_length,
1486 __in uint32_t current_offset,
1487 __out uint16_t *lengthp,
1488 __out uint32_t *next_offsetp,
1489 __out uint32_t *timestamp)
1491 /* Not supported by Siena hardware */
1496 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1498 static __checkReturn efx_rc_t
1500 __in efx_rxq_t *erp)
1502 efx_nic_t *enp = erp->er_enp;
1506 label = erp->er_index;
1508 /* Flush the queue */
1509 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1510 FRF_AZ_RX_FLUSH_DESCQ, label);
1511 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1518 __in efx_rxq_t *erp)
1520 efx_nic_t *enp = erp->er_enp;
1523 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1525 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1526 erp->er_index, &oword, B_TRUE);
1528 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1529 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1530 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1532 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1533 erp->er_index, &oword, B_TRUE);
1536 static __checkReturn efx_rc_t
1538 __in efx_nic_t *enp,
1539 __in unsigned int index,
1540 __in unsigned int label,
1541 __in efx_rxq_type_t type,
1542 __in const efx_rxq_type_data_t *type_data,
1543 __in efsys_mem_t *esmp,
1546 __in unsigned int flags,
1547 __in efx_evq_t *eep,
1548 __in efx_rxq_t *erp)
1550 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1553 boolean_t jumbo = B_FALSE;
1556 _NOTE(ARGUNUSED(esmp))
1557 _NOTE(ARGUNUSED(type_data))
1559 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1560 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1561 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1562 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1564 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1565 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1567 if (!ISP2(ndescs) ||
1568 (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
1572 if (index >= encp->enc_rxq_limit) {
1576 for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1578 if ((1 << size) == (int)(ndescs / EFX_RXQ_MINNDESCS))
1580 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1586 case EFX_RXQ_TYPE_DEFAULT:
1594 if (flags & EFX_RXQ_FLAG_SCATTER) {
1595 #if EFSYS_OPT_RX_SCATTER
1600 #endif /* EFSYS_OPT_RX_SCATTER */
1603 /* Set up the new descriptor queue */
1604 EFX_POPULATE_OWORD_7(oword,
1605 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1606 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1607 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1608 FRF_AZ_RX_DESCQ_LABEL, label,
1609 FRF_AZ_RX_DESCQ_SIZE, size,
1610 FRF_AZ_RX_DESCQ_TYPE, 0,
1611 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1613 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1614 erp->er_index, &oword, B_TRUE);
1618 #if !EFSYS_OPT_RX_SCATTER
1629 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1636 __in efx_rxq_t *erp)
1638 efx_nic_t *enp = erp->er_enp;
1641 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1642 --enp->en_rx_qcount;
1644 /* Purge descriptor queue */
1645 EFX_ZERO_OWORD(oword);
1647 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1648 erp->er_index, &oword, B_TRUE);
1650 /* Free the RXQ object */
1651 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1656 __in efx_nic_t *enp)
1658 _NOTE(ARGUNUSED(enp))
1661 #endif /* EFSYS_OPT_SIENA */