2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
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11 * this list of conditions and the following disclaimer in the documentation
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37 static __checkReturn efx_rc_t
45 static __checkReturn efx_rc_t
46 siena_rx_prefix_pktlen(
49 __out uint16_t *lengthp);
54 __in_ecount(n) efsys_dma_addr_t *addrp,
57 __in unsigned int completed,
58 __in unsigned int added);
63 __in unsigned int added,
64 __inout unsigned int *pushedp);
66 static __checkReturn efx_rc_t
74 static __checkReturn efx_rc_t
77 __in unsigned int index,
78 __in unsigned int label,
79 __in efx_rxq_type_t type,
80 __in efsys_mem_t *esmp,
90 #endif /* EFSYS_OPT_SIENA */
94 static const efx_rx_ops_t __efx_rx_siena_ops = {
95 siena_rx_init, /* erxo_init */
96 siena_rx_fini, /* erxo_fini */
97 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
98 siena_rx_qpost, /* erxo_qpost */
99 siena_rx_qpush, /* erxo_qpush */
100 siena_rx_qflush, /* erxo_qflush */
101 siena_rx_qenable, /* erxo_qenable */
102 siena_rx_qcreate, /* erxo_qcreate */
103 siena_rx_qdestroy, /* erxo_qdestroy */
105 #endif /* EFSYS_OPT_SIENA */
107 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
108 static const efx_rx_ops_t __efx_rx_ef10_ops = {
109 ef10_rx_init, /* erxo_init */
110 ef10_rx_fini, /* erxo_fini */
111 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
112 ef10_rx_qpost, /* erxo_qpost */
113 ef10_rx_qpush, /* erxo_qpush */
114 ef10_rx_qflush, /* erxo_qflush */
115 ef10_rx_qenable, /* erxo_qenable */
116 ef10_rx_qcreate, /* erxo_qcreate */
117 ef10_rx_qdestroy, /* erxo_qdestroy */
119 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
122 __checkReturn efx_rc_t
124 __inout efx_nic_t *enp)
126 const efx_rx_ops_t *erxop;
129 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
130 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
132 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
137 if (enp->en_mod_flags & EFX_MOD_RX) {
142 switch (enp->en_family) {
144 case EFX_FAMILY_SIENA:
145 erxop = &__efx_rx_siena_ops;
147 #endif /* EFSYS_OPT_SIENA */
149 #if EFSYS_OPT_HUNTINGTON
150 case EFX_FAMILY_HUNTINGTON:
151 erxop = &__efx_rx_ef10_ops;
153 #endif /* EFSYS_OPT_HUNTINGTON */
155 #if EFSYS_OPT_MEDFORD
156 case EFX_FAMILY_MEDFORD:
157 erxop = &__efx_rx_ef10_ops;
159 #endif /* EFSYS_OPT_MEDFORD */
167 if ((rc = erxop->erxo_init(enp)) != 0)
170 enp->en_erxop = erxop;
171 enp->en_mod_flags |= EFX_MOD_RX;
181 EFSYS_PROBE1(fail1, efx_rc_t, rc);
183 enp->en_erxop = NULL;
184 enp->en_mod_flags &= ~EFX_MOD_RX;
192 const efx_rx_ops_t *erxop = enp->en_erxop;
194 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
195 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
196 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
197 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
199 erxop->erxo_fini(enp);
201 enp->en_erxop = NULL;
202 enp->en_mod_flags &= ~EFX_MOD_RX;
208 __in_ecount(n) efsys_dma_addr_t *addrp,
211 __in unsigned int completed,
212 __in unsigned int added)
214 efx_nic_t *enp = erp->er_enp;
215 const efx_rx_ops_t *erxop = enp->en_erxop;
217 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
219 erxop->erxo_qpost(erp, addrp, size, n, completed, added);
225 __in unsigned int added,
226 __inout unsigned int *pushedp)
228 efx_nic_t *enp = erp->er_enp;
229 const efx_rx_ops_t *erxop = enp->en_erxop;
231 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
233 erxop->erxo_qpush(erp, added, pushedp);
236 __checkReturn efx_rc_t
240 efx_nic_t *enp = erp->er_enp;
241 const efx_rx_ops_t *erxop = enp->en_erxop;
244 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
246 if ((rc = erxop->erxo_qflush(erp)) != 0)
252 EFSYS_PROBE1(fail1, efx_rc_t, rc);
261 efx_nic_t *enp = erp->er_enp;
262 const efx_rx_ops_t *erxop = enp->en_erxop;
264 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
266 erxop->erxo_qenable(erp);
269 __checkReturn efx_rc_t
272 __in unsigned int index,
273 __in unsigned int label,
274 __in efx_rxq_type_t type,
275 __in efsys_mem_t *esmp,
279 __deref_out efx_rxq_t **erpp)
281 const efx_rx_ops_t *erxop = enp->en_erxop;
285 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
286 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
288 /* Allocate an RXQ object */
289 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
296 erp->er_magic = EFX_RXQ_MAGIC;
298 erp->er_index = index;
299 erp->er_mask = n - 1;
302 if ((rc = erxop->erxo_qcreate(enp, index, label, type, esmp, n, id,
314 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
316 EFSYS_PROBE1(fail1, efx_rc_t, rc);
325 efx_nic_t *enp = erp->er_enp;
326 const efx_rx_ops_t *erxop = enp->en_erxop;
328 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
330 erxop->erxo_qdestroy(erp);
333 __checkReturn efx_rc_t
334 efx_pseudo_hdr_pkt_length_get(
336 __in uint8_t *buffer,
337 __out uint16_t *lengthp)
339 efx_nic_t *enp = erp->er_enp;
340 const efx_rx_ops_t *erxop = enp->en_erxop;
342 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
344 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
349 static __checkReturn efx_rc_t
356 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
358 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
359 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
360 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
361 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
362 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
363 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
364 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
366 /* Zero the RSS table */
367 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
369 EFX_ZERO_OWORD(oword);
370 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
371 index, &oword, B_TRUE);
378 #define EFX_RX_LFSR_HASH(_enp, _insert) \
382 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
383 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
384 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
385 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
386 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
387 (_insert) ? 1 : 0); \
388 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
390 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
391 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
393 EFX_SET_OWORD_FIELD(oword, \
394 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
395 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
399 _NOTE(CONSTANTCONDITION) \
402 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
406 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
407 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
408 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
410 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
412 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
413 (_insert) ? 1 : 0); \
414 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
416 _NOTE(CONSTANTCONDITION) \
419 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
423 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
424 EFX_SET_OWORD_FIELD(oword, \
425 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
426 EFX_SET_OWORD_FIELD(oword, \
427 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
428 EFX_SET_OWORD_FIELD(oword, \
429 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
430 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
434 _NOTE(CONSTANTCONDITION) \
439 * Falcon/Siena pseudo-header
440 * --------------------------
442 * Receive packets are prefixed by an optional 16 byte pseudo-header.
443 * The pseudo-header is a byte array of one of the forms:
445 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
446 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
447 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
450 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
451 * LL.LL LFSR hash (16-bit big-endian)
454 static __checkReturn efx_rc_t
455 siena_rx_prefix_pktlen(
457 __in uint8_t *buffer,
458 __out uint16_t *lengthp)
460 _NOTE(ARGUNUSED(enp, buffer, lengthp))
462 /* Not supported by Falcon/Siena hardware */
471 __in_ecount(n) efsys_dma_addr_t *addrp,
474 __in unsigned int completed,
475 __in unsigned int added)
482 /* The client driver must not overfill the queue */
483 EFSYS_ASSERT3U(added - completed + n, <=,
484 EFX_RXQ_LIMIT(erp->er_mask + 1));
486 id = added & (erp->er_mask);
487 for (i = 0; i < n; i++) {
488 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
489 unsigned int, id, efsys_dma_addr_t, addrp[i],
492 EFX_POPULATE_QWORD_3(qword,
493 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
494 FSF_AZ_RX_KER_BUF_ADDR_DW0,
495 (uint32_t)(addrp[i] & 0xffffffff),
496 FSF_AZ_RX_KER_BUF_ADDR_DW1,
497 (uint32_t)(addrp[i] >> 32));
499 offset = id * sizeof (efx_qword_t);
500 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
502 id = (id + 1) & (erp->er_mask);
509 __in unsigned int added,
510 __inout unsigned int *pushedp)
512 efx_nic_t *enp = erp->er_enp;
513 unsigned int pushed = *pushedp;
518 /* All descriptors are pushed */
521 /* Push the populated descriptors out */
522 wptr = added & erp->er_mask;
524 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
526 /* Only write the third DWORD */
527 EFX_POPULATE_DWORD_1(dword,
528 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
530 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
531 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
532 wptr, pushed & erp->er_mask);
533 EFSYS_PIO_WRITE_BARRIER();
534 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
535 erp->er_index, &dword, B_FALSE);
538 static __checkReturn efx_rc_t
542 efx_nic_t *enp = erp->er_enp;
546 label = erp->er_index;
548 /* Flush the queue */
549 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
550 FRF_AZ_RX_FLUSH_DESCQ, label);
551 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
560 efx_nic_t *enp = erp->er_enp;
563 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
565 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
566 erp->er_index, &oword, B_TRUE);
568 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
569 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
570 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
572 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
573 erp->er_index, &oword, B_TRUE);
576 static __checkReturn efx_rc_t
579 __in unsigned int index,
580 __in unsigned int label,
581 __in efx_rxq_type_t type,
582 __in efsys_mem_t *esmp,
588 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
594 _NOTE(ARGUNUSED(esmp))
596 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
597 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
598 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
599 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
601 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
602 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
604 if (!ISP2(n) || (n < EFX_RXQ_MINNDESCS) || (n > EFX_RXQ_MAXNDESCS)) {
608 if (index >= encp->enc_rxq_limit) {
612 for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
614 if ((1 << size) == (int)(n / EFX_RXQ_MINNDESCS))
616 if (id + (1 << size) >= encp->enc_buftbl_limit) {
622 case EFX_RXQ_TYPE_DEFAULT:
631 /* Set up the new descriptor queue */
632 EFX_POPULATE_OWORD_7(oword,
633 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
634 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
635 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
636 FRF_AZ_RX_DESCQ_LABEL, label,
637 FRF_AZ_RX_DESCQ_SIZE, size,
638 FRF_AZ_RX_DESCQ_TYPE, 0,
639 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
641 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
642 erp->er_index, &oword, B_TRUE);
653 EFSYS_PROBE1(fail1, efx_rc_t, rc);
662 efx_nic_t *enp = erp->er_enp;
665 EFSYS_ASSERT(enp->en_rx_qcount != 0);
668 /* Purge descriptor queue */
669 EFX_ZERO_OWORD(oword);
671 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
672 erp->er_index, &oword, B_TRUE);
674 /* Free the RXQ object */
675 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
682 _NOTE(ARGUNUSED(enp))
685 #endif /* EFSYS_OPT_SIENA */