2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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28 * policies, either expressed or implied, of the FreeBSD Project.
37 static __checkReturn efx_rc_t
45 #if EFSYS_OPT_RX_SCATTER
46 static __checkReturn efx_rc_t
47 siena_rx_scatter_enable(
49 __in unsigned int buf_size);
50 #endif /* EFSYS_OPT_RX_SCATTER */
52 #if EFSYS_OPT_RX_SCALE
53 static __checkReturn efx_rc_t
54 siena_rx_scale_mode_set(
56 __in uint32_t rss_context,
57 __in efx_rx_hash_alg_t alg,
58 __in efx_rx_hash_type_t type,
59 __in boolean_t insert);
61 static __checkReturn efx_rc_t
62 siena_rx_scale_key_set(
64 __in uint32_t rss_context,
65 __in_ecount(n) uint8_t *key,
68 static __checkReturn efx_rc_t
69 siena_rx_scale_tbl_set(
71 __in uint32_t rss_context,
72 __in_ecount(n) unsigned int *table,
75 static __checkReturn uint32_t
78 __in efx_rx_hash_alg_t func,
79 __in uint8_t *buffer);
81 #endif /* EFSYS_OPT_RX_SCALE */
83 static __checkReturn efx_rc_t
84 siena_rx_prefix_pktlen(
87 __out uint16_t *lengthp);
92 __in_ecount(n) efsys_dma_addr_t *addrp,
95 __in unsigned int completed,
96 __in unsigned int added);
101 __in unsigned int added,
102 __inout unsigned int *pushedp);
104 #if EFSYS_OPT_RX_PACKED_STREAM
106 siena_rx_qps_update_credits(
107 __in efx_rxq_t *erp);
109 static __checkReturn uint8_t *
110 siena_rx_qps_packet_info(
112 __in uint8_t *buffer,
113 __in uint32_t buffer_length,
114 __in uint32_t current_offset,
115 __out uint16_t *lengthp,
116 __out uint32_t *next_offsetp,
117 __out uint32_t *timestamp);
120 static __checkReturn efx_rc_t
122 __in efx_rxq_t *erp);
126 __in efx_rxq_t *erp);
128 static __checkReturn efx_rc_t
131 __in unsigned int index,
132 __in unsigned int label,
133 __in efx_rxq_type_t type,
134 __in efsys_mem_t *esmp,
138 __in efx_rxq_t *erp);
142 __in efx_rxq_t *erp);
144 #endif /* EFSYS_OPT_SIENA */
148 static const efx_rx_ops_t __efx_rx_siena_ops = {
149 siena_rx_init, /* erxo_init */
150 siena_rx_fini, /* erxo_fini */
151 #if EFSYS_OPT_RX_SCATTER
152 siena_rx_scatter_enable, /* erxo_scatter_enable */
154 #if EFSYS_OPT_RX_SCALE
155 NULL, /* erxo_scale_context_alloc */
156 NULL, /* erxo_scale_context_free */
157 siena_rx_scale_mode_set, /* erxo_scale_mode_set */
158 siena_rx_scale_key_set, /* erxo_scale_key_set */
159 siena_rx_scale_tbl_set, /* erxo_scale_tbl_set */
160 siena_rx_prefix_hash, /* erxo_prefix_hash */
162 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
163 siena_rx_qpost, /* erxo_qpost */
164 siena_rx_qpush, /* erxo_qpush */
165 #if EFSYS_OPT_RX_PACKED_STREAM
166 siena_rx_qps_update_credits, /* erxo_qps_update_credits */
167 siena_rx_qps_packet_info, /* erxo_qps_packet_info */
169 siena_rx_qflush, /* erxo_qflush */
170 siena_rx_qenable, /* erxo_qenable */
171 siena_rx_qcreate, /* erxo_qcreate */
172 siena_rx_qdestroy, /* erxo_qdestroy */
174 #endif /* EFSYS_OPT_SIENA */
176 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
177 static const efx_rx_ops_t __efx_rx_ef10_ops = {
178 ef10_rx_init, /* erxo_init */
179 ef10_rx_fini, /* erxo_fini */
180 #if EFSYS_OPT_RX_SCATTER
181 ef10_rx_scatter_enable, /* erxo_scatter_enable */
183 #if EFSYS_OPT_RX_SCALE
184 ef10_rx_scale_context_alloc, /* erxo_scale_context_alloc */
185 ef10_rx_scale_context_free, /* erxo_scale_context_free */
186 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */
187 ef10_rx_scale_key_set, /* erxo_scale_key_set */
188 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */
189 ef10_rx_prefix_hash, /* erxo_prefix_hash */
191 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
192 ef10_rx_qpost, /* erxo_qpost */
193 ef10_rx_qpush, /* erxo_qpush */
194 #if EFSYS_OPT_RX_PACKED_STREAM
195 ef10_rx_qps_update_credits, /* erxo_qps_update_credits */
196 ef10_rx_qps_packet_info, /* erxo_qps_packet_info */
198 ef10_rx_qflush, /* erxo_qflush */
199 ef10_rx_qenable, /* erxo_qenable */
200 ef10_rx_qcreate, /* erxo_qcreate */
201 ef10_rx_qdestroy, /* erxo_qdestroy */
203 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
206 __checkReturn efx_rc_t
208 __inout efx_nic_t *enp)
210 const efx_rx_ops_t *erxop;
213 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
214 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
216 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
221 if (enp->en_mod_flags & EFX_MOD_RX) {
226 switch (enp->en_family) {
228 case EFX_FAMILY_SIENA:
229 erxop = &__efx_rx_siena_ops;
231 #endif /* EFSYS_OPT_SIENA */
233 #if EFSYS_OPT_HUNTINGTON
234 case EFX_FAMILY_HUNTINGTON:
235 erxop = &__efx_rx_ef10_ops;
237 #endif /* EFSYS_OPT_HUNTINGTON */
239 #if EFSYS_OPT_MEDFORD
240 case EFX_FAMILY_MEDFORD:
241 erxop = &__efx_rx_ef10_ops;
243 #endif /* EFSYS_OPT_MEDFORD */
251 if ((rc = erxop->erxo_init(enp)) != 0)
254 enp->en_erxop = erxop;
255 enp->en_mod_flags |= EFX_MOD_RX;
265 EFSYS_PROBE1(fail1, efx_rc_t, rc);
267 enp->en_erxop = NULL;
268 enp->en_mod_flags &= ~EFX_MOD_RX;
276 const efx_rx_ops_t *erxop = enp->en_erxop;
278 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
279 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
280 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
281 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
283 erxop->erxo_fini(enp);
285 enp->en_erxop = NULL;
286 enp->en_mod_flags &= ~EFX_MOD_RX;
289 #if EFSYS_OPT_RX_SCATTER
290 __checkReturn efx_rc_t
291 efx_rx_scatter_enable(
293 __in unsigned int buf_size)
295 const efx_rx_ops_t *erxop = enp->en_erxop;
298 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
299 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
301 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
307 EFSYS_PROBE1(fail1, efx_rc_t, rc);
310 #endif /* EFSYS_OPT_RX_SCATTER */
312 #if EFSYS_OPT_RX_SCALE
313 __checkReturn efx_rc_t
314 efx_rx_hash_default_support_get(
316 __out efx_rx_hash_support_t *supportp)
320 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
321 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
323 if (supportp == NULL) {
329 * Report the hashing support the client gets by default if it
330 * does not allocate an RSS context itself.
332 *supportp = enp->en_hash_support;
337 EFSYS_PROBE1(fail1, efx_rc_t, rc);
342 __checkReturn efx_rc_t
343 efx_rx_scale_default_support_get(
345 __out efx_rx_scale_context_type_t *typep)
349 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
350 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
358 * Report the RSS support the client gets by default if it
359 * does not allocate an RSS context itself.
361 *typep = enp->en_rss_context_type;
366 EFSYS_PROBE1(fail1, efx_rc_t, rc);
370 #endif /* EFSYS_OPT_RX_SCALE */
372 #if EFSYS_OPT_RX_SCALE
373 __checkReturn efx_rc_t
374 efx_rx_scale_context_alloc(
376 __in efx_rx_scale_context_type_t type,
377 __in uint32_t num_queues,
378 __out uint32_t *rss_contextp)
380 const efx_rx_ops_t *erxop = enp->en_erxop;
383 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
384 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
386 if (erxop->erxo_scale_context_alloc == NULL) {
390 if ((rc = erxop->erxo_scale_context_alloc(enp, type,
391 num_queues, rss_contextp)) != 0) {
400 EFSYS_PROBE1(fail1, efx_rc_t, rc);
403 #endif /* EFSYS_OPT_RX_SCALE */
405 #if EFSYS_OPT_RX_SCALE
406 __checkReturn efx_rc_t
407 efx_rx_scale_context_free(
409 __in uint32_t rss_context)
411 const efx_rx_ops_t *erxop = enp->en_erxop;
414 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
415 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
417 if (erxop->erxo_scale_context_free == NULL) {
421 if ((rc = erxop->erxo_scale_context_free(enp, rss_context)) != 0)
429 EFSYS_PROBE1(fail1, efx_rc_t, rc);
432 #endif /* EFSYS_OPT_RX_SCALE */
434 #if EFSYS_OPT_RX_SCALE
435 __checkReturn efx_rc_t
436 efx_rx_scale_mode_set(
438 __in uint32_t rss_context,
439 __in efx_rx_hash_alg_t alg,
440 __in efx_rx_hash_type_t type,
441 __in boolean_t insert)
443 const efx_rx_ops_t *erxop = enp->en_erxop;
446 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
447 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
449 if (erxop->erxo_scale_mode_set != NULL) {
450 if ((rc = erxop->erxo_scale_mode_set(enp, rss_context, alg,
458 EFSYS_PROBE1(fail1, efx_rc_t, rc);
461 #endif /* EFSYS_OPT_RX_SCALE */
463 #if EFSYS_OPT_RX_SCALE
464 __checkReturn efx_rc_t
465 efx_rx_scale_key_set(
467 __in uint32_t rss_context,
468 __in_ecount(n) uint8_t *key,
471 const efx_rx_ops_t *erxop = enp->en_erxop;
474 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
475 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
477 if ((rc = erxop->erxo_scale_key_set(enp, rss_context, key, n)) != 0)
483 EFSYS_PROBE1(fail1, efx_rc_t, rc);
487 #endif /* EFSYS_OPT_RX_SCALE */
489 #if EFSYS_OPT_RX_SCALE
490 __checkReturn efx_rc_t
491 efx_rx_scale_tbl_set(
493 __in uint32_t rss_context,
494 __in_ecount(n) unsigned int *table,
497 const efx_rx_ops_t *erxop = enp->en_erxop;
500 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
501 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
503 if ((rc = erxop->erxo_scale_tbl_set(enp, rss_context, table, n)) != 0)
509 EFSYS_PROBE1(fail1, efx_rc_t, rc);
513 #endif /* EFSYS_OPT_RX_SCALE */
518 __in_ecount(n) efsys_dma_addr_t *addrp,
521 __in unsigned int completed,
522 __in unsigned int added)
524 efx_nic_t *enp = erp->er_enp;
525 const efx_rx_ops_t *erxop = enp->en_erxop;
527 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
529 erxop->erxo_qpost(erp, addrp, size, n, completed, added);
532 #if EFSYS_OPT_RX_PACKED_STREAM
535 efx_rx_qps_update_credits(
538 efx_nic_t *enp = erp->er_enp;
539 const efx_rx_ops_t *erxop = enp->en_erxop;
541 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
543 erxop->erxo_qps_update_credits(erp);
546 __checkReturn uint8_t *
547 efx_rx_qps_packet_info(
549 __in uint8_t *buffer,
550 __in uint32_t buffer_length,
551 __in uint32_t current_offset,
552 __out uint16_t *lengthp,
553 __out uint32_t *next_offsetp,
554 __out uint32_t *timestamp)
556 efx_nic_t *enp = erp->er_enp;
557 const efx_rx_ops_t *erxop = enp->en_erxop;
559 return (erxop->erxo_qps_packet_info(erp, buffer,
560 buffer_length, current_offset, lengthp,
561 next_offsetp, timestamp));
564 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
569 __in unsigned int added,
570 __inout unsigned int *pushedp)
572 efx_nic_t *enp = erp->er_enp;
573 const efx_rx_ops_t *erxop = enp->en_erxop;
575 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
577 erxop->erxo_qpush(erp, added, pushedp);
580 __checkReturn efx_rc_t
584 efx_nic_t *enp = erp->er_enp;
585 const efx_rx_ops_t *erxop = enp->en_erxop;
588 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
590 if ((rc = erxop->erxo_qflush(erp)) != 0)
596 EFSYS_PROBE1(fail1, efx_rc_t, rc);
605 efx_nic_t *enp = erp->er_enp;
606 const efx_rx_ops_t *erxop = enp->en_erxop;
608 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
610 erxop->erxo_qenable(erp);
613 __checkReturn efx_rc_t
616 __in unsigned int index,
617 __in unsigned int label,
618 __in efx_rxq_type_t type,
619 __in efsys_mem_t *esmp,
623 __deref_out efx_rxq_t **erpp)
625 const efx_rx_ops_t *erxop = enp->en_erxop;
629 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
630 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
632 /* Allocate an RXQ object */
633 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
640 erp->er_magic = EFX_RXQ_MAGIC;
642 erp->er_index = index;
643 erp->er_mask = n - 1;
646 if ((rc = erxop->erxo_qcreate(enp, index, label, type, esmp, n, id,
658 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
660 EFSYS_PROBE1(fail1, efx_rc_t, rc);
669 efx_nic_t *enp = erp->er_enp;
670 const efx_rx_ops_t *erxop = enp->en_erxop;
672 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
674 erxop->erxo_qdestroy(erp);
677 __checkReturn efx_rc_t
678 efx_pseudo_hdr_pkt_length_get(
680 __in uint8_t *buffer,
681 __out uint16_t *lengthp)
683 efx_nic_t *enp = erp->er_enp;
684 const efx_rx_ops_t *erxop = enp->en_erxop;
686 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
688 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
691 #if EFSYS_OPT_RX_SCALE
692 __checkReturn uint32_t
693 efx_pseudo_hdr_hash_get(
695 __in efx_rx_hash_alg_t func,
696 __in uint8_t *buffer)
698 efx_nic_t *enp = erp->er_enp;
699 const efx_rx_ops_t *erxop = enp->en_erxop;
701 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
703 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
704 return (erxop->erxo_prefix_hash(enp, func, buffer));
706 #endif /* EFSYS_OPT_RX_SCALE */
710 static __checkReturn efx_rc_t
717 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
719 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
720 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
721 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
722 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
723 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
724 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
725 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
727 /* Zero the RSS table */
728 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
730 EFX_ZERO_OWORD(oword);
731 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
732 index, &oword, B_TRUE);
735 #if EFSYS_OPT_RX_SCALE
736 /* The RSS key and indirection table are writable. */
737 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
739 /* Hardware can insert RX hash with/without RSS */
740 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
741 #endif /* EFSYS_OPT_RX_SCALE */
746 #if EFSYS_OPT_RX_SCATTER
747 static __checkReturn efx_rc_t
748 siena_rx_scatter_enable(
750 __in unsigned int buf_size)
756 nbuf32 = buf_size / 32;
758 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
759 ((buf_size % 32) != 0)) {
764 if (enp->en_rx_qcount > 0) {
769 /* Set scatter buffer size */
770 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
771 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
772 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
774 /* Enable scatter for packets not matching a filter */
775 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
776 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
777 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
784 EFSYS_PROBE1(fail1, efx_rc_t, rc);
788 #endif /* EFSYS_OPT_RX_SCATTER */
791 #define EFX_RX_LFSR_HASH(_enp, _insert) \
795 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
796 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
797 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
798 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
799 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
800 (_insert) ? 1 : 0); \
801 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
803 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
804 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
806 EFX_SET_OWORD_FIELD(oword, \
807 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
808 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
812 _NOTE(CONSTANTCONDITION) \
815 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
819 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
820 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
821 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
823 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
825 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
826 (_insert) ? 1 : 0); \
827 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
829 _NOTE(CONSTANTCONDITION) \
832 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
836 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
837 EFX_SET_OWORD_FIELD(oword, \
838 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
839 EFX_SET_OWORD_FIELD(oword, \
840 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
841 EFX_SET_OWORD_FIELD(oword, \
842 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
843 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
847 _NOTE(CONSTANTCONDITION) \
851 #if EFSYS_OPT_RX_SCALE
853 static __checkReturn efx_rc_t
854 siena_rx_scale_mode_set(
856 __in uint32_t rss_context,
857 __in efx_rx_hash_alg_t alg,
858 __in efx_rx_hash_type_t type,
859 __in boolean_t insert)
863 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
869 case EFX_RX_HASHALG_LFSR:
870 EFX_RX_LFSR_HASH(enp, insert);
873 case EFX_RX_HASHALG_TOEPLITZ:
874 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
875 type & EFX_RX_HASH_IPV4,
876 type & EFX_RX_HASH_TCPIPV4);
878 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
879 type & EFX_RX_HASH_IPV6,
880 type & EFX_RX_HASH_TCPIPV6,
899 EFSYS_PROBE1(fail1, efx_rc_t, rc);
901 EFX_RX_LFSR_HASH(enp, B_FALSE);
907 #if EFSYS_OPT_RX_SCALE
908 static __checkReturn efx_rc_t
909 siena_rx_scale_key_set(
911 __in uint32_t rss_context,
912 __in_ecount(n) uint8_t *key,
920 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
927 /* Write Toeplitz IPv4 hash key */
928 EFX_ZERO_OWORD(oword);
929 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
930 offset > 0 && byte < n;
932 oword.eo_u8[offset - 1] = key[byte++];
934 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
938 /* Verify Toeplitz IPv4 hash key */
939 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
940 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
941 offset > 0 && byte < n;
943 if (oword.eo_u8[offset - 1] != key[byte++]) {
949 if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
954 /* Write Toeplitz IPv6 hash key 3 */
955 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
956 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
957 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
958 offset > 0 && byte < n;
960 oword.eo_u8[offset - 1] = key[byte++];
962 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
964 /* Write Toeplitz IPv6 hash key 2 */
965 EFX_ZERO_OWORD(oword);
966 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
967 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
968 offset > 0 && byte < n;
970 oword.eo_u8[offset - 1] = key[byte++];
972 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
974 /* Write Toeplitz IPv6 hash key 1 */
975 EFX_ZERO_OWORD(oword);
976 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
977 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
978 offset > 0 && byte < n;
980 oword.eo_u8[offset - 1] = key[byte++];
982 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
986 /* Verify Toeplitz IPv6 hash key 3 */
987 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
988 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
989 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
990 offset > 0 && byte < n;
992 if (oword.eo_u8[offset - 1] != key[byte++]) {
998 /* Verify Toeplitz IPv6 hash key 2 */
999 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1000 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1001 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1002 offset > 0 && byte < n;
1004 if (oword.eo_u8[offset - 1] != key[byte++]) {
1010 /* Verify Toeplitz IPv6 hash key 1 */
1011 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1012 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1013 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1014 offset > 0 && byte < n;
1016 if (oword.eo_u8[offset - 1] != key[byte++]) {
1034 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1040 #if EFSYS_OPT_RX_SCALE
1041 static __checkReturn efx_rc_t
1042 siena_rx_scale_tbl_set(
1043 __in efx_nic_t *enp,
1044 __in uint32_t rss_context,
1045 __in_ecount(n) unsigned int *table,
1052 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
1053 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
1055 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1060 if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
1065 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
1068 /* Calculate the entry to place in the table */
1069 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1071 EFSYS_PROBE2(table, int, index, uint32_t, byte);
1073 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
1075 /* Write the table */
1076 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1077 index, &oword, B_TRUE);
1080 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
1083 /* Determine if we're starting a new batch */
1084 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1086 /* Read the table */
1087 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
1088 index, &oword, B_TRUE);
1090 /* Verify the entry */
1091 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1104 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1111 * Falcon/Siena pseudo-header
1112 * --------------------------
1114 * Receive packets are prefixed by an optional 16 byte pseudo-header.
1115 * The pseudo-header is a byte array of one of the forms:
1117 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1118 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1119 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1122 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
1123 * LL.LL LFSR hash (16-bit big-endian)
1126 #if EFSYS_OPT_RX_SCALE
1127 static __checkReturn uint32_t
1128 siena_rx_prefix_hash(
1129 __in efx_nic_t *enp,
1130 __in efx_rx_hash_alg_t func,
1131 __in uint8_t *buffer)
1133 _NOTE(ARGUNUSED(enp))
1136 case EFX_RX_HASHALG_TOEPLITZ:
1137 return ((buffer[12] << 24) |
1138 (buffer[13] << 16) |
1142 case EFX_RX_HASHALG_LFSR:
1143 return ((buffer[14] << 8) | buffer[15]);
1150 #endif /* EFSYS_OPT_RX_SCALE */
1152 static __checkReturn efx_rc_t
1153 siena_rx_prefix_pktlen(
1154 __in efx_nic_t *enp,
1155 __in uint8_t *buffer,
1156 __out uint16_t *lengthp)
1158 _NOTE(ARGUNUSED(enp, buffer, lengthp))
1160 /* Not supported by Falcon/Siena hardware */
1168 __in efx_rxq_t *erp,
1169 __in_ecount(n) efsys_dma_addr_t *addrp,
1171 __in unsigned int n,
1172 __in unsigned int completed,
1173 __in unsigned int added)
1177 unsigned int offset;
1180 /* The client driver must not overfill the queue */
1181 EFSYS_ASSERT3U(added - completed + n, <=,
1182 EFX_RXQ_LIMIT(erp->er_mask + 1));
1184 id = added & (erp->er_mask);
1185 for (i = 0; i < n; i++) {
1186 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1187 unsigned int, id, efsys_dma_addr_t, addrp[i],
1190 EFX_POPULATE_QWORD_3(qword,
1191 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1192 FSF_AZ_RX_KER_BUF_ADDR_DW0,
1193 (uint32_t)(addrp[i] & 0xffffffff),
1194 FSF_AZ_RX_KER_BUF_ADDR_DW1,
1195 (uint32_t)(addrp[i] >> 32));
1197 offset = id * sizeof (efx_qword_t);
1198 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1200 id = (id + 1) & (erp->er_mask);
1206 __in efx_rxq_t *erp,
1207 __in unsigned int added,
1208 __inout unsigned int *pushedp)
1210 efx_nic_t *enp = erp->er_enp;
1211 unsigned int pushed = *pushedp;
1216 /* All descriptors are pushed */
1219 /* Push the populated descriptors out */
1220 wptr = added & erp->er_mask;
1222 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1224 /* Only write the third DWORD */
1225 EFX_POPULATE_DWORD_1(dword,
1226 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1228 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1229 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1230 wptr, pushed & erp->er_mask);
1231 EFSYS_PIO_WRITE_BARRIER();
1232 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1233 erp->er_index, &dword, B_FALSE);
1236 #if EFSYS_OPT_RX_PACKED_STREAM
1238 siena_rx_qps_update_credits(
1239 __in efx_rxq_t *erp)
1241 /* Not supported by Siena hardware */
1246 siena_rx_qps_packet_info(
1247 __in efx_rxq_t *erp,
1248 __in uint8_t *buffer,
1249 __in uint32_t buffer_length,
1250 __in uint32_t current_offset,
1251 __out uint16_t *lengthp,
1252 __out uint32_t *next_offsetp,
1253 __out uint32_t *timestamp)
1255 /* Not supported by Siena hardware */
1260 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1262 static __checkReturn efx_rc_t
1264 __in efx_rxq_t *erp)
1266 efx_nic_t *enp = erp->er_enp;
1270 label = erp->er_index;
1272 /* Flush the queue */
1273 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1274 FRF_AZ_RX_FLUSH_DESCQ, label);
1275 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1282 __in efx_rxq_t *erp)
1284 efx_nic_t *enp = erp->er_enp;
1287 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1289 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1290 erp->er_index, &oword, B_TRUE);
1292 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1293 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1294 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1296 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1297 erp->er_index, &oword, B_TRUE);
1300 static __checkReturn efx_rc_t
1302 __in efx_nic_t *enp,
1303 __in unsigned int index,
1304 __in unsigned int label,
1305 __in efx_rxq_type_t type,
1306 __in efsys_mem_t *esmp,
1309 __in efx_evq_t *eep,
1310 __in efx_rxq_t *erp)
1312 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1318 _NOTE(ARGUNUSED(esmp))
1320 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1321 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1322 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1323 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1325 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1326 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1328 if (!ISP2(n) || (n < EFX_RXQ_MINNDESCS) || (n > EFX_RXQ_MAXNDESCS)) {
1332 if (index >= encp->enc_rxq_limit) {
1336 for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1338 if ((1 << size) == (int)(n / EFX_RXQ_MINNDESCS))
1340 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1346 case EFX_RXQ_TYPE_DEFAULT:
1350 #if EFSYS_OPT_RX_SCATTER
1351 case EFX_RXQ_TYPE_SCATTER:
1352 if (enp->en_family < EFX_FAMILY_SIENA) {
1358 #endif /* EFSYS_OPT_RX_SCATTER */
1365 /* Set up the new descriptor queue */
1366 EFX_POPULATE_OWORD_7(oword,
1367 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1368 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1369 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1370 FRF_AZ_RX_DESCQ_LABEL, label,
1371 FRF_AZ_RX_DESCQ_SIZE, size,
1372 FRF_AZ_RX_DESCQ_TYPE, 0,
1373 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1375 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1376 erp->er_index, &oword, B_TRUE);
1387 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1394 __in efx_rxq_t *erp)
1396 efx_nic_t *enp = erp->er_enp;
1399 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1400 --enp->en_rx_qcount;
1402 /* Purge descriptor queue */
1403 EFX_ZERO_OWORD(oword);
1405 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1406 erp->er_index, &oword, B_TRUE);
1408 /* Free the RXQ object */
1409 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1414 __in efx_nic_t *enp)
1416 _NOTE(ARGUNUSED(enp))
1419 #endif /* EFSYS_OPT_SIENA */