2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
37 static __checkReturn efx_rc_t
45 #if EFSYS_OPT_RX_SCATTER
46 static __checkReturn efx_rc_t
47 siena_rx_scatter_enable(
49 __in unsigned int buf_size);
50 #endif /* EFSYS_OPT_RX_SCATTER */
52 #if EFSYS_OPT_RX_SCALE
53 static __checkReturn efx_rc_t
54 siena_rx_scale_mode_set(
56 __in uint32_t rss_context,
57 __in efx_rx_hash_alg_t alg,
58 __in efx_rx_hash_type_t type,
59 __in boolean_t insert);
61 static __checkReturn efx_rc_t
62 siena_rx_scale_key_set(
64 __in uint32_t rss_context,
65 __in_ecount(n) uint8_t *key,
68 static __checkReturn efx_rc_t
69 siena_rx_scale_tbl_set(
71 __in uint32_t rss_context,
72 __in_ecount(n) unsigned int *table,
75 static __checkReturn uint32_t
78 __in efx_rx_hash_alg_t func,
79 __in uint8_t *buffer);
81 #endif /* EFSYS_OPT_RX_SCALE */
83 static __checkReturn efx_rc_t
84 siena_rx_prefix_pktlen(
87 __out uint16_t *lengthp);
92 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
94 __in unsigned int ndescs,
95 __in unsigned int completed,
96 __in unsigned int added);
101 __in unsigned int added,
102 __inout unsigned int *pushedp);
104 #if EFSYS_OPT_RX_PACKED_STREAM
106 siena_rx_qpush_ps_credits(
107 __in efx_rxq_t *erp);
109 static __checkReturn uint8_t *
110 siena_rx_qps_packet_info(
112 __in uint8_t *buffer,
113 __in uint32_t buffer_length,
114 __in uint32_t current_offset,
115 __out uint16_t *lengthp,
116 __out uint32_t *next_offsetp,
117 __out uint32_t *timestamp);
120 static __checkReturn efx_rc_t
122 __in efx_rxq_t *erp);
126 __in efx_rxq_t *erp);
128 static __checkReturn efx_rc_t
131 __in unsigned int index,
132 __in unsigned int label,
133 __in efx_rxq_type_t type,
134 __in efsys_mem_t *esmp,
137 __in unsigned int flags,
139 __in efx_rxq_t *erp);
143 __in efx_rxq_t *erp);
145 #endif /* EFSYS_OPT_SIENA */
149 static const efx_rx_ops_t __efx_rx_siena_ops = {
150 siena_rx_init, /* erxo_init */
151 siena_rx_fini, /* erxo_fini */
152 #if EFSYS_OPT_RX_SCATTER
153 siena_rx_scatter_enable, /* erxo_scatter_enable */
155 #if EFSYS_OPT_RX_SCALE
156 NULL, /* erxo_scale_context_alloc */
157 NULL, /* erxo_scale_context_free */
158 siena_rx_scale_mode_set, /* erxo_scale_mode_set */
159 siena_rx_scale_key_set, /* erxo_scale_key_set */
160 siena_rx_scale_tbl_set, /* erxo_scale_tbl_set */
161 siena_rx_prefix_hash, /* erxo_prefix_hash */
163 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
164 siena_rx_qpost, /* erxo_qpost */
165 siena_rx_qpush, /* erxo_qpush */
166 #if EFSYS_OPT_RX_PACKED_STREAM
167 siena_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
168 siena_rx_qps_packet_info, /* erxo_qps_packet_info */
170 siena_rx_qflush, /* erxo_qflush */
171 siena_rx_qenable, /* erxo_qenable */
172 siena_rx_qcreate, /* erxo_qcreate */
173 siena_rx_qdestroy, /* erxo_qdestroy */
175 #endif /* EFSYS_OPT_SIENA */
177 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
178 static const efx_rx_ops_t __efx_rx_ef10_ops = {
179 ef10_rx_init, /* erxo_init */
180 ef10_rx_fini, /* erxo_fini */
181 #if EFSYS_OPT_RX_SCATTER
182 ef10_rx_scatter_enable, /* erxo_scatter_enable */
184 #if EFSYS_OPT_RX_SCALE
185 ef10_rx_scale_context_alloc, /* erxo_scale_context_alloc */
186 ef10_rx_scale_context_free, /* erxo_scale_context_free */
187 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */
188 ef10_rx_scale_key_set, /* erxo_scale_key_set */
189 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */
190 ef10_rx_prefix_hash, /* erxo_prefix_hash */
192 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
193 ef10_rx_qpost, /* erxo_qpost */
194 ef10_rx_qpush, /* erxo_qpush */
195 #if EFSYS_OPT_RX_PACKED_STREAM
196 ef10_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
197 ef10_rx_qps_packet_info, /* erxo_qps_packet_info */
199 ef10_rx_qflush, /* erxo_qflush */
200 ef10_rx_qenable, /* erxo_qenable */
201 ef10_rx_qcreate, /* erxo_qcreate */
202 ef10_rx_qdestroy, /* erxo_qdestroy */
204 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
207 __checkReturn efx_rc_t
209 __inout efx_nic_t *enp)
211 const efx_rx_ops_t *erxop;
214 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
215 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
217 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
222 if (enp->en_mod_flags & EFX_MOD_RX) {
227 switch (enp->en_family) {
229 case EFX_FAMILY_SIENA:
230 erxop = &__efx_rx_siena_ops;
232 #endif /* EFSYS_OPT_SIENA */
234 #if EFSYS_OPT_HUNTINGTON
235 case EFX_FAMILY_HUNTINGTON:
236 erxop = &__efx_rx_ef10_ops;
238 #endif /* EFSYS_OPT_HUNTINGTON */
240 #if EFSYS_OPT_MEDFORD
241 case EFX_FAMILY_MEDFORD:
242 erxop = &__efx_rx_ef10_ops;
244 #endif /* EFSYS_OPT_MEDFORD */
252 if ((rc = erxop->erxo_init(enp)) != 0)
255 enp->en_erxop = erxop;
256 enp->en_mod_flags |= EFX_MOD_RX;
266 EFSYS_PROBE1(fail1, efx_rc_t, rc);
268 enp->en_erxop = NULL;
269 enp->en_mod_flags &= ~EFX_MOD_RX;
277 const efx_rx_ops_t *erxop = enp->en_erxop;
279 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
280 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
281 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
282 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
284 erxop->erxo_fini(enp);
286 enp->en_erxop = NULL;
287 enp->en_mod_flags &= ~EFX_MOD_RX;
290 #if EFSYS_OPT_RX_SCATTER
291 __checkReturn efx_rc_t
292 efx_rx_scatter_enable(
294 __in unsigned int buf_size)
296 const efx_rx_ops_t *erxop = enp->en_erxop;
299 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
300 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
302 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
308 EFSYS_PROBE1(fail1, efx_rc_t, rc);
311 #endif /* EFSYS_OPT_RX_SCATTER */
313 #if EFSYS_OPT_RX_SCALE
314 __checkReturn efx_rc_t
315 efx_rx_hash_default_support_get(
317 __out efx_rx_hash_support_t *supportp)
321 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
322 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
324 if (supportp == NULL) {
330 * Report the hashing support the client gets by default if it
331 * does not allocate an RSS context itself.
333 *supportp = enp->en_hash_support;
338 EFSYS_PROBE1(fail1, efx_rc_t, rc);
343 __checkReturn efx_rc_t
344 efx_rx_scale_default_support_get(
346 __out efx_rx_scale_context_type_t *typep)
350 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
351 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
359 * Report the RSS support the client gets by default if it
360 * does not allocate an RSS context itself.
362 *typep = enp->en_rss_context_type;
367 EFSYS_PROBE1(fail1, efx_rc_t, rc);
371 #endif /* EFSYS_OPT_RX_SCALE */
373 #if EFSYS_OPT_RX_SCALE
374 __checkReturn efx_rc_t
375 efx_rx_scale_context_alloc(
377 __in efx_rx_scale_context_type_t type,
378 __in uint32_t num_queues,
379 __out uint32_t *rss_contextp)
381 const efx_rx_ops_t *erxop = enp->en_erxop;
384 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
385 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
387 if (erxop->erxo_scale_context_alloc == NULL) {
391 if ((rc = erxop->erxo_scale_context_alloc(enp, type,
392 num_queues, rss_contextp)) != 0) {
401 EFSYS_PROBE1(fail1, efx_rc_t, rc);
404 #endif /* EFSYS_OPT_RX_SCALE */
406 #if EFSYS_OPT_RX_SCALE
407 __checkReturn efx_rc_t
408 efx_rx_scale_context_free(
410 __in uint32_t rss_context)
412 const efx_rx_ops_t *erxop = enp->en_erxop;
415 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
416 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
418 if (erxop->erxo_scale_context_free == NULL) {
422 if ((rc = erxop->erxo_scale_context_free(enp, rss_context)) != 0)
430 EFSYS_PROBE1(fail1, efx_rc_t, rc);
433 #endif /* EFSYS_OPT_RX_SCALE */
435 #if EFSYS_OPT_RX_SCALE
436 __checkReturn efx_rc_t
437 efx_rx_scale_mode_set(
439 __in uint32_t rss_context,
440 __in efx_rx_hash_alg_t alg,
441 __in efx_rx_hash_type_t type,
442 __in boolean_t insert)
444 const efx_rx_ops_t *erxop = enp->en_erxop;
447 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
448 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
450 if (erxop->erxo_scale_mode_set != NULL) {
451 if ((rc = erxop->erxo_scale_mode_set(enp, rss_context, alg,
459 EFSYS_PROBE1(fail1, efx_rc_t, rc);
462 #endif /* EFSYS_OPT_RX_SCALE */
464 #if EFSYS_OPT_RX_SCALE
465 __checkReturn efx_rc_t
466 efx_rx_scale_key_set(
468 __in uint32_t rss_context,
469 __in_ecount(n) uint8_t *key,
472 const efx_rx_ops_t *erxop = enp->en_erxop;
475 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
476 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
478 if ((rc = erxop->erxo_scale_key_set(enp, rss_context, key, n)) != 0)
484 EFSYS_PROBE1(fail1, efx_rc_t, rc);
488 #endif /* EFSYS_OPT_RX_SCALE */
490 #if EFSYS_OPT_RX_SCALE
491 __checkReturn efx_rc_t
492 efx_rx_scale_tbl_set(
494 __in uint32_t rss_context,
495 __in_ecount(n) unsigned int *table,
498 const efx_rx_ops_t *erxop = enp->en_erxop;
501 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
502 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
504 if ((rc = erxop->erxo_scale_tbl_set(enp, rss_context, table, n)) != 0)
510 EFSYS_PROBE1(fail1, efx_rc_t, rc);
514 #endif /* EFSYS_OPT_RX_SCALE */
519 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
521 __in unsigned int ndescs,
522 __in unsigned int completed,
523 __in unsigned int added)
525 efx_nic_t *enp = erp->er_enp;
526 const efx_rx_ops_t *erxop = enp->en_erxop;
528 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
530 erxop->erxo_qpost(erp, addrp, size, ndescs, completed, added);
533 #if EFSYS_OPT_RX_PACKED_STREAM
536 efx_rx_qpush_ps_credits(
539 efx_nic_t *enp = erp->er_enp;
540 const efx_rx_ops_t *erxop = enp->en_erxop;
542 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
544 erxop->erxo_qpush_ps_credits(erp);
547 __checkReturn uint8_t *
548 efx_rx_qps_packet_info(
550 __in uint8_t *buffer,
551 __in uint32_t buffer_length,
552 __in uint32_t current_offset,
553 __out uint16_t *lengthp,
554 __out uint32_t *next_offsetp,
555 __out uint32_t *timestamp)
557 efx_nic_t *enp = erp->er_enp;
558 const efx_rx_ops_t *erxop = enp->en_erxop;
560 return (erxop->erxo_qps_packet_info(erp, buffer,
561 buffer_length, current_offset, lengthp,
562 next_offsetp, timestamp));
565 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
570 __in unsigned int added,
571 __inout unsigned int *pushedp)
573 efx_nic_t *enp = erp->er_enp;
574 const efx_rx_ops_t *erxop = enp->en_erxop;
576 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
578 erxop->erxo_qpush(erp, added, pushedp);
581 __checkReturn efx_rc_t
585 efx_nic_t *enp = erp->er_enp;
586 const efx_rx_ops_t *erxop = enp->en_erxop;
589 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
591 if ((rc = erxop->erxo_qflush(erp)) != 0)
597 EFSYS_PROBE1(fail1, efx_rc_t, rc);
606 efx_nic_t *enp = erp->er_enp;
607 const efx_rx_ops_t *erxop = enp->en_erxop;
609 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
611 erxop->erxo_qenable(erp);
614 __checkReturn efx_rc_t
617 __in unsigned int index,
618 __in unsigned int label,
619 __in efx_rxq_type_t type,
620 __in efsys_mem_t *esmp,
623 __in unsigned int flags,
625 __deref_out efx_rxq_t **erpp)
627 const efx_rx_ops_t *erxop = enp->en_erxop;
631 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
632 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
634 /* Allocate an RXQ object */
635 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
642 erp->er_magic = EFX_RXQ_MAGIC;
644 erp->er_index = index;
645 erp->er_mask = ndescs - 1;
648 if ((rc = erxop->erxo_qcreate(enp, index, label, type, esmp, ndescs, id,
649 flags, eep, erp)) != 0)
660 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
662 EFSYS_PROBE1(fail1, efx_rc_t, rc);
671 efx_nic_t *enp = erp->er_enp;
672 const efx_rx_ops_t *erxop = enp->en_erxop;
674 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
676 erxop->erxo_qdestroy(erp);
679 __checkReturn efx_rc_t
680 efx_pseudo_hdr_pkt_length_get(
682 __in uint8_t *buffer,
683 __out uint16_t *lengthp)
685 efx_nic_t *enp = erp->er_enp;
686 const efx_rx_ops_t *erxop = enp->en_erxop;
688 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
690 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
693 #if EFSYS_OPT_RX_SCALE
694 __checkReturn uint32_t
695 efx_pseudo_hdr_hash_get(
697 __in efx_rx_hash_alg_t func,
698 __in uint8_t *buffer)
700 efx_nic_t *enp = erp->er_enp;
701 const efx_rx_ops_t *erxop = enp->en_erxop;
703 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
705 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
706 return (erxop->erxo_prefix_hash(enp, func, buffer));
708 #endif /* EFSYS_OPT_RX_SCALE */
712 static __checkReturn efx_rc_t
719 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
721 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
722 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
723 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
724 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
725 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
726 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
727 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
729 /* Zero the RSS table */
730 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
732 EFX_ZERO_OWORD(oword);
733 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
734 index, &oword, B_TRUE);
737 #if EFSYS_OPT_RX_SCALE
738 /* The RSS key and indirection table are writable. */
739 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
741 /* Hardware can insert RX hash with/without RSS */
742 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
743 #endif /* EFSYS_OPT_RX_SCALE */
748 #if EFSYS_OPT_RX_SCATTER
749 static __checkReturn efx_rc_t
750 siena_rx_scatter_enable(
752 __in unsigned int buf_size)
758 nbuf32 = buf_size / 32;
760 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
761 ((buf_size % 32) != 0)) {
766 if (enp->en_rx_qcount > 0) {
771 /* Set scatter buffer size */
772 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
773 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
774 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
776 /* Enable scatter for packets not matching a filter */
777 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
778 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
779 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
786 EFSYS_PROBE1(fail1, efx_rc_t, rc);
790 #endif /* EFSYS_OPT_RX_SCATTER */
793 #define EFX_RX_LFSR_HASH(_enp, _insert) \
797 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
798 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
799 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
800 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
801 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
802 (_insert) ? 1 : 0); \
803 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
805 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
806 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
808 EFX_SET_OWORD_FIELD(oword, \
809 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
810 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
814 _NOTE(CONSTANTCONDITION) \
817 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
821 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
822 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
823 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
825 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
827 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
828 (_insert) ? 1 : 0); \
829 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
831 _NOTE(CONSTANTCONDITION) \
834 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
838 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
839 EFX_SET_OWORD_FIELD(oword, \
840 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
841 EFX_SET_OWORD_FIELD(oword, \
842 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
843 EFX_SET_OWORD_FIELD(oword, \
844 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
845 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
849 _NOTE(CONSTANTCONDITION) \
853 #if EFSYS_OPT_RX_SCALE
855 static __checkReturn efx_rc_t
856 siena_rx_scale_mode_set(
858 __in uint32_t rss_context,
859 __in efx_rx_hash_alg_t alg,
860 __in efx_rx_hash_type_t type,
861 __in boolean_t insert)
865 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
871 case EFX_RX_HASHALG_LFSR:
872 EFX_RX_LFSR_HASH(enp, insert);
875 case EFX_RX_HASHALG_TOEPLITZ:
876 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
877 type & EFX_RX_HASH_IPV4,
878 type & EFX_RX_HASH_TCPIPV4);
880 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
881 type & EFX_RX_HASH_IPV6,
882 type & EFX_RX_HASH_TCPIPV6,
901 EFSYS_PROBE1(fail1, efx_rc_t, rc);
903 EFX_RX_LFSR_HASH(enp, B_FALSE);
909 #if EFSYS_OPT_RX_SCALE
910 static __checkReturn efx_rc_t
911 siena_rx_scale_key_set(
913 __in uint32_t rss_context,
914 __in_ecount(n) uint8_t *key,
922 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
929 /* Write Toeplitz IPv4 hash key */
930 EFX_ZERO_OWORD(oword);
931 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
932 offset > 0 && byte < n;
934 oword.eo_u8[offset - 1] = key[byte++];
936 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
940 /* Verify Toeplitz IPv4 hash key */
941 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
942 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
943 offset > 0 && byte < n;
945 if (oword.eo_u8[offset - 1] != key[byte++]) {
951 if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
956 /* Write Toeplitz IPv6 hash key 3 */
957 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
958 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
959 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
960 offset > 0 && byte < n;
962 oword.eo_u8[offset - 1] = key[byte++];
964 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
966 /* Write Toeplitz IPv6 hash key 2 */
967 EFX_ZERO_OWORD(oword);
968 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
969 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
970 offset > 0 && byte < n;
972 oword.eo_u8[offset - 1] = key[byte++];
974 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
976 /* Write Toeplitz IPv6 hash key 1 */
977 EFX_ZERO_OWORD(oword);
978 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
979 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
980 offset > 0 && byte < n;
982 oword.eo_u8[offset - 1] = key[byte++];
984 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
988 /* Verify Toeplitz IPv6 hash key 3 */
989 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
990 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
991 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
992 offset > 0 && byte < n;
994 if (oword.eo_u8[offset - 1] != key[byte++]) {
1000 /* Verify Toeplitz IPv6 hash key 2 */
1001 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1002 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1003 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1004 offset > 0 && byte < n;
1006 if (oword.eo_u8[offset - 1] != key[byte++]) {
1012 /* Verify Toeplitz IPv6 hash key 1 */
1013 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1014 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1015 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1016 offset > 0 && byte < n;
1018 if (oword.eo_u8[offset - 1] != key[byte++]) {
1036 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1042 #if EFSYS_OPT_RX_SCALE
1043 static __checkReturn efx_rc_t
1044 siena_rx_scale_tbl_set(
1045 __in efx_nic_t *enp,
1046 __in uint32_t rss_context,
1047 __in_ecount(n) unsigned int *table,
1054 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
1055 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
1057 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1062 if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
1067 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
1070 /* Calculate the entry to place in the table */
1071 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1073 EFSYS_PROBE2(table, int, index, uint32_t, byte);
1075 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
1077 /* Write the table */
1078 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1079 index, &oword, B_TRUE);
1082 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
1085 /* Determine if we're starting a new batch */
1086 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1088 /* Read the table */
1089 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
1090 index, &oword, B_TRUE);
1092 /* Verify the entry */
1093 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1106 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1113 * Falcon/Siena pseudo-header
1114 * --------------------------
1116 * Receive packets are prefixed by an optional 16 byte pseudo-header.
1117 * The pseudo-header is a byte array of one of the forms:
1119 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1120 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1121 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1124 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
1125 * LL.LL LFSR hash (16-bit big-endian)
1128 #if EFSYS_OPT_RX_SCALE
1129 static __checkReturn uint32_t
1130 siena_rx_prefix_hash(
1131 __in efx_nic_t *enp,
1132 __in efx_rx_hash_alg_t func,
1133 __in uint8_t *buffer)
1135 _NOTE(ARGUNUSED(enp))
1138 case EFX_RX_HASHALG_TOEPLITZ:
1139 return ((buffer[12] << 24) |
1140 (buffer[13] << 16) |
1144 case EFX_RX_HASHALG_LFSR:
1145 return ((buffer[14] << 8) | buffer[15]);
1152 #endif /* EFSYS_OPT_RX_SCALE */
1154 static __checkReturn efx_rc_t
1155 siena_rx_prefix_pktlen(
1156 __in efx_nic_t *enp,
1157 __in uint8_t *buffer,
1158 __out uint16_t *lengthp)
1160 _NOTE(ARGUNUSED(enp, buffer, lengthp))
1162 /* Not supported by Falcon/Siena hardware */
1170 __in efx_rxq_t *erp,
1171 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1173 __in unsigned int ndescs,
1174 __in unsigned int completed,
1175 __in unsigned int added)
1179 unsigned int offset;
1182 /* The client driver must not overfill the queue */
1183 EFSYS_ASSERT3U(added - completed + ndescs, <=,
1184 EFX_RXQ_LIMIT(erp->er_mask + 1));
1186 id = added & (erp->er_mask);
1187 for (i = 0; i < ndescs; i++) {
1188 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1189 unsigned int, id, efsys_dma_addr_t, addrp[i],
1192 EFX_POPULATE_QWORD_3(qword,
1193 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1194 FSF_AZ_RX_KER_BUF_ADDR_DW0,
1195 (uint32_t)(addrp[i] & 0xffffffff),
1196 FSF_AZ_RX_KER_BUF_ADDR_DW1,
1197 (uint32_t)(addrp[i] >> 32));
1199 offset = id * sizeof (efx_qword_t);
1200 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1202 id = (id + 1) & (erp->er_mask);
1208 __in efx_rxq_t *erp,
1209 __in unsigned int added,
1210 __inout unsigned int *pushedp)
1212 efx_nic_t *enp = erp->er_enp;
1213 unsigned int pushed = *pushedp;
1218 /* All descriptors are pushed */
1221 /* Push the populated descriptors out */
1222 wptr = added & erp->er_mask;
1224 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1226 /* Only write the third DWORD */
1227 EFX_POPULATE_DWORD_1(dword,
1228 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1230 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1231 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1232 wptr, pushed & erp->er_mask);
1233 EFSYS_PIO_WRITE_BARRIER();
1234 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1235 erp->er_index, &dword, B_FALSE);
1238 #if EFSYS_OPT_RX_PACKED_STREAM
1240 siena_rx_qpush_ps_credits(
1241 __in efx_rxq_t *erp)
1243 /* Not supported by Siena hardware */
1248 siena_rx_qps_packet_info(
1249 __in efx_rxq_t *erp,
1250 __in uint8_t *buffer,
1251 __in uint32_t buffer_length,
1252 __in uint32_t current_offset,
1253 __out uint16_t *lengthp,
1254 __out uint32_t *next_offsetp,
1255 __out uint32_t *timestamp)
1257 /* Not supported by Siena hardware */
1262 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1264 static __checkReturn efx_rc_t
1266 __in efx_rxq_t *erp)
1268 efx_nic_t *enp = erp->er_enp;
1272 label = erp->er_index;
1274 /* Flush the queue */
1275 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1276 FRF_AZ_RX_FLUSH_DESCQ, label);
1277 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1284 __in efx_rxq_t *erp)
1286 efx_nic_t *enp = erp->er_enp;
1289 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1291 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1292 erp->er_index, &oword, B_TRUE);
1294 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1295 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1296 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1298 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1299 erp->er_index, &oword, B_TRUE);
1302 static __checkReturn efx_rc_t
1304 __in efx_nic_t *enp,
1305 __in unsigned int index,
1306 __in unsigned int label,
1307 __in efx_rxq_type_t type,
1308 __in efsys_mem_t *esmp,
1311 __in unsigned int flags,
1312 __in efx_evq_t *eep,
1313 __in efx_rxq_t *erp)
1315 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1318 boolean_t jumbo = B_FALSE;
1321 _NOTE(ARGUNUSED(esmp))
1323 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1324 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1325 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1326 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1328 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1329 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1331 if (!ISP2(ndescs) ||
1332 (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
1336 if (index >= encp->enc_rxq_limit) {
1340 for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1342 if ((1 << size) == (int)(ndescs / EFX_RXQ_MINNDESCS))
1344 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1350 case EFX_RXQ_TYPE_DEFAULT:
1358 if (flags & EFX_RXQ_FLAG_SCATTER) {
1359 #if EFSYS_OPT_RX_SCATTER
1364 #endif /* EFSYS_OPT_RX_SCATTER */
1367 /* Set up the new descriptor queue */
1368 EFX_POPULATE_OWORD_7(oword,
1369 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1370 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1371 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1372 FRF_AZ_RX_DESCQ_LABEL, label,
1373 FRF_AZ_RX_DESCQ_SIZE, size,
1374 FRF_AZ_RX_DESCQ_TYPE, 0,
1375 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1377 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1378 erp->er_index, &oword, B_TRUE);
1382 #if !EFSYS_OPT_RX_SCATTER
1393 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1400 __in efx_rxq_t *erp)
1402 efx_nic_t *enp = erp->er_enp;
1405 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1406 --enp->en_rx_qcount;
1408 /* Purge descriptor queue */
1409 EFX_ZERO_OWORD(oword);
1411 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1412 erp->er_index, &oword, B_TRUE);
1414 /* Free the RXQ object */
1415 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1420 __in efx_nic_t *enp)
1422 _NOTE(ARGUNUSED(enp))
1425 #endif /* EFSYS_OPT_SIENA */