1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
13 static __checkReturn efx_rc_t
21 #if EFSYS_OPT_RX_SCATTER
22 static __checkReturn efx_rc_t
23 siena_rx_scatter_enable(
25 __in unsigned int buf_size);
26 #endif /* EFSYS_OPT_RX_SCATTER */
28 #if EFSYS_OPT_RX_SCALE
29 static __checkReturn efx_rc_t
30 siena_rx_scale_mode_set(
32 __in uint32_t rss_context,
33 __in efx_rx_hash_alg_t alg,
34 __in efx_rx_hash_type_t type,
35 __in boolean_t insert);
37 static __checkReturn efx_rc_t
38 siena_rx_scale_key_set(
40 __in uint32_t rss_context,
41 __in_ecount(n) uint8_t *key,
44 static __checkReturn efx_rc_t
45 siena_rx_scale_tbl_set(
47 __in uint32_t rss_context,
48 __in_ecount(n) unsigned int *table,
51 static __checkReturn uint32_t
54 __in efx_rx_hash_alg_t func,
55 __in uint8_t *buffer);
57 #endif /* EFSYS_OPT_RX_SCALE */
59 static __checkReturn efx_rc_t
60 siena_rx_prefix_pktlen(
63 __out uint16_t *lengthp);
68 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
70 __in unsigned int ndescs,
71 __in unsigned int completed,
72 __in unsigned int added);
77 __in unsigned int added,
78 __inout unsigned int *pushedp);
80 #if EFSYS_OPT_RX_PACKED_STREAM
82 siena_rx_qpush_ps_credits(
85 static __checkReturn uint8_t *
86 siena_rx_qps_packet_info(
89 __in uint32_t buffer_length,
90 __in uint32_t current_offset,
91 __out uint16_t *lengthp,
92 __out uint32_t *next_offsetp,
93 __out uint32_t *timestamp);
96 static __checkReturn efx_rc_t
102 __in efx_rxq_t *erp);
104 static __checkReturn efx_rc_t
107 __in unsigned int index,
108 __in unsigned int label,
109 __in efx_rxq_type_t type,
110 __in uint32_t type_data,
111 __in efsys_mem_t *esmp,
114 __in unsigned int flags,
116 __in efx_rxq_t *erp);
120 __in efx_rxq_t *erp);
122 #endif /* EFSYS_OPT_SIENA */
126 static const efx_rx_ops_t __efx_rx_siena_ops = {
127 siena_rx_init, /* erxo_init */
128 siena_rx_fini, /* erxo_fini */
129 #if EFSYS_OPT_RX_SCATTER
130 siena_rx_scatter_enable, /* erxo_scatter_enable */
132 #if EFSYS_OPT_RX_SCALE
133 NULL, /* erxo_scale_context_alloc */
134 NULL, /* erxo_scale_context_free */
135 siena_rx_scale_mode_set, /* erxo_scale_mode_set */
136 siena_rx_scale_key_set, /* erxo_scale_key_set */
137 siena_rx_scale_tbl_set, /* erxo_scale_tbl_set */
138 siena_rx_prefix_hash, /* erxo_prefix_hash */
140 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
141 siena_rx_qpost, /* erxo_qpost */
142 siena_rx_qpush, /* erxo_qpush */
143 #if EFSYS_OPT_RX_PACKED_STREAM
144 siena_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
145 siena_rx_qps_packet_info, /* erxo_qps_packet_info */
147 siena_rx_qflush, /* erxo_qflush */
148 siena_rx_qenable, /* erxo_qenable */
149 siena_rx_qcreate, /* erxo_qcreate */
150 siena_rx_qdestroy, /* erxo_qdestroy */
152 #endif /* EFSYS_OPT_SIENA */
154 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
155 static const efx_rx_ops_t __efx_rx_ef10_ops = {
156 ef10_rx_init, /* erxo_init */
157 ef10_rx_fini, /* erxo_fini */
158 #if EFSYS_OPT_RX_SCATTER
159 ef10_rx_scatter_enable, /* erxo_scatter_enable */
161 #if EFSYS_OPT_RX_SCALE
162 ef10_rx_scale_context_alloc, /* erxo_scale_context_alloc */
163 ef10_rx_scale_context_free, /* erxo_scale_context_free */
164 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */
165 ef10_rx_scale_key_set, /* erxo_scale_key_set */
166 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */
167 ef10_rx_prefix_hash, /* erxo_prefix_hash */
169 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
170 ef10_rx_qpost, /* erxo_qpost */
171 ef10_rx_qpush, /* erxo_qpush */
172 #if EFSYS_OPT_RX_PACKED_STREAM
173 ef10_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
174 ef10_rx_qps_packet_info, /* erxo_qps_packet_info */
176 ef10_rx_qflush, /* erxo_qflush */
177 ef10_rx_qenable, /* erxo_qenable */
178 ef10_rx_qcreate, /* erxo_qcreate */
179 ef10_rx_qdestroy, /* erxo_qdestroy */
181 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
184 __checkReturn efx_rc_t
186 __inout efx_nic_t *enp)
188 const efx_rx_ops_t *erxop;
191 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
192 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
194 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
199 if (enp->en_mod_flags & EFX_MOD_RX) {
204 switch (enp->en_family) {
206 case EFX_FAMILY_SIENA:
207 erxop = &__efx_rx_siena_ops;
209 #endif /* EFSYS_OPT_SIENA */
211 #if EFSYS_OPT_HUNTINGTON
212 case EFX_FAMILY_HUNTINGTON:
213 erxop = &__efx_rx_ef10_ops;
215 #endif /* EFSYS_OPT_HUNTINGTON */
217 #if EFSYS_OPT_MEDFORD
218 case EFX_FAMILY_MEDFORD:
219 erxop = &__efx_rx_ef10_ops;
221 #endif /* EFSYS_OPT_MEDFORD */
223 #if EFSYS_OPT_MEDFORD2
224 case EFX_FAMILY_MEDFORD2:
225 erxop = &__efx_rx_ef10_ops;
227 #endif /* EFSYS_OPT_MEDFORD2 */
235 if ((rc = erxop->erxo_init(enp)) != 0)
238 enp->en_erxop = erxop;
239 enp->en_mod_flags |= EFX_MOD_RX;
249 EFSYS_PROBE1(fail1, efx_rc_t, rc);
251 enp->en_erxop = NULL;
252 enp->en_mod_flags &= ~EFX_MOD_RX;
260 const efx_rx_ops_t *erxop = enp->en_erxop;
262 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
263 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
264 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
265 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
267 erxop->erxo_fini(enp);
269 enp->en_erxop = NULL;
270 enp->en_mod_flags &= ~EFX_MOD_RX;
273 #if EFSYS_OPT_RX_SCATTER
274 __checkReturn efx_rc_t
275 efx_rx_scatter_enable(
277 __in unsigned int buf_size)
279 const efx_rx_ops_t *erxop = enp->en_erxop;
282 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
283 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
285 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
291 EFSYS_PROBE1(fail1, efx_rc_t, rc);
294 #endif /* EFSYS_OPT_RX_SCATTER */
296 #if EFSYS_OPT_RX_SCALE
297 __checkReturn efx_rc_t
298 efx_rx_scale_hash_flags_get(
300 __in efx_rx_hash_alg_t hash_alg,
301 __inout_ecount(EFX_RX_HASH_NFLAGS) unsigned int *flags,
302 __out unsigned int *nflagsp)
304 unsigned int *entryp = flags;
307 if (flags == NULL || nflagsp == NULL) {
312 #define LIST_FLAGS(_entryp, _class, _l4_hashing) \
315 *(_entryp++) = EFX_RX_HASH(_class, 4TUPLE); \
317 *(_entryp++) = EFX_RX_HASH(_class, 2TUPLE); \
318 *(_entryp++) = EFX_RX_HASH(_class, DISABLE); \
320 _NOTE(CONSTANTCONDITION) \
324 case EFX_RX_HASHALG_TOEPLITZ:
325 LIST_FLAGS(entryp, IPV4_TCP, B_TRUE);
326 LIST_FLAGS(entryp, IPV6_TCP, B_TRUE);
327 LIST_FLAGS(entryp, IPV4, B_FALSE);
328 LIST_FLAGS(entryp, IPV6, B_FALSE);
338 *nflagsp = (unsigned int)(entryp - flags);
339 EFSYS_ASSERT3U(*nflagsp, <=, EFX_RX_HASH_NFLAGS);
347 EFSYS_PROBE1(fail1, efx_rc_t, rc);
352 __checkReturn efx_rc_t
353 efx_rx_hash_default_support_get(
355 __out efx_rx_hash_support_t *supportp)
359 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
360 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
362 if (supportp == NULL) {
368 * Report the hashing support the client gets by default if it
369 * does not allocate an RSS context itself.
371 *supportp = enp->en_hash_support;
376 EFSYS_PROBE1(fail1, efx_rc_t, rc);
381 __checkReturn efx_rc_t
382 efx_rx_scale_default_support_get(
384 __out efx_rx_scale_context_type_t *typep)
388 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
389 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
397 * Report the RSS support the client gets by default if it
398 * does not allocate an RSS context itself.
400 *typep = enp->en_rss_context_type;
405 EFSYS_PROBE1(fail1, efx_rc_t, rc);
409 #endif /* EFSYS_OPT_RX_SCALE */
411 #if EFSYS_OPT_RX_SCALE
412 __checkReturn efx_rc_t
413 efx_rx_scale_context_alloc(
415 __in efx_rx_scale_context_type_t type,
416 __in uint32_t num_queues,
417 __out uint32_t *rss_contextp)
419 const efx_rx_ops_t *erxop = enp->en_erxop;
422 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
423 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
425 if (erxop->erxo_scale_context_alloc == NULL) {
429 if ((rc = erxop->erxo_scale_context_alloc(enp, type,
430 num_queues, rss_contextp)) != 0) {
439 EFSYS_PROBE1(fail1, efx_rc_t, rc);
442 #endif /* EFSYS_OPT_RX_SCALE */
444 #if EFSYS_OPT_RX_SCALE
445 __checkReturn efx_rc_t
446 efx_rx_scale_context_free(
448 __in uint32_t rss_context)
450 const efx_rx_ops_t *erxop = enp->en_erxop;
453 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
454 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
456 if (erxop->erxo_scale_context_free == NULL) {
460 if ((rc = erxop->erxo_scale_context_free(enp, rss_context)) != 0)
468 EFSYS_PROBE1(fail1, efx_rc_t, rc);
471 #endif /* EFSYS_OPT_RX_SCALE */
473 #if EFSYS_OPT_RX_SCALE
474 __checkReturn efx_rc_t
475 efx_rx_scale_mode_set(
477 __in uint32_t rss_context,
478 __in efx_rx_hash_alg_t alg,
479 __in efx_rx_hash_type_t type,
480 __in boolean_t insert)
482 const efx_rx_ops_t *erxop = enp->en_erxop;
483 unsigned int type_flags[EFX_RX_HASH_NFLAGS];
484 unsigned int type_nflags;
485 efx_rx_hash_type_t type_check;
489 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
490 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
493 * Legacy flags and modern bits cannot be
494 * used at the same time in the hash type.
496 if ((type & EFX_RX_HASH_LEGACY_MASK) &&
497 (type & ~EFX_RX_HASH_LEGACY_MASK)) {
503 * Translate legacy flags to the new representation
504 * so that chip-specific handlers will consider the
507 if (type & EFX_RX_HASH_IPV4) {
508 type |= EFX_RX_HASH(IPV4, 2TUPLE);
509 type |= EFX_RX_HASH(IPV4_TCP, 2TUPLE);
512 if (type & EFX_RX_HASH_TCPIPV4)
513 type |= EFX_RX_HASH(IPV4_TCP, 4TUPLE);
515 if (type & EFX_RX_HASH_IPV6) {
516 type |= EFX_RX_HASH(IPV6, 2TUPLE);
517 type |= EFX_RX_HASH(IPV6_TCP, 2TUPLE);
520 if (type & EFX_RX_HASH_TCPIPV6)
521 type |= EFX_RX_HASH(IPV6_TCP, 4TUPLE);
523 type &= ~EFX_RX_HASH_LEGACY_MASK;
527 * Get the list of supported hash flags and sanitise the input.
529 rc = efx_rx_scale_hash_flags_get(enp, alg, type_flags, &type_nflags);
533 for (i = 0; i < type_nflags; ++i) {
534 if ((type_check & type_flags[i]) == type_flags[i])
535 type_check &= ~(type_flags[i]);
538 if (type_check != 0) {
543 if (erxop->erxo_scale_mode_set != NULL) {
544 if ((rc = erxop->erxo_scale_mode_set(enp, rss_context, alg,
558 EFSYS_PROBE1(fail1, efx_rc_t, rc);
561 #endif /* EFSYS_OPT_RX_SCALE */
563 #if EFSYS_OPT_RX_SCALE
564 __checkReturn efx_rc_t
565 efx_rx_scale_key_set(
567 __in uint32_t rss_context,
568 __in_ecount(n) uint8_t *key,
571 const efx_rx_ops_t *erxop = enp->en_erxop;
574 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
575 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
577 if ((rc = erxop->erxo_scale_key_set(enp, rss_context, key, n)) != 0)
583 EFSYS_PROBE1(fail1, efx_rc_t, rc);
587 #endif /* EFSYS_OPT_RX_SCALE */
589 #if EFSYS_OPT_RX_SCALE
590 __checkReturn efx_rc_t
591 efx_rx_scale_tbl_set(
593 __in uint32_t rss_context,
594 __in_ecount(n) unsigned int *table,
597 const efx_rx_ops_t *erxop = enp->en_erxop;
600 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
601 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
603 if ((rc = erxop->erxo_scale_tbl_set(enp, rss_context, table, n)) != 0)
609 EFSYS_PROBE1(fail1, efx_rc_t, rc);
613 #endif /* EFSYS_OPT_RX_SCALE */
618 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
620 __in unsigned int ndescs,
621 __in unsigned int completed,
622 __in unsigned int added)
624 efx_nic_t *enp = erp->er_enp;
625 const efx_rx_ops_t *erxop = enp->en_erxop;
627 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
629 erxop->erxo_qpost(erp, addrp, size, ndescs, completed, added);
632 #if EFSYS_OPT_RX_PACKED_STREAM
635 efx_rx_qpush_ps_credits(
638 efx_nic_t *enp = erp->er_enp;
639 const efx_rx_ops_t *erxop = enp->en_erxop;
641 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
643 erxop->erxo_qpush_ps_credits(erp);
646 __checkReturn uint8_t *
647 efx_rx_qps_packet_info(
649 __in uint8_t *buffer,
650 __in uint32_t buffer_length,
651 __in uint32_t current_offset,
652 __out uint16_t *lengthp,
653 __out uint32_t *next_offsetp,
654 __out uint32_t *timestamp)
656 efx_nic_t *enp = erp->er_enp;
657 const efx_rx_ops_t *erxop = enp->en_erxop;
659 return (erxop->erxo_qps_packet_info(erp, buffer,
660 buffer_length, current_offset, lengthp,
661 next_offsetp, timestamp));
664 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
669 __in unsigned int added,
670 __inout unsigned int *pushedp)
672 efx_nic_t *enp = erp->er_enp;
673 const efx_rx_ops_t *erxop = enp->en_erxop;
675 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
677 erxop->erxo_qpush(erp, added, pushedp);
680 __checkReturn efx_rc_t
684 efx_nic_t *enp = erp->er_enp;
685 const efx_rx_ops_t *erxop = enp->en_erxop;
688 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
690 if ((rc = erxop->erxo_qflush(erp)) != 0)
696 EFSYS_PROBE1(fail1, efx_rc_t, rc);
705 efx_nic_t *enp = erp->er_enp;
706 const efx_rx_ops_t *erxop = enp->en_erxop;
708 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
710 erxop->erxo_qenable(erp);
713 static __checkReturn efx_rc_t
714 efx_rx_qcreate_internal(
716 __in unsigned int index,
717 __in unsigned int label,
718 __in efx_rxq_type_t type,
719 __in uint32_t type_data,
720 __in efsys_mem_t *esmp,
723 __in unsigned int flags,
725 __deref_out efx_rxq_t **erpp)
727 const efx_rx_ops_t *erxop = enp->en_erxop;
731 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
732 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
734 /* Allocate an RXQ object */
735 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
742 erp->er_magic = EFX_RXQ_MAGIC;
744 erp->er_index = index;
745 erp->er_mask = ndescs - 1;
748 if ((rc = erxop->erxo_qcreate(enp, index, label, type, type_data, esmp,
749 ndescs, id, flags, eep, erp)) != 0)
760 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
762 EFSYS_PROBE1(fail1, efx_rc_t, rc);
767 __checkReturn efx_rc_t
770 __in unsigned int index,
771 __in unsigned int label,
772 __in efx_rxq_type_t type,
773 __in efsys_mem_t *esmp,
776 __in unsigned int flags,
778 __deref_out efx_rxq_t **erpp)
780 return efx_rx_qcreate_internal(enp, index, label, type, 0, esmp, ndescs,
781 id, flags, eep, erpp);
784 #if EFSYS_OPT_RX_PACKED_STREAM
786 __checkReturn efx_rc_t
787 efx_rx_qcreate_packed_stream(
789 __in unsigned int index,
790 __in unsigned int label,
791 __in uint32_t ps_buf_size,
792 __in efsys_mem_t *esmp,
795 __deref_out efx_rxq_t **erpp)
797 return efx_rx_qcreate_internal(enp, index, label,
798 EFX_RXQ_TYPE_PACKED_STREAM, ps_buf_size, esmp, ndescs,
799 0 /* id unused on EF10 */, EFX_RXQ_FLAG_NONE, eep, erpp);
808 efx_nic_t *enp = erp->er_enp;
809 const efx_rx_ops_t *erxop = enp->en_erxop;
811 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
813 erxop->erxo_qdestroy(erp);
816 __checkReturn efx_rc_t
817 efx_pseudo_hdr_pkt_length_get(
819 __in uint8_t *buffer,
820 __out uint16_t *lengthp)
822 efx_nic_t *enp = erp->er_enp;
823 const efx_rx_ops_t *erxop = enp->en_erxop;
825 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
827 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
830 #if EFSYS_OPT_RX_SCALE
831 __checkReturn uint32_t
832 efx_pseudo_hdr_hash_get(
834 __in efx_rx_hash_alg_t func,
835 __in uint8_t *buffer)
837 efx_nic_t *enp = erp->er_enp;
838 const efx_rx_ops_t *erxop = enp->en_erxop;
840 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
842 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
843 return (erxop->erxo_prefix_hash(enp, func, buffer));
845 #endif /* EFSYS_OPT_RX_SCALE */
849 static __checkReturn efx_rc_t
856 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
858 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
859 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
860 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
861 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
862 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
863 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
864 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
866 /* Zero the RSS table */
867 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
869 EFX_ZERO_OWORD(oword);
870 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
871 index, &oword, B_TRUE);
874 #if EFSYS_OPT_RX_SCALE
875 /* The RSS key and indirection table are writable. */
876 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
878 /* Hardware can insert RX hash with/without RSS */
879 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
880 #endif /* EFSYS_OPT_RX_SCALE */
885 #if EFSYS_OPT_RX_SCATTER
886 static __checkReturn efx_rc_t
887 siena_rx_scatter_enable(
889 __in unsigned int buf_size)
895 nbuf32 = buf_size / 32;
897 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
898 ((buf_size % 32) != 0)) {
903 if (enp->en_rx_qcount > 0) {
908 /* Set scatter buffer size */
909 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
910 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
911 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
913 /* Enable scatter for packets not matching a filter */
914 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
915 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
916 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
923 EFSYS_PROBE1(fail1, efx_rc_t, rc);
927 #endif /* EFSYS_OPT_RX_SCATTER */
930 #define EFX_RX_LFSR_HASH(_enp, _insert) \
934 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
935 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
936 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
937 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
938 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
939 (_insert) ? 1 : 0); \
940 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
942 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
943 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
945 EFX_SET_OWORD_FIELD(oword, \
946 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
947 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
951 _NOTE(CONSTANTCONDITION) \
954 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
958 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
959 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
960 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
962 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
964 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
965 (_insert) ? 1 : 0); \
966 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
968 _NOTE(CONSTANTCONDITION) \
971 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
975 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
976 EFX_SET_OWORD_FIELD(oword, \
977 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
978 EFX_SET_OWORD_FIELD(oword, \
979 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
980 EFX_SET_OWORD_FIELD(oword, \
981 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
982 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
986 _NOTE(CONSTANTCONDITION) \
990 #if EFSYS_OPT_RX_SCALE
992 static __checkReturn efx_rc_t
993 siena_rx_scale_mode_set(
995 __in uint32_t rss_context,
996 __in efx_rx_hash_alg_t alg,
997 __in efx_rx_hash_type_t type,
998 __in boolean_t insert)
1000 efx_rx_hash_type_t type_ipv4 = EFX_RX_HASH(IPV4, 2TUPLE);
1001 efx_rx_hash_type_t type_ipv4_tcp = EFX_RX_HASH(IPV4_TCP, 4TUPLE);
1002 efx_rx_hash_type_t type_ipv6 = EFX_RX_HASH(IPV6, 2TUPLE);
1003 efx_rx_hash_type_t type_ipv6_tcp = EFX_RX_HASH(IPV6_TCP, 4TUPLE);
1006 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1012 case EFX_RX_HASHALG_LFSR:
1013 EFX_RX_LFSR_HASH(enp, insert);
1016 case EFX_RX_HASHALG_TOEPLITZ:
1017 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
1018 (type & type_ipv4) == type_ipv4,
1019 (type & type_ipv4_tcp) == type_ipv4_tcp);
1021 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
1022 (type & type_ipv6) == type_ipv6,
1023 (type & type_ipv6_tcp) == type_ipv6_tcp,
1042 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1044 EFX_RX_LFSR_HASH(enp, B_FALSE);
1050 #if EFSYS_OPT_RX_SCALE
1051 static __checkReturn efx_rc_t
1052 siena_rx_scale_key_set(
1053 __in efx_nic_t *enp,
1054 __in uint32_t rss_context,
1055 __in_ecount(n) uint8_t *key,
1060 unsigned int offset;
1063 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1070 /* Write Toeplitz IPv4 hash key */
1071 EFX_ZERO_OWORD(oword);
1072 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1073 offset > 0 && byte < n;
1075 oword.eo_u8[offset - 1] = key[byte++];
1077 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1081 /* Verify Toeplitz IPv4 hash key */
1082 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1083 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1084 offset > 0 && byte < n;
1086 if (oword.eo_u8[offset - 1] != key[byte++]) {
1092 if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
1097 /* Write Toeplitz IPv6 hash key 3 */
1098 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1099 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1100 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1101 offset > 0 && byte < n;
1103 oword.eo_u8[offset - 1] = key[byte++];
1105 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1107 /* Write Toeplitz IPv6 hash key 2 */
1108 EFX_ZERO_OWORD(oword);
1109 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1110 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1111 offset > 0 && byte < n;
1113 oword.eo_u8[offset - 1] = key[byte++];
1115 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1117 /* Write Toeplitz IPv6 hash key 1 */
1118 EFX_ZERO_OWORD(oword);
1119 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1120 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1121 offset > 0 && byte < n;
1123 oword.eo_u8[offset - 1] = key[byte++];
1125 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1129 /* Verify Toeplitz IPv6 hash key 3 */
1130 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1131 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1132 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1133 offset > 0 && byte < n;
1135 if (oword.eo_u8[offset - 1] != key[byte++]) {
1141 /* Verify Toeplitz IPv6 hash key 2 */
1142 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1143 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1144 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1145 offset > 0 && byte < n;
1147 if (oword.eo_u8[offset - 1] != key[byte++]) {
1153 /* Verify Toeplitz IPv6 hash key 1 */
1154 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1155 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1156 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1157 offset > 0 && byte < n;
1159 if (oword.eo_u8[offset - 1] != key[byte++]) {
1177 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1183 #if EFSYS_OPT_RX_SCALE
1184 static __checkReturn efx_rc_t
1185 siena_rx_scale_tbl_set(
1186 __in efx_nic_t *enp,
1187 __in uint32_t rss_context,
1188 __in_ecount(n) unsigned int *table,
1195 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
1196 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
1198 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1203 if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
1208 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
1211 /* Calculate the entry to place in the table */
1212 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1214 EFSYS_PROBE2(table, int, index, uint32_t, byte);
1216 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
1218 /* Write the table */
1219 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1220 index, &oword, B_TRUE);
1223 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
1226 /* Determine if we're starting a new batch */
1227 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1229 /* Read the table */
1230 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
1231 index, &oword, B_TRUE);
1233 /* Verify the entry */
1234 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1247 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1254 * Falcon/Siena pseudo-header
1255 * --------------------------
1257 * Receive packets are prefixed by an optional 16 byte pseudo-header.
1258 * The pseudo-header is a byte array of one of the forms:
1260 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1261 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1262 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1265 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
1266 * LL.LL LFSR hash (16-bit big-endian)
1269 #if EFSYS_OPT_RX_SCALE
1270 static __checkReturn uint32_t
1271 siena_rx_prefix_hash(
1272 __in efx_nic_t *enp,
1273 __in efx_rx_hash_alg_t func,
1274 __in uint8_t *buffer)
1276 _NOTE(ARGUNUSED(enp))
1279 case EFX_RX_HASHALG_TOEPLITZ:
1280 return ((buffer[12] << 24) |
1281 (buffer[13] << 16) |
1285 case EFX_RX_HASHALG_LFSR:
1286 return ((buffer[14] << 8) | buffer[15]);
1293 #endif /* EFSYS_OPT_RX_SCALE */
1295 static __checkReturn efx_rc_t
1296 siena_rx_prefix_pktlen(
1297 __in efx_nic_t *enp,
1298 __in uint8_t *buffer,
1299 __out uint16_t *lengthp)
1301 _NOTE(ARGUNUSED(enp, buffer, lengthp))
1303 /* Not supported by Falcon/Siena hardware */
1311 __in efx_rxq_t *erp,
1312 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1314 __in unsigned int ndescs,
1315 __in unsigned int completed,
1316 __in unsigned int added)
1320 unsigned int offset;
1323 /* The client driver must not overfill the queue */
1324 EFSYS_ASSERT3U(added - completed + ndescs, <=,
1325 EFX_RXQ_LIMIT(erp->er_mask + 1));
1327 id = added & (erp->er_mask);
1328 for (i = 0; i < ndescs; i++) {
1329 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1330 unsigned int, id, efsys_dma_addr_t, addrp[i],
1333 EFX_POPULATE_QWORD_3(qword,
1334 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1335 FSF_AZ_RX_KER_BUF_ADDR_DW0,
1336 (uint32_t)(addrp[i] & 0xffffffff),
1337 FSF_AZ_RX_KER_BUF_ADDR_DW1,
1338 (uint32_t)(addrp[i] >> 32));
1340 offset = id * sizeof (efx_qword_t);
1341 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1343 id = (id + 1) & (erp->er_mask);
1349 __in efx_rxq_t *erp,
1350 __in unsigned int added,
1351 __inout unsigned int *pushedp)
1353 efx_nic_t *enp = erp->er_enp;
1354 unsigned int pushed = *pushedp;
1359 /* All descriptors are pushed */
1362 /* Push the populated descriptors out */
1363 wptr = added & erp->er_mask;
1365 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1367 /* Only write the third DWORD */
1368 EFX_POPULATE_DWORD_1(dword,
1369 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1371 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1372 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1373 wptr, pushed & erp->er_mask);
1374 EFSYS_PIO_WRITE_BARRIER();
1375 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1376 erp->er_index, &dword, B_FALSE);
1379 #if EFSYS_OPT_RX_PACKED_STREAM
1381 siena_rx_qpush_ps_credits(
1382 __in efx_rxq_t *erp)
1384 /* Not supported by Siena hardware */
1389 siena_rx_qps_packet_info(
1390 __in efx_rxq_t *erp,
1391 __in uint8_t *buffer,
1392 __in uint32_t buffer_length,
1393 __in uint32_t current_offset,
1394 __out uint16_t *lengthp,
1395 __out uint32_t *next_offsetp,
1396 __out uint32_t *timestamp)
1398 /* Not supported by Siena hardware */
1403 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1405 static __checkReturn efx_rc_t
1407 __in efx_rxq_t *erp)
1409 efx_nic_t *enp = erp->er_enp;
1413 label = erp->er_index;
1415 /* Flush the queue */
1416 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1417 FRF_AZ_RX_FLUSH_DESCQ, label);
1418 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1425 __in efx_rxq_t *erp)
1427 efx_nic_t *enp = erp->er_enp;
1430 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1432 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1433 erp->er_index, &oword, B_TRUE);
1435 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1436 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1437 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1439 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1440 erp->er_index, &oword, B_TRUE);
1443 static __checkReturn efx_rc_t
1445 __in efx_nic_t *enp,
1446 __in unsigned int index,
1447 __in unsigned int label,
1448 __in efx_rxq_type_t type,
1449 __in uint32_t type_data,
1450 __in efsys_mem_t *esmp,
1453 __in unsigned int flags,
1454 __in efx_evq_t *eep,
1455 __in efx_rxq_t *erp)
1457 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1460 boolean_t jumbo = B_FALSE;
1463 _NOTE(ARGUNUSED(esmp))
1464 _NOTE(ARGUNUSED(type_data))
1466 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1467 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1468 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1469 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1471 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1472 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1474 if (!ISP2(ndescs) ||
1475 (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
1479 if (index >= encp->enc_rxq_limit) {
1483 for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1485 if ((1 << size) == (int)(ndescs / EFX_RXQ_MINNDESCS))
1487 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1493 case EFX_RXQ_TYPE_DEFAULT:
1501 if (flags & EFX_RXQ_FLAG_SCATTER) {
1502 #if EFSYS_OPT_RX_SCATTER
1507 #endif /* EFSYS_OPT_RX_SCATTER */
1510 /* Set up the new descriptor queue */
1511 EFX_POPULATE_OWORD_7(oword,
1512 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1513 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1514 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1515 FRF_AZ_RX_DESCQ_LABEL, label,
1516 FRF_AZ_RX_DESCQ_SIZE, size,
1517 FRF_AZ_RX_DESCQ_TYPE, 0,
1518 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1520 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1521 erp->er_index, &oword, B_TRUE);
1525 #if !EFSYS_OPT_RX_SCATTER
1536 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1543 __in efx_rxq_t *erp)
1545 efx_nic_t *enp = erp->er_enp;
1548 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1549 --enp->en_rx_qcount;
1551 /* Purge descriptor queue */
1552 EFX_ZERO_OWORD(oword);
1554 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1555 erp->er_index, &oword, B_TRUE);
1557 /* Free the RXQ object */
1558 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1563 __in efx_nic_t *enp)
1565 _NOTE(ARGUNUSED(enp))
1568 #endif /* EFSYS_OPT_SIENA */