1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
13 static __checkReturn efx_rc_t
21 #if EFSYS_OPT_RX_SCATTER
22 static __checkReturn efx_rc_t
23 siena_rx_scatter_enable(
25 __in unsigned int buf_size);
26 #endif /* EFSYS_OPT_RX_SCATTER */
28 #if EFSYS_OPT_RX_SCALE
29 static __checkReturn efx_rc_t
30 siena_rx_scale_mode_set(
32 __in uint32_t rss_context,
33 __in efx_rx_hash_alg_t alg,
34 __in efx_rx_hash_type_t type,
35 __in boolean_t insert);
37 static __checkReturn efx_rc_t
38 siena_rx_scale_key_set(
40 __in uint32_t rss_context,
41 __in_ecount(n) uint8_t *key,
44 static __checkReturn efx_rc_t
45 siena_rx_scale_tbl_set(
47 __in uint32_t rss_context,
48 __in_ecount(n) unsigned int *table,
51 static __checkReturn uint32_t
54 __in efx_rx_hash_alg_t func,
55 __in uint8_t *buffer);
57 #endif /* EFSYS_OPT_RX_SCALE */
59 static __checkReturn efx_rc_t
60 siena_rx_prefix_pktlen(
63 __out uint16_t *lengthp);
68 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
70 __in unsigned int ndescs,
71 __in unsigned int completed,
72 __in unsigned int added);
77 __in unsigned int added,
78 __inout unsigned int *pushedp);
80 #if EFSYS_OPT_RX_PACKED_STREAM
82 siena_rx_qpush_ps_credits(
85 static __checkReturn uint8_t *
86 siena_rx_qps_packet_info(
89 __in uint32_t buffer_length,
90 __in uint32_t current_offset,
91 __out uint16_t *lengthp,
92 __out uint32_t *next_offsetp,
93 __out uint32_t *timestamp);
96 static __checkReturn efx_rc_t
102 __in efx_rxq_t *erp);
104 static __checkReturn efx_rc_t
107 __in unsigned int index,
108 __in unsigned int label,
109 __in efx_rxq_type_t type,
110 __in const efx_rxq_type_data_t *type_data,
111 __in efsys_mem_t *esmp,
114 __in unsigned int flags,
116 __in efx_rxq_t *erp);
120 __in efx_rxq_t *erp);
122 #endif /* EFSYS_OPT_SIENA */
126 static const efx_rx_ops_t __efx_rx_siena_ops = {
127 siena_rx_init, /* erxo_init */
128 siena_rx_fini, /* erxo_fini */
129 #if EFSYS_OPT_RX_SCATTER
130 siena_rx_scatter_enable, /* erxo_scatter_enable */
132 #if EFSYS_OPT_RX_SCALE
133 NULL, /* erxo_scale_context_alloc */
134 NULL, /* erxo_scale_context_free */
135 siena_rx_scale_mode_set, /* erxo_scale_mode_set */
136 siena_rx_scale_key_set, /* erxo_scale_key_set */
137 siena_rx_scale_tbl_set, /* erxo_scale_tbl_set */
138 siena_rx_prefix_hash, /* erxo_prefix_hash */
140 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
141 siena_rx_qpost, /* erxo_qpost */
142 siena_rx_qpush, /* erxo_qpush */
143 #if EFSYS_OPT_RX_PACKED_STREAM
144 siena_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
145 siena_rx_qps_packet_info, /* erxo_qps_packet_info */
147 siena_rx_qflush, /* erxo_qflush */
148 siena_rx_qenable, /* erxo_qenable */
149 siena_rx_qcreate, /* erxo_qcreate */
150 siena_rx_qdestroy, /* erxo_qdestroy */
152 #endif /* EFSYS_OPT_SIENA */
154 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
155 static const efx_rx_ops_t __efx_rx_ef10_ops = {
156 ef10_rx_init, /* erxo_init */
157 ef10_rx_fini, /* erxo_fini */
158 #if EFSYS_OPT_RX_SCATTER
159 ef10_rx_scatter_enable, /* erxo_scatter_enable */
161 #if EFSYS_OPT_RX_SCALE
162 ef10_rx_scale_context_alloc, /* erxo_scale_context_alloc */
163 ef10_rx_scale_context_free, /* erxo_scale_context_free */
164 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */
165 ef10_rx_scale_key_set, /* erxo_scale_key_set */
166 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */
167 ef10_rx_prefix_hash, /* erxo_prefix_hash */
169 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
170 ef10_rx_qpost, /* erxo_qpost */
171 ef10_rx_qpush, /* erxo_qpush */
172 #if EFSYS_OPT_RX_PACKED_STREAM
173 ef10_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
174 ef10_rx_qps_packet_info, /* erxo_qps_packet_info */
176 ef10_rx_qflush, /* erxo_qflush */
177 ef10_rx_qenable, /* erxo_qenable */
178 ef10_rx_qcreate, /* erxo_qcreate */
179 ef10_rx_qdestroy, /* erxo_qdestroy */
181 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
184 __checkReturn efx_rc_t
186 __inout efx_nic_t *enp)
188 const efx_rx_ops_t *erxop;
191 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
192 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
194 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
199 if (enp->en_mod_flags & EFX_MOD_RX) {
204 switch (enp->en_family) {
206 case EFX_FAMILY_SIENA:
207 erxop = &__efx_rx_siena_ops;
209 #endif /* EFSYS_OPT_SIENA */
211 #if EFSYS_OPT_HUNTINGTON
212 case EFX_FAMILY_HUNTINGTON:
213 erxop = &__efx_rx_ef10_ops;
215 #endif /* EFSYS_OPT_HUNTINGTON */
217 #if EFSYS_OPT_MEDFORD
218 case EFX_FAMILY_MEDFORD:
219 erxop = &__efx_rx_ef10_ops;
221 #endif /* EFSYS_OPT_MEDFORD */
223 #if EFSYS_OPT_MEDFORD2
224 case EFX_FAMILY_MEDFORD2:
225 erxop = &__efx_rx_ef10_ops;
227 #endif /* EFSYS_OPT_MEDFORD2 */
235 if ((rc = erxop->erxo_init(enp)) != 0)
238 enp->en_erxop = erxop;
239 enp->en_mod_flags |= EFX_MOD_RX;
249 EFSYS_PROBE1(fail1, efx_rc_t, rc);
251 enp->en_erxop = NULL;
252 enp->en_mod_flags &= ~EFX_MOD_RX;
260 const efx_rx_ops_t *erxop = enp->en_erxop;
262 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
263 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
264 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
265 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
267 erxop->erxo_fini(enp);
269 enp->en_erxop = NULL;
270 enp->en_mod_flags &= ~EFX_MOD_RX;
273 #if EFSYS_OPT_RX_SCATTER
274 __checkReturn efx_rc_t
275 efx_rx_scatter_enable(
277 __in unsigned int buf_size)
279 const efx_rx_ops_t *erxop = enp->en_erxop;
282 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
283 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
285 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
291 EFSYS_PROBE1(fail1, efx_rc_t, rc);
294 #endif /* EFSYS_OPT_RX_SCATTER */
296 #if EFSYS_OPT_RX_SCALE
297 __checkReturn efx_rc_t
298 efx_rx_scale_hash_flags_get(
300 __in efx_rx_hash_alg_t hash_alg,
301 __inout_ecount(EFX_RX_HASH_NFLAGS) unsigned int *flags,
302 __out unsigned int *nflagsp)
304 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
306 boolean_t additional_modes;
307 unsigned int *entryp = flags;
310 if (flags == NULL || nflagsp == NULL) {
315 l4 = encp->enc_rx_scale_l4_hash_supported;
316 additional_modes = encp->enc_rx_scale_additional_modes_supported;
318 #define LIST_FLAGS(_entryp, _class, _l4_hashing, _additional_modes) \
321 *(_entryp++) = EFX_RX_HASH(_class, 4TUPLE); \
323 if (_additional_modes) { \
325 EFX_RX_HASH(_class, 2TUPLE_DST); \
327 EFX_RX_HASH(_class, 2TUPLE_SRC); \
331 *(_entryp++) = EFX_RX_HASH(_class, 2TUPLE); \
333 if (_additional_modes) { \
334 *(_entryp++) = EFX_RX_HASH(_class, 1TUPLE_DST); \
335 *(_entryp++) = EFX_RX_HASH(_class, 1TUPLE_SRC); \
338 *(_entryp++) = EFX_RX_HASH(_class, DISABLE); \
340 _NOTE(CONSTANTCONDITION) \
344 case EFX_RX_HASHALG_PACKED_STREAM:
345 if ((encp->enc_rx_scale_hash_alg_mask & (1U << hash_alg)) == 0)
348 case EFX_RX_HASHALG_TOEPLITZ:
349 if ((encp->enc_rx_scale_hash_alg_mask & (1U << hash_alg)) == 0)
352 LIST_FLAGS(entryp, IPV4_TCP, l4, additional_modes);
353 LIST_FLAGS(entryp, IPV6_TCP, l4, additional_modes);
355 if (additional_modes) {
356 LIST_FLAGS(entryp, IPV4_UDP, l4, additional_modes);
357 LIST_FLAGS(entryp, IPV6_UDP, l4, additional_modes);
360 LIST_FLAGS(entryp, IPV4, B_FALSE, additional_modes);
361 LIST_FLAGS(entryp, IPV6, B_FALSE, additional_modes);
371 *nflagsp = (unsigned int)(entryp - flags);
372 EFSYS_ASSERT3U(*nflagsp, <=, EFX_RX_HASH_NFLAGS);
380 EFSYS_PROBE1(fail1, efx_rc_t, rc);
385 __checkReturn efx_rc_t
386 efx_rx_hash_default_support_get(
388 __out efx_rx_hash_support_t *supportp)
392 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
393 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
395 if (supportp == NULL) {
401 * Report the hashing support the client gets by default if it
402 * does not allocate an RSS context itself.
404 *supportp = enp->en_hash_support;
409 EFSYS_PROBE1(fail1, efx_rc_t, rc);
414 __checkReturn efx_rc_t
415 efx_rx_scale_default_support_get(
417 __out efx_rx_scale_context_type_t *typep)
421 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
422 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
430 * Report the RSS support the client gets by default if it
431 * does not allocate an RSS context itself.
433 *typep = enp->en_rss_context_type;
438 EFSYS_PROBE1(fail1, efx_rc_t, rc);
442 #endif /* EFSYS_OPT_RX_SCALE */
444 #if EFSYS_OPT_RX_SCALE
445 __checkReturn efx_rc_t
446 efx_rx_scale_context_alloc(
448 __in efx_rx_scale_context_type_t type,
449 __in uint32_t num_queues,
450 __out uint32_t *rss_contextp)
452 const efx_rx_ops_t *erxop = enp->en_erxop;
455 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
456 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
458 if (erxop->erxo_scale_context_alloc == NULL) {
462 if ((rc = erxop->erxo_scale_context_alloc(enp, type,
463 num_queues, rss_contextp)) != 0) {
472 EFSYS_PROBE1(fail1, efx_rc_t, rc);
475 #endif /* EFSYS_OPT_RX_SCALE */
477 #if EFSYS_OPT_RX_SCALE
478 __checkReturn efx_rc_t
479 efx_rx_scale_context_free(
481 __in uint32_t rss_context)
483 const efx_rx_ops_t *erxop = enp->en_erxop;
486 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
487 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
489 if (erxop->erxo_scale_context_free == NULL) {
493 if ((rc = erxop->erxo_scale_context_free(enp, rss_context)) != 0)
501 EFSYS_PROBE1(fail1, efx_rc_t, rc);
504 #endif /* EFSYS_OPT_RX_SCALE */
506 #if EFSYS_OPT_RX_SCALE
507 __checkReturn efx_rc_t
508 efx_rx_scale_mode_set(
510 __in uint32_t rss_context,
511 __in efx_rx_hash_alg_t alg,
512 __in efx_rx_hash_type_t type,
513 __in boolean_t insert)
515 const efx_rx_ops_t *erxop = enp->en_erxop;
516 unsigned int type_flags[EFX_RX_HASH_NFLAGS];
517 unsigned int type_nflags;
518 efx_rx_hash_type_t type_check;
522 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
523 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
526 * Legacy flags and modern bits cannot be
527 * used at the same time in the hash type.
529 if ((type & EFX_RX_HASH_LEGACY_MASK) &&
530 (type & ~EFX_RX_HASH_LEGACY_MASK)) {
536 * Translate legacy flags to the new representation
537 * so that chip-specific handlers will consider the
540 if (type & EFX_RX_HASH_IPV4) {
541 type |= EFX_RX_HASH(IPV4, 2TUPLE);
542 type |= EFX_RX_HASH(IPV4_TCP, 2TUPLE);
543 type |= EFX_RX_HASH(IPV4_UDP, 2TUPLE);
546 if (type & EFX_RX_HASH_TCPIPV4)
547 type |= EFX_RX_HASH(IPV4_TCP, 4TUPLE);
549 if (type & EFX_RX_HASH_IPV6) {
550 type |= EFX_RX_HASH(IPV6, 2TUPLE);
551 type |= EFX_RX_HASH(IPV6_TCP, 2TUPLE);
552 type |= EFX_RX_HASH(IPV6_UDP, 2TUPLE);
555 if (type & EFX_RX_HASH_TCPIPV6)
556 type |= EFX_RX_HASH(IPV6_TCP, 4TUPLE);
558 type &= ~EFX_RX_HASH_LEGACY_MASK;
562 * Get the list of supported hash flags and sanitise the input.
564 rc = efx_rx_scale_hash_flags_get(enp, alg, type_flags, &type_nflags);
568 for (i = 0; i < type_nflags; ++i) {
569 if ((type_check & type_flags[i]) == type_flags[i])
570 type_check &= ~(type_flags[i]);
573 if (type_check != 0) {
578 if (erxop->erxo_scale_mode_set != NULL) {
579 if ((rc = erxop->erxo_scale_mode_set(enp, rss_context, alg,
593 EFSYS_PROBE1(fail1, efx_rc_t, rc);
596 #endif /* EFSYS_OPT_RX_SCALE */
598 #if EFSYS_OPT_RX_SCALE
599 __checkReturn efx_rc_t
600 efx_rx_scale_key_set(
602 __in uint32_t rss_context,
603 __in_ecount(n) uint8_t *key,
606 const efx_rx_ops_t *erxop = enp->en_erxop;
609 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
610 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
612 if ((rc = erxop->erxo_scale_key_set(enp, rss_context, key, n)) != 0)
618 EFSYS_PROBE1(fail1, efx_rc_t, rc);
622 #endif /* EFSYS_OPT_RX_SCALE */
624 #if EFSYS_OPT_RX_SCALE
625 __checkReturn efx_rc_t
626 efx_rx_scale_tbl_set(
628 __in uint32_t rss_context,
629 __in_ecount(n) unsigned int *table,
632 const efx_rx_ops_t *erxop = enp->en_erxop;
635 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
636 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
638 if ((rc = erxop->erxo_scale_tbl_set(enp, rss_context, table, n)) != 0)
644 EFSYS_PROBE1(fail1, efx_rc_t, rc);
648 #endif /* EFSYS_OPT_RX_SCALE */
653 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
655 __in unsigned int ndescs,
656 __in unsigned int completed,
657 __in unsigned int added)
659 efx_nic_t *enp = erp->er_enp;
660 const efx_rx_ops_t *erxop = enp->en_erxop;
662 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
664 erxop->erxo_qpost(erp, addrp, size, ndescs, completed, added);
667 #if EFSYS_OPT_RX_PACKED_STREAM
670 efx_rx_qpush_ps_credits(
673 efx_nic_t *enp = erp->er_enp;
674 const efx_rx_ops_t *erxop = enp->en_erxop;
676 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
678 erxop->erxo_qpush_ps_credits(erp);
681 __checkReturn uint8_t *
682 efx_rx_qps_packet_info(
684 __in uint8_t *buffer,
685 __in uint32_t buffer_length,
686 __in uint32_t current_offset,
687 __out uint16_t *lengthp,
688 __out uint32_t *next_offsetp,
689 __out uint32_t *timestamp)
691 efx_nic_t *enp = erp->er_enp;
692 const efx_rx_ops_t *erxop = enp->en_erxop;
694 return (erxop->erxo_qps_packet_info(erp, buffer,
695 buffer_length, current_offset, lengthp,
696 next_offsetp, timestamp));
699 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
704 __in unsigned int added,
705 __inout unsigned int *pushedp)
707 efx_nic_t *enp = erp->er_enp;
708 const efx_rx_ops_t *erxop = enp->en_erxop;
710 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
712 erxop->erxo_qpush(erp, added, pushedp);
715 __checkReturn efx_rc_t
719 efx_nic_t *enp = erp->er_enp;
720 const efx_rx_ops_t *erxop = enp->en_erxop;
723 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
725 if ((rc = erxop->erxo_qflush(erp)) != 0)
731 EFSYS_PROBE1(fail1, efx_rc_t, rc);
740 efx_nic_t *enp = erp->er_enp;
741 const efx_rx_ops_t *erxop = enp->en_erxop;
743 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
745 erxop->erxo_qenable(erp);
748 static __checkReturn efx_rc_t
749 efx_rx_qcreate_internal(
751 __in unsigned int index,
752 __in unsigned int label,
753 __in efx_rxq_type_t type,
754 __in const efx_rxq_type_data_t *type_data,
755 __in efsys_mem_t *esmp,
758 __in unsigned int flags,
760 __deref_out efx_rxq_t **erpp)
762 const efx_rx_ops_t *erxop = enp->en_erxop;
766 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
767 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
769 /* Allocate an RXQ object */
770 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
777 erp->er_magic = EFX_RXQ_MAGIC;
779 erp->er_index = index;
780 erp->er_mask = ndescs - 1;
783 if ((rc = erxop->erxo_qcreate(enp, index, label, type, type_data, esmp,
784 ndescs, id, flags, eep, erp)) != 0)
795 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
797 EFSYS_PROBE1(fail1, efx_rc_t, rc);
802 __checkReturn efx_rc_t
805 __in unsigned int index,
806 __in unsigned int label,
807 __in efx_rxq_type_t type,
808 __in efsys_mem_t *esmp,
811 __in unsigned int flags,
813 __deref_out efx_rxq_t **erpp)
815 return efx_rx_qcreate_internal(enp, index, label, type, NULL,
816 esmp, ndescs, id, flags, eep, erpp);
819 #if EFSYS_OPT_RX_PACKED_STREAM
821 __checkReturn efx_rc_t
822 efx_rx_qcreate_packed_stream(
824 __in unsigned int index,
825 __in unsigned int label,
826 __in uint32_t ps_buf_size,
827 __in efsys_mem_t *esmp,
830 __deref_out efx_rxq_t **erpp)
832 efx_rxq_type_data_t type_data;
834 memset(&type_data, 0, sizeof(type_data));
836 type_data.ertd_packed_stream.eps_buf_size = ps_buf_size;
838 return efx_rx_qcreate_internal(enp, index, label,
839 EFX_RXQ_TYPE_PACKED_STREAM, &type_data, esmp, ndescs,
840 0 /* id unused on EF10 */, EFX_RXQ_FLAG_NONE, eep, erpp);
849 efx_nic_t *enp = erp->er_enp;
850 const efx_rx_ops_t *erxop = enp->en_erxop;
852 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
854 erxop->erxo_qdestroy(erp);
857 __checkReturn efx_rc_t
858 efx_pseudo_hdr_pkt_length_get(
860 __in uint8_t *buffer,
861 __out uint16_t *lengthp)
863 efx_nic_t *enp = erp->er_enp;
864 const efx_rx_ops_t *erxop = enp->en_erxop;
866 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
868 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
871 #if EFSYS_OPT_RX_SCALE
872 __checkReturn uint32_t
873 efx_pseudo_hdr_hash_get(
875 __in efx_rx_hash_alg_t func,
876 __in uint8_t *buffer)
878 efx_nic_t *enp = erp->er_enp;
879 const efx_rx_ops_t *erxop = enp->en_erxop;
881 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
883 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
884 return (erxop->erxo_prefix_hash(enp, func, buffer));
886 #endif /* EFSYS_OPT_RX_SCALE */
890 static __checkReturn efx_rc_t
897 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
899 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
900 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
901 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
902 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
903 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
904 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
905 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
907 /* Zero the RSS table */
908 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
910 EFX_ZERO_OWORD(oword);
911 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
912 index, &oword, B_TRUE);
915 #if EFSYS_OPT_RX_SCALE
916 /* The RSS key and indirection table are writable. */
917 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
919 /* Hardware can insert RX hash with/without RSS */
920 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
921 #endif /* EFSYS_OPT_RX_SCALE */
926 #if EFSYS_OPT_RX_SCATTER
927 static __checkReturn efx_rc_t
928 siena_rx_scatter_enable(
930 __in unsigned int buf_size)
936 nbuf32 = buf_size / 32;
938 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
939 ((buf_size % 32) != 0)) {
944 if (enp->en_rx_qcount > 0) {
949 /* Set scatter buffer size */
950 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
951 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
952 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
954 /* Enable scatter for packets not matching a filter */
955 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
956 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
957 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
964 EFSYS_PROBE1(fail1, efx_rc_t, rc);
968 #endif /* EFSYS_OPT_RX_SCATTER */
971 #define EFX_RX_LFSR_HASH(_enp, _insert) \
975 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
976 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
977 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
978 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
979 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
980 (_insert) ? 1 : 0); \
981 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
983 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
984 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
986 EFX_SET_OWORD_FIELD(oword, \
987 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
988 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
992 _NOTE(CONSTANTCONDITION) \
995 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
999 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1000 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
1001 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
1003 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
1005 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
1006 (_insert) ? 1 : 0); \
1007 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1009 _NOTE(CONSTANTCONDITION) \
1012 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
1014 efx_oword_t oword; \
1016 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1017 EFX_SET_OWORD_FIELD(oword, \
1018 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
1019 EFX_SET_OWORD_FIELD(oword, \
1020 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
1021 EFX_SET_OWORD_FIELD(oword, \
1022 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
1023 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1027 _NOTE(CONSTANTCONDITION) \
1031 #if EFSYS_OPT_RX_SCALE
1033 static __checkReturn efx_rc_t
1034 siena_rx_scale_mode_set(
1035 __in efx_nic_t *enp,
1036 __in uint32_t rss_context,
1037 __in efx_rx_hash_alg_t alg,
1038 __in efx_rx_hash_type_t type,
1039 __in boolean_t insert)
1041 efx_rx_hash_type_t type_ipv4 = EFX_RX_HASH(IPV4, 2TUPLE);
1042 efx_rx_hash_type_t type_ipv4_tcp = EFX_RX_HASH(IPV4_TCP, 4TUPLE);
1043 efx_rx_hash_type_t type_ipv6 = EFX_RX_HASH(IPV6, 2TUPLE);
1044 efx_rx_hash_type_t type_ipv6_tcp = EFX_RX_HASH(IPV6_TCP, 4TUPLE);
1047 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1053 case EFX_RX_HASHALG_LFSR:
1054 EFX_RX_LFSR_HASH(enp, insert);
1057 case EFX_RX_HASHALG_TOEPLITZ:
1058 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
1059 (type & type_ipv4) == type_ipv4,
1060 (type & type_ipv4_tcp) == type_ipv4_tcp);
1062 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
1063 (type & type_ipv6) == type_ipv6,
1064 (type & type_ipv6_tcp) == type_ipv6_tcp,
1083 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1085 EFX_RX_LFSR_HASH(enp, B_FALSE);
1091 #if EFSYS_OPT_RX_SCALE
1092 static __checkReturn efx_rc_t
1093 siena_rx_scale_key_set(
1094 __in efx_nic_t *enp,
1095 __in uint32_t rss_context,
1096 __in_ecount(n) uint8_t *key,
1101 unsigned int offset;
1104 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1111 /* Write Toeplitz IPv4 hash key */
1112 EFX_ZERO_OWORD(oword);
1113 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1114 offset > 0 && byte < n;
1116 oword.eo_u8[offset - 1] = key[byte++];
1118 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1122 /* Verify Toeplitz IPv4 hash key */
1123 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1124 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1125 offset > 0 && byte < n;
1127 if (oword.eo_u8[offset - 1] != key[byte++]) {
1133 if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
1138 /* Write Toeplitz IPv6 hash key 3 */
1139 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1140 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1141 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1142 offset > 0 && byte < n;
1144 oword.eo_u8[offset - 1] = key[byte++];
1146 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1148 /* Write Toeplitz IPv6 hash key 2 */
1149 EFX_ZERO_OWORD(oword);
1150 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1151 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1152 offset > 0 && byte < n;
1154 oword.eo_u8[offset - 1] = key[byte++];
1156 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1158 /* Write Toeplitz IPv6 hash key 1 */
1159 EFX_ZERO_OWORD(oword);
1160 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1161 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1162 offset > 0 && byte < n;
1164 oword.eo_u8[offset - 1] = key[byte++];
1166 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1170 /* Verify Toeplitz IPv6 hash key 3 */
1171 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1172 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1173 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1174 offset > 0 && byte < n;
1176 if (oword.eo_u8[offset - 1] != key[byte++]) {
1182 /* Verify Toeplitz IPv6 hash key 2 */
1183 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1184 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1185 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1186 offset > 0 && byte < n;
1188 if (oword.eo_u8[offset - 1] != key[byte++]) {
1194 /* Verify Toeplitz IPv6 hash key 1 */
1195 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1196 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1197 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1198 offset > 0 && byte < n;
1200 if (oword.eo_u8[offset - 1] != key[byte++]) {
1218 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1224 #if EFSYS_OPT_RX_SCALE
1225 static __checkReturn efx_rc_t
1226 siena_rx_scale_tbl_set(
1227 __in efx_nic_t *enp,
1228 __in uint32_t rss_context,
1229 __in_ecount(n) unsigned int *table,
1236 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
1237 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
1239 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1244 if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
1249 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
1252 /* Calculate the entry to place in the table */
1253 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1255 EFSYS_PROBE2(table, int, index, uint32_t, byte);
1257 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
1259 /* Write the table */
1260 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1261 index, &oword, B_TRUE);
1264 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
1267 /* Determine if we're starting a new batch */
1268 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1270 /* Read the table */
1271 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
1272 index, &oword, B_TRUE);
1274 /* Verify the entry */
1275 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1288 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1295 * Falcon/Siena pseudo-header
1296 * --------------------------
1298 * Receive packets are prefixed by an optional 16 byte pseudo-header.
1299 * The pseudo-header is a byte array of one of the forms:
1301 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1302 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1303 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1306 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
1307 * LL.LL LFSR hash (16-bit big-endian)
1310 #if EFSYS_OPT_RX_SCALE
1311 static __checkReturn uint32_t
1312 siena_rx_prefix_hash(
1313 __in efx_nic_t *enp,
1314 __in efx_rx_hash_alg_t func,
1315 __in uint8_t *buffer)
1317 _NOTE(ARGUNUSED(enp))
1320 case EFX_RX_HASHALG_TOEPLITZ:
1321 return ((buffer[12] << 24) |
1322 (buffer[13] << 16) |
1326 case EFX_RX_HASHALG_LFSR:
1327 return ((buffer[14] << 8) | buffer[15]);
1334 #endif /* EFSYS_OPT_RX_SCALE */
1336 static __checkReturn efx_rc_t
1337 siena_rx_prefix_pktlen(
1338 __in efx_nic_t *enp,
1339 __in uint8_t *buffer,
1340 __out uint16_t *lengthp)
1342 _NOTE(ARGUNUSED(enp, buffer, lengthp))
1344 /* Not supported by Falcon/Siena hardware */
1352 __in efx_rxq_t *erp,
1353 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1355 __in unsigned int ndescs,
1356 __in unsigned int completed,
1357 __in unsigned int added)
1361 unsigned int offset;
1364 /* The client driver must not overfill the queue */
1365 EFSYS_ASSERT3U(added - completed + ndescs, <=,
1366 EFX_RXQ_LIMIT(erp->er_mask + 1));
1368 id = added & (erp->er_mask);
1369 for (i = 0; i < ndescs; i++) {
1370 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1371 unsigned int, id, efsys_dma_addr_t, addrp[i],
1374 EFX_POPULATE_QWORD_3(qword,
1375 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1376 FSF_AZ_RX_KER_BUF_ADDR_DW0,
1377 (uint32_t)(addrp[i] & 0xffffffff),
1378 FSF_AZ_RX_KER_BUF_ADDR_DW1,
1379 (uint32_t)(addrp[i] >> 32));
1381 offset = id * sizeof (efx_qword_t);
1382 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1384 id = (id + 1) & (erp->er_mask);
1390 __in efx_rxq_t *erp,
1391 __in unsigned int added,
1392 __inout unsigned int *pushedp)
1394 efx_nic_t *enp = erp->er_enp;
1395 unsigned int pushed = *pushedp;
1400 /* All descriptors are pushed */
1403 /* Push the populated descriptors out */
1404 wptr = added & erp->er_mask;
1406 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1408 /* Only write the third DWORD */
1409 EFX_POPULATE_DWORD_1(dword,
1410 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1412 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1413 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1414 wptr, pushed & erp->er_mask);
1415 EFSYS_PIO_WRITE_BARRIER();
1416 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1417 erp->er_index, &dword, B_FALSE);
1420 #if EFSYS_OPT_RX_PACKED_STREAM
1422 siena_rx_qpush_ps_credits(
1423 __in efx_rxq_t *erp)
1425 /* Not supported by Siena hardware */
1430 siena_rx_qps_packet_info(
1431 __in efx_rxq_t *erp,
1432 __in uint8_t *buffer,
1433 __in uint32_t buffer_length,
1434 __in uint32_t current_offset,
1435 __out uint16_t *lengthp,
1436 __out uint32_t *next_offsetp,
1437 __out uint32_t *timestamp)
1439 /* Not supported by Siena hardware */
1444 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1446 static __checkReturn efx_rc_t
1448 __in efx_rxq_t *erp)
1450 efx_nic_t *enp = erp->er_enp;
1454 label = erp->er_index;
1456 /* Flush the queue */
1457 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1458 FRF_AZ_RX_FLUSH_DESCQ, label);
1459 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1466 __in efx_rxq_t *erp)
1468 efx_nic_t *enp = erp->er_enp;
1471 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1473 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1474 erp->er_index, &oword, B_TRUE);
1476 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1477 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1478 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1480 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1481 erp->er_index, &oword, B_TRUE);
1484 static __checkReturn efx_rc_t
1486 __in efx_nic_t *enp,
1487 __in unsigned int index,
1488 __in unsigned int label,
1489 __in efx_rxq_type_t type,
1490 __in const efx_rxq_type_data_t *type_data,
1491 __in efsys_mem_t *esmp,
1494 __in unsigned int flags,
1495 __in efx_evq_t *eep,
1496 __in efx_rxq_t *erp)
1498 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1501 boolean_t jumbo = B_FALSE;
1504 _NOTE(ARGUNUSED(esmp))
1505 _NOTE(ARGUNUSED(type_data))
1507 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1508 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1509 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1510 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1512 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1513 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1515 if (!ISP2(ndescs) ||
1516 (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
1520 if (index >= encp->enc_rxq_limit) {
1524 for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1526 if ((1 << size) == (int)(ndescs / EFX_RXQ_MINNDESCS))
1528 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1534 case EFX_RXQ_TYPE_DEFAULT:
1542 if (flags & EFX_RXQ_FLAG_SCATTER) {
1543 #if EFSYS_OPT_RX_SCATTER
1548 #endif /* EFSYS_OPT_RX_SCATTER */
1551 /* Set up the new descriptor queue */
1552 EFX_POPULATE_OWORD_7(oword,
1553 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1554 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1555 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1556 FRF_AZ_RX_DESCQ_LABEL, label,
1557 FRF_AZ_RX_DESCQ_SIZE, size,
1558 FRF_AZ_RX_DESCQ_TYPE, 0,
1559 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1561 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1562 erp->er_index, &oword, B_TRUE);
1566 #if !EFSYS_OPT_RX_SCATTER
1577 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1584 __in efx_rxq_t *erp)
1586 efx_nic_t *enp = erp->er_enp;
1589 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1590 --enp->en_rx_qcount;
1592 /* Purge descriptor queue */
1593 EFX_ZERO_OWORD(oword);
1595 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1596 erp->er_index, &oword, B_TRUE);
1598 /* Free the RXQ object */
1599 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1604 __in efx_nic_t *enp)
1606 _NOTE(ARGUNUSED(enp))
1609 #endif /* EFSYS_OPT_SIENA */