1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
13 static __checkReturn efx_rc_t
21 #if EFSYS_OPT_RX_SCATTER
22 static __checkReturn efx_rc_t
23 siena_rx_scatter_enable(
25 __in unsigned int buf_size);
26 #endif /* EFSYS_OPT_RX_SCATTER */
28 #if EFSYS_OPT_RX_SCALE
29 static __checkReturn efx_rc_t
30 siena_rx_scale_mode_set(
32 __in uint32_t rss_context,
33 __in efx_rx_hash_alg_t alg,
34 __in efx_rx_hash_type_t type,
35 __in boolean_t insert);
37 static __checkReturn efx_rc_t
38 siena_rx_scale_key_set(
40 __in uint32_t rss_context,
41 __in_ecount(n) uint8_t *key,
44 static __checkReturn efx_rc_t
45 siena_rx_scale_tbl_set(
47 __in uint32_t rss_context,
48 __in_ecount(n) unsigned int *table,
51 static __checkReturn uint32_t
54 __in efx_rx_hash_alg_t func,
55 __in uint8_t *buffer);
57 #endif /* EFSYS_OPT_RX_SCALE */
59 static __checkReturn efx_rc_t
60 siena_rx_prefix_pktlen(
63 __out uint16_t *lengthp);
68 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
70 __in unsigned int ndescs,
71 __in unsigned int completed,
72 __in unsigned int added);
77 __in unsigned int added,
78 __inout unsigned int *pushedp);
80 #if EFSYS_OPT_RX_PACKED_STREAM
82 siena_rx_qpush_ps_credits(
85 static __checkReturn uint8_t *
86 siena_rx_qps_packet_info(
89 __in uint32_t buffer_length,
90 __in uint32_t current_offset,
91 __out uint16_t *lengthp,
92 __out uint32_t *next_offsetp,
93 __out uint32_t *timestamp);
96 static __checkReturn efx_rc_t
102 __in efx_rxq_t *erp);
104 static __checkReturn efx_rc_t
107 __in unsigned int index,
108 __in unsigned int label,
109 __in efx_rxq_type_t type,
110 __in uint32_t type_data,
111 __in efsys_mem_t *esmp,
114 __in unsigned int flags,
116 __in efx_rxq_t *erp);
120 __in efx_rxq_t *erp);
122 #endif /* EFSYS_OPT_SIENA */
126 static const efx_rx_ops_t __efx_rx_siena_ops = {
127 siena_rx_init, /* erxo_init */
128 siena_rx_fini, /* erxo_fini */
129 #if EFSYS_OPT_RX_SCATTER
130 siena_rx_scatter_enable, /* erxo_scatter_enable */
132 #if EFSYS_OPT_RX_SCALE
133 NULL, /* erxo_scale_context_alloc */
134 NULL, /* erxo_scale_context_free */
135 siena_rx_scale_mode_set, /* erxo_scale_mode_set */
136 siena_rx_scale_key_set, /* erxo_scale_key_set */
137 siena_rx_scale_tbl_set, /* erxo_scale_tbl_set */
138 siena_rx_prefix_hash, /* erxo_prefix_hash */
140 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
141 siena_rx_qpost, /* erxo_qpost */
142 siena_rx_qpush, /* erxo_qpush */
143 #if EFSYS_OPT_RX_PACKED_STREAM
144 siena_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
145 siena_rx_qps_packet_info, /* erxo_qps_packet_info */
147 siena_rx_qflush, /* erxo_qflush */
148 siena_rx_qenable, /* erxo_qenable */
149 siena_rx_qcreate, /* erxo_qcreate */
150 siena_rx_qdestroy, /* erxo_qdestroy */
152 #endif /* EFSYS_OPT_SIENA */
154 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
155 static const efx_rx_ops_t __efx_rx_ef10_ops = {
156 ef10_rx_init, /* erxo_init */
157 ef10_rx_fini, /* erxo_fini */
158 #if EFSYS_OPT_RX_SCATTER
159 ef10_rx_scatter_enable, /* erxo_scatter_enable */
161 #if EFSYS_OPT_RX_SCALE
162 ef10_rx_scale_context_alloc, /* erxo_scale_context_alloc */
163 ef10_rx_scale_context_free, /* erxo_scale_context_free */
164 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */
165 ef10_rx_scale_key_set, /* erxo_scale_key_set */
166 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */
167 ef10_rx_prefix_hash, /* erxo_prefix_hash */
169 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
170 ef10_rx_qpost, /* erxo_qpost */
171 ef10_rx_qpush, /* erxo_qpush */
172 #if EFSYS_OPT_RX_PACKED_STREAM
173 ef10_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
174 ef10_rx_qps_packet_info, /* erxo_qps_packet_info */
176 ef10_rx_qflush, /* erxo_qflush */
177 ef10_rx_qenable, /* erxo_qenable */
178 ef10_rx_qcreate, /* erxo_qcreate */
179 ef10_rx_qdestroy, /* erxo_qdestroy */
181 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
184 __checkReturn efx_rc_t
186 __inout efx_nic_t *enp)
188 const efx_rx_ops_t *erxop;
191 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
192 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
194 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
199 if (enp->en_mod_flags & EFX_MOD_RX) {
204 switch (enp->en_family) {
206 case EFX_FAMILY_SIENA:
207 erxop = &__efx_rx_siena_ops;
209 #endif /* EFSYS_OPT_SIENA */
211 #if EFSYS_OPT_HUNTINGTON
212 case EFX_FAMILY_HUNTINGTON:
213 erxop = &__efx_rx_ef10_ops;
215 #endif /* EFSYS_OPT_HUNTINGTON */
217 #if EFSYS_OPT_MEDFORD
218 case EFX_FAMILY_MEDFORD:
219 erxop = &__efx_rx_ef10_ops;
221 #endif /* EFSYS_OPT_MEDFORD */
223 #if EFSYS_OPT_MEDFORD2
224 case EFX_FAMILY_MEDFORD2:
225 erxop = &__efx_rx_ef10_ops;
227 #endif /* EFSYS_OPT_MEDFORD2 */
235 if ((rc = erxop->erxo_init(enp)) != 0)
238 enp->en_erxop = erxop;
239 enp->en_mod_flags |= EFX_MOD_RX;
249 EFSYS_PROBE1(fail1, efx_rc_t, rc);
251 enp->en_erxop = NULL;
252 enp->en_mod_flags &= ~EFX_MOD_RX;
260 const efx_rx_ops_t *erxop = enp->en_erxop;
262 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
263 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
264 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
265 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
267 erxop->erxo_fini(enp);
269 enp->en_erxop = NULL;
270 enp->en_mod_flags &= ~EFX_MOD_RX;
273 #if EFSYS_OPT_RX_SCATTER
274 __checkReturn efx_rc_t
275 efx_rx_scatter_enable(
277 __in unsigned int buf_size)
279 const efx_rx_ops_t *erxop = enp->en_erxop;
282 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
283 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
285 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
291 EFSYS_PROBE1(fail1, efx_rc_t, rc);
294 #endif /* EFSYS_OPT_RX_SCATTER */
296 #if EFSYS_OPT_RX_SCALE
297 __checkReturn efx_rc_t
298 efx_rx_hash_default_support_get(
300 __out efx_rx_hash_support_t *supportp)
304 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
305 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
307 if (supportp == NULL) {
313 * Report the hashing support the client gets by default if it
314 * does not allocate an RSS context itself.
316 *supportp = enp->en_hash_support;
321 EFSYS_PROBE1(fail1, efx_rc_t, rc);
326 __checkReturn efx_rc_t
327 efx_rx_scale_default_support_get(
329 __out efx_rx_scale_context_type_t *typep)
333 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
334 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
342 * Report the RSS support the client gets by default if it
343 * does not allocate an RSS context itself.
345 *typep = enp->en_rss_context_type;
350 EFSYS_PROBE1(fail1, efx_rc_t, rc);
354 #endif /* EFSYS_OPT_RX_SCALE */
356 #if EFSYS_OPT_RX_SCALE
357 __checkReturn efx_rc_t
358 efx_rx_scale_context_alloc(
360 __in efx_rx_scale_context_type_t type,
361 __in uint32_t num_queues,
362 __out uint32_t *rss_contextp)
364 const efx_rx_ops_t *erxop = enp->en_erxop;
367 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
368 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
370 if (erxop->erxo_scale_context_alloc == NULL) {
374 if ((rc = erxop->erxo_scale_context_alloc(enp, type,
375 num_queues, rss_contextp)) != 0) {
384 EFSYS_PROBE1(fail1, efx_rc_t, rc);
387 #endif /* EFSYS_OPT_RX_SCALE */
389 #if EFSYS_OPT_RX_SCALE
390 __checkReturn efx_rc_t
391 efx_rx_scale_context_free(
393 __in uint32_t rss_context)
395 const efx_rx_ops_t *erxop = enp->en_erxop;
398 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
399 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
401 if (erxop->erxo_scale_context_free == NULL) {
405 if ((rc = erxop->erxo_scale_context_free(enp, rss_context)) != 0)
413 EFSYS_PROBE1(fail1, efx_rc_t, rc);
416 #endif /* EFSYS_OPT_RX_SCALE */
418 #if EFSYS_OPT_RX_SCALE
419 __checkReturn efx_rc_t
420 efx_rx_scale_mode_set(
422 __in uint32_t rss_context,
423 __in efx_rx_hash_alg_t alg,
424 __in efx_rx_hash_type_t type,
425 __in boolean_t insert)
427 const efx_rx_ops_t *erxop = enp->en_erxop;
430 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
431 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
433 if (erxop->erxo_scale_mode_set != NULL) {
434 if ((rc = erxop->erxo_scale_mode_set(enp, rss_context, alg,
442 EFSYS_PROBE1(fail1, efx_rc_t, rc);
445 #endif /* EFSYS_OPT_RX_SCALE */
447 #if EFSYS_OPT_RX_SCALE
448 __checkReturn efx_rc_t
449 efx_rx_scale_key_set(
451 __in uint32_t rss_context,
452 __in_ecount(n) uint8_t *key,
455 const efx_rx_ops_t *erxop = enp->en_erxop;
458 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
459 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
461 if ((rc = erxop->erxo_scale_key_set(enp, rss_context, key, n)) != 0)
467 EFSYS_PROBE1(fail1, efx_rc_t, rc);
471 #endif /* EFSYS_OPT_RX_SCALE */
473 #if EFSYS_OPT_RX_SCALE
474 __checkReturn efx_rc_t
475 efx_rx_scale_tbl_set(
477 __in uint32_t rss_context,
478 __in_ecount(n) unsigned int *table,
481 const efx_rx_ops_t *erxop = enp->en_erxop;
484 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
485 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
487 if ((rc = erxop->erxo_scale_tbl_set(enp, rss_context, table, n)) != 0)
493 EFSYS_PROBE1(fail1, efx_rc_t, rc);
497 #endif /* EFSYS_OPT_RX_SCALE */
502 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
504 __in unsigned int ndescs,
505 __in unsigned int completed,
506 __in unsigned int added)
508 efx_nic_t *enp = erp->er_enp;
509 const efx_rx_ops_t *erxop = enp->en_erxop;
511 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
513 erxop->erxo_qpost(erp, addrp, size, ndescs, completed, added);
516 #if EFSYS_OPT_RX_PACKED_STREAM
519 efx_rx_qpush_ps_credits(
522 efx_nic_t *enp = erp->er_enp;
523 const efx_rx_ops_t *erxop = enp->en_erxop;
525 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
527 erxop->erxo_qpush_ps_credits(erp);
530 __checkReturn uint8_t *
531 efx_rx_qps_packet_info(
533 __in uint8_t *buffer,
534 __in uint32_t buffer_length,
535 __in uint32_t current_offset,
536 __out uint16_t *lengthp,
537 __out uint32_t *next_offsetp,
538 __out uint32_t *timestamp)
540 efx_nic_t *enp = erp->er_enp;
541 const efx_rx_ops_t *erxop = enp->en_erxop;
543 return (erxop->erxo_qps_packet_info(erp, buffer,
544 buffer_length, current_offset, lengthp,
545 next_offsetp, timestamp));
548 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
553 __in unsigned int added,
554 __inout unsigned int *pushedp)
556 efx_nic_t *enp = erp->er_enp;
557 const efx_rx_ops_t *erxop = enp->en_erxop;
559 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
561 erxop->erxo_qpush(erp, added, pushedp);
564 __checkReturn efx_rc_t
568 efx_nic_t *enp = erp->er_enp;
569 const efx_rx_ops_t *erxop = enp->en_erxop;
572 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
574 if ((rc = erxop->erxo_qflush(erp)) != 0)
580 EFSYS_PROBE1(fail1, efx_rc_t, rc);
589 efx_nic_t *enp = erp->er_enp;
590 const efx_rx_ops_t *erxop = enp->en_erxop;
592 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
594 erxop->erxo_qenable(erp);
597 static __checkReturn efx_rc_t
598 efx_rx_qcreate_internal(
600 __in unsigned int index,
601 __in unsigned int label,
602 __in efx_rxq_type_t type,
603 __in uint32_t type_data,
604 __in efsys_mem_t *esmp,
607 __in unsigned int flags,
609 __deref_out efx_rxq_t **erpp)
611 const efx_rx_ops_t *erxop = enp->en_erxop;
615 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
616 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
618 /* Allocate an RXQ object */
619 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
626 erp->er_magic = EFX_RXQ_MAGIC;
628 erp->er_index = index;
629 erp->er_mask = ndescs - 1;
632 if ((rc = erxop->erxo_qcreate(enp, index, label, type, type_data, esmp,
633 ndescs, id, flags, eep, erp)) != 0)
644 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
646 EFSYS_PROBE1(fail1, efx_rc_t, rc);
651 __checkReturn efx_rc_t
654 __in unsigned int index,
655 __in unsigned int label,
656 __in efx_rxq_type_t type,
657 __in efsys_mem_t *esmp,
660 __in unsigned int flags,
662 __deref_out efx_rxq_t **erpp)
664 return efx_rx_qcreate_internal(enp, index, label, type, 0, esmp, ndescs,
665 id, flags, eep, erpp);
668 #if EFSYS_OPT_RX_PACKED_STREAM
670 __checkReturn efx_rc_t
671 efx_rx_qcreate_packed_stream(
673 __in unsigned int index,
674 __in unsigned int label,
675 __in uint32_t ps_buf_size,
676 __in efsys_mem_t *esmp,
679 __deref_out efx_rxq_t **erpp)
681 return efx_rx_qcreate_internal(enp, index, label,
682 EFX_RXQ_TYPE_PACKED_STREAM, ps_buf_size, esmp, ndescs,
683 0 /* id unused on EF10 */, EFX_RXQ_FLAG_NONE, eep, erpp);
692 efx_nic_t *enp = erp->er_enp;
693 const efx_rx_ops_t *erxop = enp->en_erxop;
695 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
697 erxop->erxo_qdestroy(erp);
700 __checkReturn efx_rc_t
701 efx_pseudo_hdr_pkt_length_get(
703 __in uint8_t *buffer,
704 __out uint16_t *lengthp)
706 efx_nic_t *enp = erp->er_enp;
707 const efx_rx_ops_t *erxop = enp->en_erxop;
709 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
711 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
714 #if EFSYS_OPT_RX_SCALE
715 __checkReturn uint32_t
716 efx_pseudo_hdr_hash_get(
718 __in efx_rx_hash_alg_t func,
719 __in uint8_t *buffer)
721 efx_nic_t *enp = erp->er_enp;
722 const efx_rx_ops_t *erxop = enp->en_erxop;
724 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
726 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
727 return (erxop->erxo_prefix_hash(enp, func, buffer));
729 #endif /* EFSYS_OPT_RX_SCALE */
733 static __checkReturn efx_rc_t
740 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
742 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
743 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
744 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
745 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
746 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
747 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
748 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
750 /* Zero the RSS table */
751 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
753 EFX_ZERO_OWORD(oword);
754 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
755 index, &oword, B_TRUE);
758 #if EFSYS_OPT_RX_SCALE
759 /* The RSS key and indirection table are writable. */
760 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
762 /* Hardware can insert RX hash with/without RSS */
763 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
764 #endif /* EFSYS_OPT_RX_SCALE */
769 #if EFSYS_OPT_RX_SCATTER
770 static __checkReturn efx_rc_t
771 siena_rx_scatter_enable(
773 __in unsigned int buf_size)
779 nbuf32 = buf_size / 32;
781 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
782 ((buf_size % 32) != 0)) {
787 if (enp->en_rx_qcount > 0) {
792 /* Set scatter buffer size */
793 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
794 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
795 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
797 /* Enable scatter for packets not matching a filter */
798 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
799 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
800 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
807 EFSYS_PROBE1(fail1, efx_rc_t, rc);
811 #endif /* EFSYS_OPT_RX_SCATTER */
814 #define EFX_RX_LFSR_HASH(_enp, _insert) \
818 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
819 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
820 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
821 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
822 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
823 (_insert) ? 1 : 0); \
824 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
826 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
827 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
829 EFX_SET_OWORD_FIELD(oword, \
830 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
831 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
835 _NOTE(CONSTANTCONDITION) \
838 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
842 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
843 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
844 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
846 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
848 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
849 (_insert) ? 1 : 0); \
850 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
852 _NOTE(CONSTANTCONDITION) \
855 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
859 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
860 EFX_SET_OWORD_FIELD(oword, \
861 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
862 EFX_SET_OWORD_FIELD(oword, \
863 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
864 EFX_SET_OWORD_FIELD(oword, \
865 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
866 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
870 _NOTE(CONSTANTCONDITION) \
874 #if EFSYS_OPT_RX_SCALE
876 static __checkReturn efx_rc_t
877 siena_rx_scale_mode_set(
879 __in uint32_t rss_context,
880 __in efx_rx_hash_alg_t alg,
881 __in efx_rx_hash_type_t type,
882 __in boolean_t insert)
886 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
892 case EFX_RX_HASHALG_LFSR:
893 EFX_RX_LFSR_HASH(enp, insert);
896 case EFX_RX_HASHALG_TOEPLITZ:
897 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
898 type & EFX_RX_HASH_IPV4,
899 type & EFX_RX_HASH_TCPIPV4);
901 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
902 type & EFX_RX_HASH_IPV6,
903 type & EFX_RX_HASH_TCPIPV6,
922 EFSYS_PROBE1(fail1, efx_rc_t, rc);
924 EFX_RX_LFSR_HASH(enp, B_FALSE);
930 #if EFSYS_OPT_RX_SCALE
931 static __checkReturn efx_rc_t
932 siena_rx_scale_key_set(
934 __in uint32_t rss_context,
935 __in_ecount(n) uint8_t *key,
943 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
950 /* Write Toeplitz IPv4 hash key */
951 EFX_ZERO_OWORD(oword);
952 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
953 offset > 0 && byte < n;
955 oword.eo_u8[offset - 1] = key[byte++];
957 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
961 /* Verify Toeplitz IPv4 hash key */
962 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
963 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
964 offset > 0 && byte < n;
966 if (oword.eo_u8[offset - 1] != key[byte++]) {
972 if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
977 /* Write Toeplitz IPv6 hash key 3 */
978 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
979 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
980 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
981 offset > 0 && byte < n;
983 oword.eo_u8[offset - 1] = key[byte++];
985 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
987 /* Write Toeplitz IPv6 hash key 2 */
988 EFX_ZERO_OWORD(oword);
989 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
990 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
991 offset > 0 && byte < n;
993 oword.eo_u8[offset - 1] = key[byte++];
995 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
997 /* Write Toeplitz IPv6 hash key 1 */
998 EFX_ZERO_OWORD(oword);
999 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1000 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1001 offset > 0 && byte < n;
1003 oword.eo_u8[offset - 1] = key[byte++];
1005 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1009 /* Verify Toeplitz IPv6 hash key 3 */
1010 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1011 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1012 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1013 offset > 0 && byte < n;
1015 if (oword.eo_u8[offset - 1] != key[byte++]) {
1021 /* Verify Toeplitz IPv6 hash key 2 */
1022 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1023 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1024 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1025 offset > 0 && byte < n;
1027 if (oword.eo_u8[offset - 1] != key[byte++]) {
1033 /* Verify Toeplitz IPv6 hash key 1 */
1034 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1035 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1036 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1037 offset > 0 && byte < n;
1039 if (oword.eo_u8[offset - 1] != key[byte++]) {
1057 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1063 #if EFSYS_OPT_RX_SCALE
1064 static __checkReturn efx_rc_t
1065 siena_rx_scale_tbl_set(
1066 __in efx_nic_t *enp,
1067 __in uint32_t rss_context,
1068 __in_ecount(n) unsigned int *table,
1075 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
1076 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
1078 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1083 if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
1088 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
1091 /* Calculate the entry to place in the table */
1092 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1094 EFSYS_PROBE2(table, int, index, uint32_t, byte);
1096 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
1098 /* Write the table */
1099 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1100 index, &oword, B_TRUE);
1103 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
1106 /* Determine if we're starting a new batch */
1107 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1109 /* Read the table */
1110 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
1111 index, &oword, B_TRUE);
1113 /* Verify the entry */
1114 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1127 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1134 * Falcon/Siena pseudo-header
1135 * --------------------------
1137 * Receive packets are prefixed by an optional 16 byte pseudo-header.
1138 * The pseudo-header is a byte array of one of the forms:
1140 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1141 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1142 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1145 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
1146 * LL.LL LFSR hash (16-bit big-endian)
1149 #if EFSYS_OPT_RX_SCALE
1150 static __checkReturn uint32_t
1151 siena_rx_prefix_hash(
1152 __in efx_nic_t *enp,
1153 __in efx_rx_hash_alg_t func,
1154 __in uint8_t *buffer)
1156 _NOTE(ARGUNUSED(enp))
1159 case EFX_RX_HASHALG_TOEPLITZ:
1160 return ((buffer[12] << 24) |
1161 (buffer[13] << 16) |
1165 case EFX_RX_HASHALG_LFSR:
1166 return ((buffer[14] << 8) | buffer[15]);
1173 #endif /* EFSYS_OPT_RX_SCALE */
1175 static __checkReturn efx_rc_t
1176 siena_rx_prefix_pktlen(
1177 __in efx_nic_t *enp,
1178 __in uint8_t *buffer,
1179 __out uint16_t *lengthp)
1181 _NOTE(ARGUNUSED(enp, buffer, lengthp))
1183 /* Not supported by Falcon/Siena hardware */
1191 __in efx_rxq_t *erp,
1192 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1194 __in unsigned int ndescs,
1195 __in unsigned int completed,
1196 __in unsigned int added)
1200 unsigned int offset;
1203 /* The client driver must not overfill the queue */
1204 EFSYS_ASSERT3U(added - completed + ndescs, <=,
1205 EFX_RXQ_LIMIT(erp->er_mask + 1));
1207 id = added & (erp->er_mask);
1208 for (i = 0; i < ndescs; i++) {
1209 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1210 unsigned int, id, efsys_dma_addr_t, addrp[i],
1213 EFX_POPULATE_QWORD_3(qword,
1214 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1215 FSF_AZ_RX_KER_BUF_ADDR_DW0,
1216 (uint32_t)(addrp[i] & 0xffffffff),
1217 FSF_AZ_RX_KER_BUF_ADDR_DW1,
1218 (uint32_t)(addrp[i] >> 32));
1220 offset = id * sizeof (efx_qword_t);
1221 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1223 id = (id + 1) & (erp->er_mask);
1229 __in efx_rxq_t *erp,
1230 __in unsigned int added,
1231 __inout unsigned int *pushedp)
1233 efx_nic_t *enp = erp->er_enp;
1234 unsigned int pushed = *pushedp;
1239 /* All descriptors are pushed */
1242 /* Push the populated descriptors out */
1243 wptr = added & erp->er_mask;
1245 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1247 /* Only write the third DWORD */
1248 EFX_POPULATE_DWORD_1(dword,
1249 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1251 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1252 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1253 wptr, pushed & erp->er_mask);
1254 EFSYS_PIO_WRITE_BARRIER();
1255 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1256 erp->er_index, &dword, B_FALSE);
1259 #if EFSYS_OPT_RX_PACKED_STREAM
1261 siena_rx_qpush_ps_credits(
1262 __in efx_rxq_t *erp)
1264 /* Not supported by Siena hardware */
1269 siena_rx_qps_packet_info(
1270 __in efx_rxq_t *erp,
1271 __in uint8_t *buffer,
1272 __in uint32_t buffer_length,
1273 __in uint32_t current_offset,
1274 __out uint16_t *lengthp,
1275 __out uint32_t *next_offsetp,
1276 __out uint32_t *timestamp)
1278 /* Not supported by Siena hardware */
1283 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1285 static __checkReturn efx_rc_t
1287 __in efx_rxq_t *erp)
1289 efx_nic_t *enp = erp->er_enp;
1293 label = erp->er_index;
1295 /* Flush the queue */
1296 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1297 FRF_AZ_RX_FLUSH_DESCQ, label);
1298 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1305 __in efx_rxq_t *erp)
1307 efx_nic_t *enp = erp->er_enp;
1310 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1312 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1313 erp->er_index, &oword, B_TRUE);
1315 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1316 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1317 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1319 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1320 erp->er_index, &oword, B_TRUE);
1323 static __checkReturn efx_rc_t
1325 __in efx_nic_t *enp,
1326 __in unsigned int index,
1327 __in unsigned int label,
1328 __in efx_rxq_type_t type,
1329 __in uint32_t type_data,
1330 __in efsys_mem_t *esmp,
1333 __in unsigned int flags,
1334 __in efx_evq_t *eep,
1335 __in efx_rxq_t *erp)
1337 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1340 boolean_t jumbo = B_FALSE;
1343 _NOTE(ARGUNUSED(esmp))
1344 _NOTE(ARGUNUSED(type_data))
1346 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1347 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1348 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1349 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1351 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1352 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1354 if (!ISP2(ndescs) ||
1355 (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
1359 if (index >= encp->enc_rxq_limit) {
1363 for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1365 if ((1 << size) == (int)(ndescs / EFX_RXQ_MINNDESCS))
1367 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1373 case EFX_RXQ_TYPE_DEFAULT:
1381 if (flags & EFX_RXQ_FLAG_SCATTER) {
1382 #if EFSYS_OPT_RX_SCATTER
1387 #endif /* EFSYS_OPT_RX_SCATTER */
1390 /* Set up the new descriptor queue */
1391 EFX_POPULATE_OWORD_7(oword,
1392 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1393 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1394 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1395 FRF_AZ_RX_DESCQ_LABEL, label,
1396 FRF_AZ_RX_DESCQ_SIZE, size,
1397 FRF_AZ_RX_DESCQ_TYPE, 0,
1398 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1400 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1401 erp->er_index, &oword, B_TRUE);
1405 #if !EFSYS_OPT_RX_SCATTER
1416 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1423 __in efx_rxq_t *erp)
1425 efx_nic_t *enp = erp->er_enp;
1428 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1429 --enp->en_rx_qcount;
1431 /* Purge descriptor queue */
1432 EFX_ZERO_OWORD(oword);
1434 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1435 erp->er_index, &oword, B_TRUE);
1437 /* Free the RXQ object */
1438 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1443 __in efx_nic_t *enp)
1445 _NOTE(ARGUNUSED(enp))
1448 #endif /* EFSYS_OPT_SIENA */