drivers/net/sfc/base/efx_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11 #if EFSYS_OPT_SIENA
  12
  13 static  __checkReturn   efx_rc_t
  14 siena_rx_init(
  15         __in            efx_nic_t *enp);
  16
  17 static                  void
  18 siena_rx_fini(
  19         __in            efx_nic_t *enp);
  20
  21 #if EFSYS_OPT_RX_SCATTER
  22 static  __checkReturn   efx_rc_t
  23 siena_rx_scatter_enable(
  24         __in            efx_nic_t *enp,
  25         __in            unsigned int buf_size);
  26 #endif /* EFSYS_OPT_RX_SCATTER */
  27
  28 #if EFSYS_OPT_RX_SCALE
  29 static  __checkReturn   efx_rc_t
  30 siena_rx_scale_mode_set(
  31         __in            efx_nic_t *enp,
  32         __in            uint32_t rss_context,
  33         __in            efx_rx_hash_alg_t alg,
  34         __in            efx_rx_hash_type_t type,
  35         __in            boolean_t insert);
  36
  37 static  __checkReturn   efx_rc_t
  38 siena_rx_scale_key_set(
  39         __in            efx_nic_t *enp,
  40         __in            uint32_t rss_context,
  41         __in_ecount(n)  uint8_t *key,
  42         __in            size_t n);
  43
  44 static  __checkReturn   efx_rc_t
  45 siena_rx_scale_tbl_set(
  46         __in            efx_nic_t *enp,
  47         __in            uint32_t rss_context,
  48         __in_ecount(n)  unsigned int *table,
  49         __in            size_t n);
  50
  51 static  __checkReturn   uint32_t
  52 siena_rx_prefix_hash(
  53         __in            efx_nic_t *enp,
  54         __in            efx_rx_hash_alg_t func,
  55         __in            uint8_t *buffer);
  56
  57 #endif /* EFSYS_OPT_RX_SCALE */
  58
  59 static  __checkReturn   efx_rc_t
  60 siena_rx_prefix_pktlen(
  61         __in            efx_nic_t *enp,
  62         __in            uint8_t *buffer,
  63         __out           uint16_t *lengthp);
  64
  65 static                          void
  66 siena_rx_qpost(
  67         __in                    efx_rxq_t *erp,
  68         __in_ecount(ndescs)     efsys_dma_addr_t *addrp,
  69         __in                    size_t size,
  70         __in                    unsigned int ndescs,
  71         __in                    unsigned int completed,
  72         __in                    unsigned int added);
  73
  74 static                  void
  75 siena_rx_qpush(
  76         __in            efx_rxq_t *erp,
  77         __in            unsigned int added,
  78         __inout         unsigned int *pushedp);
  79
  80 #if EFSYS_OPT_RX_PACKED_STREAM
  81 static          void
  82 siena_rx_qpush_ps_credits(
  83         __in            efx_rxq_t *erp);
  84
  85 static  __checkReturn   uint8_t *
  86 siena_rx_qps_packet_info(
  87         __in            efx_rxq_t *erp,
  88         __in            uint8_t *buffer,
  89         __in            uint32_t buffer_length,
  90         __in            uint32_t current_offset,
  91         __out           uint16_t *lengthp,
  92         __out           uint32_t *next_offsetp,
  93         __out           uint32_t *timestamp);
  94 #endif
  95
  96 static  __checkReturn   efx_rc_t
  97 siena_rx_qflush(
  98         __in            efx_rxq_t *erp);
  99
 100 static                  void
 101 siena_rx_qenable(
 102         __in            efx_rxq_t *erp);
 103
 104 static  __checkReturn   efx_rc_t
 105 siena_rx_qcreate(
 106         __in            efx_nic_t *enp,
 107         __in            unsigned int index,
 108         __in            unsigned int label,
 109         __in            efx_rxq_type_t type,
 110         __in            uint32_t type_data,
 111         __in            efsys_mem_t *esmp,
 112         __in            size_t ndescs,
 113         __in            uint32_t id,
 114         __in            unsigned int flags,
 115         __in            efx_evq_t *eep,
 116         __in            efx_rxq_t *erp);
 117
 118 static                  void
 119 siena_rx_qdestroy(
 120         __in            efx_rxq_t *erp);
 121
 122 #endif /* EFSYS_OPT_SIENA */
 123
 124
 125 #if EFSYS_OPT_SIENA
 126 static const efx_rx_ops_t __efx_rx_siena_ops = {
 127         siena_rx_init,                          /* erxo_init */
 128         siena_rx_fini,                          /* erxo_fini */
 129 #if EFSYS_OPT_RX_SCATTER
 130         siena_rx_scatter_enable,                /* erxo_scatter_enable */
 131 #endif
 132 #if EFSYS_OPT_RX_SCALE
 133         NULL,                                   /* erxo_scale_context_alloc */
 134         NULL,                                   /* erxo_scale_context_free */
 135         siena_rx_scale_mode_set,                /* erxo_scale_mode_set */
 136         siena_rx_scale_key_set,                 /* erxo_scale_key_set */
 137         siena_rx_scale_tbl_set,                 /* erxo_scale_tbl_set */
 138         siena_rx_prefix_hash,                   /* erxo_prefix_hash */
 139 #endif
 140         siena_rx_prefix_pktlen,                 /* erxo_prefix_pktlen */
 141         siena_rx_qpost,                         /* erxo_qpost */
 142         siena_rx_qpush,                         /* erxo_qpush */
 143 #if EFSYS_OPT_RX_PACKED_STREAM
 144         siena_rx_qpush_ps_credits,              /* erxo_qpush_ps_credits */
 145         siena_rx_qps_packet_info,               /* erxo_qps_packet_info */
 146 #endif
 147         siena_rx_qflush,                        /* erxo_qflush */
 148         siena_rx_qenable,                       /* erxo_qenable */
 149         siena_rx_qcreate,                       /* erxo_qcreate */
 150         siena_rx_qdestroy,                      /* erxo_qdestroy */
 151 };
 152 #endif  /* EFSYS_OPT_SIENA */
 153
 154 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
 155 static const efx_rx_ops_t __efx_rx_ef10_ops = {
 156         ef10_rx_init,                           /* erxo_init */
 157         ef10_rx_fini,                           /* erxo_fini */
 158 #if EFSYS_OPT_RX_SCATTER
 159         ef10_rx_scatter_enable,                 /* erxo_scatter_enable */
 160 #endif
 161 #if EFSYS_OPT_RX_SCALE
 162         ef10_rx_scale_context_alloc,            /* erxo_scale_context_alloc */
 163         ef10_rx_scale_context_free,             /* erxo_scale_context_free */
 164         ef10_rx_scale_mode_set,                 /* erxo_scale_mode_set */
 165         ef10_rx_scale_key_set,                  /* erxo_scale_key_set */
 166         ef10_rx_scale_tbl_set,                  /* erxo_scale_tbl_set */
 167         ef10_rx_prefix_hash,                    /* erxo_prefix_hash */
 168 #endif
 169         ef10_rx_prefix_pktlen,                  /* erxo_prefix_pktlen */
 170         ef10_rx_qpost,                          /* erxo_qpost */
 171         ef10_rx_qpush,                          /* erxo_qpush */
 172 #if EFSYS_OPT_RX_PACKED_STREAM
 173         ef10_rx_qpush_ps_credits,               /* erxo_qpush_ps_credits */
 174         ef10_rx_qps_packet_info,                /* erxo_qps_packet_info */
 175 #endif
 176         ef10_rx_qflush,                         /* erxo_qflush */
 177         ef10_rx_qenable,                        /* erxo_qenable */
 178         ef10_rx_qcreate,                        /* erxo_qcreate */
 179         ef10_rx_qdestroy,                       /* erxo_qdestroy */
 180 };
 181 #endif  /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
 182
 183
 184         __checkReturn   efx_rc_t
 185 efx_rx_init(
 186         __inout         efx_nic_t *enp)
 187 {
 188         const efx_rx_ops_t *erxop;
 189         efx_rc_t rc;
 190
 191         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 192         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 193
 194         if (!(enp->en_mod_flags & EFX_MOD_EV)) {
 195                 rc = EINVAL;
 196                 goto fail1;
 197         }
 198
 199         if (enp->en_mod_flags & EFX_MOD_RX) {
 200                 rc = EINVAL;
 201                 goto fail2;
 202         }
 203
 204         switch (enp->en_family) {
 205 #if EFSYS_OPT_SIENA
 206         case EFX_FAMILY_SIENA:
 207                 erxop = &__efx_rx_siena_ops;
 208                 break;
 209 #endif /* EFSYS_OPT_SIENA */
 210
 211 #if EFSYS_OPT_HUNTINGTON
 212         case EFX_FAMILY_HUNTINGTON:
 213                 erxop = &__efx_rx_ef10_ops;
 214                 break;
 215 #endif /* EFSYS_OPT_HUNTINGTON */
 216
 217 #if EFSYS_OPT_MEDFORD
 218         case EFX_FAMILY_MEDFORD:
 219                 erxop = &__efx_rx_ef10_ops;
 220                 break;
 221 #endif /* EFSYS_OPT_MEDFORD */
 222
 223 #if EFSYS_OPT_MEDFORD2
 224         case EFX_FAMILY_MEDFORD2:
 225                 erxop = &__efx_rx_ef10_ops;
 226                 break;
 227 #endif /* EFSYS_OPT_MEDFORD2 */
 228
 229         default:
 230                 EFSYS_ASSERT(0);
 231                 rc = ENOTSUP;
 232                 goto fail3;
 233         }
 234
 235         if ((rc = erxop->erxo_init(enp)) != 0)
 236                 goto fail4;
 237
 238         enp->en_erxop = erxop;
 239         enp->en_mod_flags |= EFX_MOD_RX;
 240         return (0);
 241
 242 fail4:
 243         EFSYS_PROBE(fail4);
 244 fail3:
 245         EFSYS_PROBE(fail3);
 246 fail2:
 247         EFSYS_PROBE(fail2);
 248 fail1:
 249         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 250
 251         enp->en_erxop = NULL;
 252         enp->en_mod_flags &= ~EFX_MOD_RX;
 253         return (rc);
 254 }
 255
 256                         void
 257 efx_rx_fini(
 258         __in            efx_nic_t *enp)
 259 {
 260         const efx_rx_ops_t *erxop = enp->en_erxop;
 261
 262         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 263         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 264         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 265         EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
 266
 267         erxop->erxo_fini(enp);
 268
 269         enp->en_erxop = NULL;
 270         enp->en_mod_flags &= ~EFX_MOD_RX;
 271 }
 272
 273 #if EFSYS_OPT_RX_SCATTER
 274         __checkReturn   efx_rc_t
 275 efx_rx_scatter_enable(
 276         __in            efx_nic_t *enp,
 277         __in            unsigned int buf_size)
 278 {
 279         const efx_rx_ops_t *erxop = enp->en_erxop;
 280         efx_rc_t rc;
 281
 282         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 283         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 284
 285         if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
 286                 goto fail1;
 287
 288         return (0);
 289
 290 fail1:
 291         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 292         return (rc);
 293 }
 294 #endif  /* EFSYS_OPT_RX_SCATTER */
 295
 296 #if EFSYS_OPT_RX_SCALE
 297         __checkReturn                           efx_rc_t
 298 efx_rx_scale_hash_flags_get(
 299         __in                                    efx_nic_t *enp,
 300         __in                                    efx_rx_hash_alg_t hash_alg,
 301         __inout_ecount(EFX_RX_HASH_NFLAGS)      unsigned int *flags,
 302         __out                                   unsigned int *nflagsp)
 303 {
 304         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 305         boolean_t additional_modes;
 306         unsigned int *entryp = flags;
 307         efx_rc_t rc;
 308
 309         if (flags == NULL || nflagsp == NULL) {
 310                 rc = EINVAL;
 311                 goto fail1;
 312         }
 313
 314         additional_modes = encp->enc_rx_scale_additional_modes_supported;
 315
 316 #define LIST_FLAGS(_entryp, _class, _l4_hashing, _additional_modes)     \
 317         do {                                                            \
 318                 if (_l4_hashing) {                                      \
 319                         *(_entryp++) = EFX_RX_HASH(_class, 4TUPLE);     \
 320                                                                         \
 321                         if (_additional_modes) {                        \
 322                                 *(_entryp++) =                          \
 323                                     EFX_RX_HASH(_class, 2TUPLE_DST);    \
 324                                 *(_entryp++) =                          \
 325                                     EFX_RX_HASH(_class, 2TUPLE_SRC);    \
 326                         }                                               \
 327                 }                                                       \
 328                                                                         \
 329                 *(_entryp++) = EFX_RX_HASH(_class, 2TUPLE);             \
 330                                                                         \
 331                 if (_additional_modes) {                                \
 332                         *(_entryp++) = EFX_RX_HASH(_class, 1TUPLE_DST); \
 333                         *(_entryp++) = EFX_RX_HASH(_class, 1TUPLE_SRC); \
 334                 }                                                       \
 335                                                                         \
 336                 *(_entryp++) = EFX_RX_HASH(_class, DISABLE);            \
 337                                                                         \
 338                 _NOTE(CONSTANTCONDITION)                                \
 339         } while (B_FALSE)
 340
 341         switch (hash_alg) {
 342         case EFX_RX_HASHALG_TOEPLITZ:
 343                 LIST_FLAGS(entryp, IPV4_TCP, B_TRUE, additional_modes);
 344                 LIST_FLAGS(entryp, IPV6_TCP, B_TRUE, additional_modes);
 345
 346                 if (additional_modes) {
 347                         LIST_FLAGS(entryp, IPV4_UDP, B_TRUE, additional_modes);
 348                         LIST_FLAGS(entryp, IPV6_UDP, B_TRUE, additional_modes);
 349                 }
 350
 351                 LIST_FLAGS(entryp, IPV4, B_FALSE, additional_modes);
 352                 LIST_FLAGS(entryp, IPV6, B_FALSE, additional_modes);
 353                 break;
 354
 355         default:
 356                 rc = EINVAL;
 357                 goto fail2;
 358         }
 359
 360 #undef LIST_FLAGS
 361
 362         *nflagsp = (unsigned int)(entryp - flags);
 363         EFSYS_ASSERT3U(*nflagsp, <=, EFX_RX_HASH_NFLAGS);
 364
 365         return (0);
 366
 367 fail2:
 368         EFSYS_PROBE(fail2);
 369
 370 fail1:
 371         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 372
 373         return (rc);
 374 }
 375
 376         __checkReturn   efx_rc_t
 377 efx_rx_hash_default_support_get(
 378         __in            efx_nic_t *enp,
 379         __out           efx_rx_hash_support_t *supportp)
 380 {
 381         efx_rc_t rc;
 382
 383         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 384         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 385
 386         if (supportp == NULL) {
 387                 rc = EINVAL;
 388                 goto fail1;
 389         }
 390
 391         /*
 392          * Report the hashing support the client gets by default if it
 393          * does not allocate an RSS context itself.
 394          */
 395         *supportp = enp->en_hash_support;
 396
 397         return (0);
 398
 399 fail1:
 400         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 401
 402         return (rc);
 403 }
 404
 405         __checkReturn   efx_rc_t
 406 efx_rx_scale_default_support_get(
 407         __in            efx_nic_t *enp,
 408         __out           efx_rx_scale_context_type_t *typep)
 409 {
 410         efx_rc_t rc;
 411
 412         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 413         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 414
 415         if (typep == NULL) {
 416                 rc = EINVAL;
 417                 goto fail1;
 418         }
 419
 420         /*
 421          * Report the RSS support the client gets by default if it
 422          * does not allocate an RSS context itself.
 423          */
 424         *typep = enp->en_rss_context_type;
 425
 426         return (0);
 427
 428 fail1:
 429         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 430
 431         return (rc);
 432 }
 433 #endif  /* EFSYS_OPT_RX_SCALE */
 434
 435 #if EFSYS_OPT_RX_SCALE
 436         __checkReturn   efx_rc_t
 437 efx_rx_scale_context_alloc(
 438         __in            efx_nic_t *enp,
 439         __in            efx_rx_scale_context_type_t type,
 440         __in            uint32_t num_queues,
 441         __out           uint32_t *rss_contextp)
 442 {
 443         const efx_rx_ops_t *erxop = enp->en_erxop;
 444         efx_rc_t rc;
 445
 446         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 447         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 448
 449         if (erxop->erxo_scale_context_alloc == NULL) {
 450                 rc = ENOTSUP;
 451                 goto fail1;
 452         }
 453         if ((rc = erxop->erxo_scale_context_alloc(enp, type,
 454                             num_queues, rss_contextp)) != 0) {
 455                 goto fail2;
 456         }
 457
 458         return (0);
 459
 460 fail2:
 461         EFSYS_PROBE(fail2);
 462 fail1:
 463         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 464         return (rc);
 465 }
 466 #endif  /* EFSYS_OPT_RX_SCALE */
 467
 468 #if EFSYS_OPT_RX_SCALE
 469         __checkReturn   efx_rc_t
 470 efx_rx_scale_context_free(
 471         __in            efx_nic_t *enp,
 472         __in            uint32_t rss_context)
 473 {
 474         const efx_rx_ops_t *erxop = enp->en_erxop;
 475         efx_rc_t rc;
 476
 477         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 478         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 479
 480         if (erxop->erxo_scale_context_free == NULL) {
 481                 rc = ENOTSUP;
 482                 goto fail1;
 483         }
 484         if ((rc = erxop->erxo_scale_context_free(enp, rss_context)) != 0)
 485                 goto fail2;
 486
 487         return (0);
 488
 489 fail2:
 490         EFSYS_PROBE(fail2);
 491 fail1:
 492         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 493         return (rc);
 494 }
 495 #endif  /* EFSYS_OPT_RX_SCALE */
 496
 497 #if EFSYS_OPT_RX_SCALE
 498         __checkReturn   efx_rc_t
 499 efx_rx_scale_mode_set(
 500         __in            efx_nic_t *enp,
 501         __in            uint32_t rss_context,
 502         __in            efx_rx_hash_alg_t alg,
 503         __in            efx_rx_hash_type_t type,
 504         __in            boolean_t insert)
 505 {
 506         const efx_rx_ops_t *erxop = enp->en_erxop;
 507         unsigned int type_flags[EFX_RX_HASH_NFLAGS];
 508         unsigned int type_nflags;
 509         efx_rx_hash_type_t type_check;
 510         unsigned int i;
 511         efx_rc_t rc;
 512
 513         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 514         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 515
 516         /*
 517          * Legacy flags and modern bits cannot be
 518          * used at the same time in the hash type.
 519          */
 520         if ((type & EFX_RX_HASH_LEGACY_MASK) &&
 521             (type & ~EFX_RX_HASH_LEGACY_MASK)) {
 522                 rc = EINVAL;
 523                 goto fail1;
 524         }
 525
 526         /*
 527          * Translate legacy flags to the new representation
 528          * so that chip-specific handlers will consider the
 529          * new flags only.
 530          */
 531         if (type & EFX_RX_HASH_IPV4) {
 532                 type |= EFX_RX_HASH(IPV4, 2TUPLE);
 533                 type |= EFX_RX_HASH(IPV4_TCP, 2TUPLE);
 534                 type |= EFX_RX_HASH(IPV4_UDP, 2TUPLE);
 535         }
 536
 537         if (type & EFX_RX_HASH_TCPIPV4)
 538                 type |= EFX_RX_HASH(IPV4_TCP, 4TUPLE);
 539
 540         if (type & EFX_RX_HASH_IPV6) {
 541                 type |= EFX_RX_HASH(IPV6, 2TUPLE);
 542                 type |= EFX_RX_HASH(IPV6_TCP, 2TUPLE);
 543                 type |= EFX_RX_HASH(IPV6_UDP, 2TUPLE);
 544         }
 545
 546         if (type & EFX_RX_HASH_TCPIPV6)
 547                 type |= EFX_RX_HASH(IPV6_TCP, 4TUPLE);
 548
 549         type &= ~EFX_RX_HASH_LEGACY_MASK;
 550         type_check = type;
 551
 552         /*
 553          * Get the list of supported hash flags and sanitise the input.
 554          */
 555         rc = efx_rx_scale_hash_flags_get(enp, alg, type_flags, &type_nflags);
 556         if (rc != 0)
 557                 goto fail2;
 558
 559         for (i = 0; i < type_nflags; ++i) {
 560                 if ((type_check & type_flags[i]) == type_flags[i])
 561                         type_check &= ~(type_flags[i]);
 562         }
 563
 564         if (type_check != 0) {
 565                 rc = EINVAL;
 566                 goto fail3;
 567         }
 568
 569         if (erxop->erxo_scale_mode_set != NULL) {
 570                 if ((rc = erxop->erxo_scale_mode_set(enp, rss_context, alg,
 571                             type, insert)) != 0)
 572                         goto fail4;
 573         }
 574
 575         return (0);
 576
 577 fail4:
 578         EFSYS_PROBE(fail4);
 579 fail3:
 580         EFSYS_PROBE(fail3);
 581 fail2:
 582         EFSYS_PROBE(fail2);
 583 fail1:
 584         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 585         return (rc);
 586 }
 587 #endif  /* EFSYS_OPT_RX_SCALE */
 588
 589 #if EFSYS_OPT_RX_SCALE
 590         __checkReturn   efx_rc_t
 591 efx_rx_scale_key_set(
 592         __in            efx_nic_t *enp,
 593         __in            uint32_t rss_context,
 594         __in_ecount(n)  uint8_t *key,
 595         __in            size_t n)
 596 {
 597         const efx_rx_ops_t *erxop = enp->en_erxop;
 598         efx_rc_t rc;
 599
 600         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 601         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 602
 603         if ((rc = erxop->erxo_scale_key_set(enp, rss_context, key, n)) != 0)
 604                 goto fail1;
 605
 606         return (0);
 607
 608 fail1:
 609         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 610
 611         return (rc);
 612 }
 613 #endif  /* EFSYS_OPT_RX_SCALE */
 614
 615 #if EFSYS_OPT_RX_SCALE
 616         __checkReturn   efx_rc_t
 617 efx_rx_scale_tbl_set(
 618         __in            efx_nic_t *enp,
 619         __in            uint32_t rss_context,
 620         __in_ecount(n)  unsigned int *table,
 621         __in            size_t n)
 622 {
 623         const efx_rx_ops_t *erxop = enp->en_erxop;
 624         efx_rc_t rc;
 625
 626         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 627         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 628
 629         if ((rc = erxop->erxo_scale_tbl_set(enp, rss_context, table, n)) != 0)
 630                 goto fail1;
 631
 632         return (0);
 633
 634 fail1:
 635         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 636
 637         return (rc);
 638 }
 639 #endif  /* EFSYS_OPT_RX_SCALE */
 640
 641                                 void
 642 efx_rx_qpost(
 643         __in                    efx_rxq_t *erp,
 644         __in_ecount(ndescs)     efsys_dma_addr_t *addrp,
 645         __in                    size_t size,
 646         __in                    unsigned int ndescs,
 647         __in                    unsigned int completed,
 648         __in                    unsigned int added)
 649 {
 650         efx_nic_t *enp = erp->er_enp;
 651         const efx_rx_ops_t *erxop = enp->en_erxop;
 652
 653         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 654
 655         erxop->erxo_qpost(erp, addrp, size, ndescs, completed, added);
 656 }
 657
 658 #if EFSYS_OPT_RX_PACKED_STREAM
 659
 660                         void
 661 efx_rx_qpush_ps_credits(
 662         __in            efx_rxq_t *erp)
 663 {
 664         efx_nic_t *enp = erp->er_enp;
 665         const efx_rx_ops_t *erxop = enp->en_erxop;
 666
 667         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 668
 669         erxop->erxo_qpush_ps_credits(erp);
 670 }
 671
 672         __checkReturn   uint8_t *
 673 efx_rx_qps_packet_info(
 674         __in            efx_rxq_t *erp,
 675         __in            uint8_t *buffer,
 676         __in            uint32_t buffer_length,
 677         __in            uint32_t current_offset,
 678         __out           uint16_t *lengthp,
 679         __out           uint32_t *next_offsetp,
 680         __out           uint32_t *timestamp)
 681 {
 682         efx_nic_t *enp = erp->er_enp;
 683         const efx_rx_ops_t *erxop = enp->en_erxop;
 684
 685         return (erxop->erxo_qps_packet_info(erp, buffer,
 686                 buffer_length, current_offset, lengthp,
 687                 next_offsetp, timestamp));
 688 }
 689
 690 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
 691
 692                         void
 693 efx_rx_qpush(
 694         __in            efx_rxq_t *erp,
 695         __in            unsigned int added,
 696         __inout         unsigned int *pushedp)
 697 {
 698         efx_nic_t *enp = erp->er_enp;
 699         const efx_rx_ops_t *erxop = enp->en_erxop;
 700
 701         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 702
 703         erxop->erxo_qpush(erp, added, pushedp);
 704 }
 705
 706         __checkReturn   efx_rc_t
 707 efx_rx_qflush(
 708         __in            efx_rxq_t *erp)
 709 {
 710         efx_nic_t *enp = erp->er_enp;
 711         const efx_rx_ops_t *erxop = enp->en_erxop;
 712         efx_rc_t rc;
 713
 714         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 715
 716         if ((rc = erxop->erxo_qflush(erp)) != 0)
 717                 goto fail1;
 718
 719         return (0);
 720
 721 fail1:
 722         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 723
 724         return (rc);
 725 }
 726
 727                         void
 728 efx_rx_qenable(
 729         __in            efx_rxq_t *erp)
 730 {
 731         efx_nic_t *enp = erp->er_enp;
 732         const efx_rx_ops_t *erxop = enp->en_erxop;
 733
 734         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 735
 736         erxop->erxo_qenable(erp);
 737 }
 738
 739 static  __checkReturn   efx_rc_t
 740 efx_rx_qcreate_internal(
 741         __in            efx_nic_t *enp,
 742         __in            unsigned int index,
 743         __in            unsigned int label,
 744         __in            efx_rxq_type_t type,
 745         __in            uint32_t type_data,
 746         __in            efsys_mem_t *esmp,
 747         __in            size_t ndescs,
 748         __in            uint32_t id,
 749         __in            unsigned int flags,
 750         __in            efx_evq_t *eep,
 751         __deref_out     efx_rxq_t **erpp)
 752 {
 753         const efx_rx_ops_t *erxop = enp->en_erxop;
 754         efx_rxq_t *erp;
 755         efx_rc_t rc;
 756
 757         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 758         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 759
 760         /* Allocate an RXQ object */
 761         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
 762
 763         if (erp == NULL) {
 764                 rc = ENOMEM;
 765                 goto fail1;
 766         }
 767
 768         erp->er_magic = EFX_RXQ_MAGIC;
 769         erp->er_enp = enp;
 770         erp->er_index = index;
 771         erp->er_mask = ndescs - 1;
 772         erp->er_esmp = esmp;
 773
 774         if ((rc = erxop->erxo_qcreate(enp, index, label, type, type_data, esmp,
 775             ndescs, id, flags, eep, erp)) != 0)
 776                 goto fail2;
 777
 778         enp->en_rx_qcount++;
 779         *erpp = erp;
 780
 781         return (0);
 782
 783 fail2:
 784         EFSYS_PROBE(fail2);
 785
 786         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
 787 fail1:
 788         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 789
 790         return (rc);
 791 }
 792
 793         __checkReturn   efx_rc_t
 794 efx_rx_qcreate(
 795         __in            efx_nic_t *enp,
 796         __in            unsigned int index,
 797         __in            unsigned int label,
 798         __in            efx_rxq_type_t type,
 799         __in            efsys_mem_t *esmp,
 800         __in            size_t ndescs,
 801         __in            uint32_t id,
 802         __in            unsigned int flags,
 803         __in            efx_evq_t *eep,
 804         __deref_out     efx_rxq_t **erpp)
 805 {
 806         return efx_rx_qcreate_internal(enp, index, label, type, 0, esmp, ndescs,
 807             id, flags, eep, erpp);
 808 }
 809
 810 #if EFSYS_OPT_RX_PACKED_STREAM
 811
 812         __checkReturn   efx_rc_t
 813 efx_rx_qcreate_packed_stream(
 814         __in            efx_nic_t *enp,
 815         __in            unsigned int index,
 816         __in            unsigned int label,
 817         __in            uint32_t ps_buf_size,
 818         __in            efsys_mem_t *esmp,
 819         __in            size_t ndescs,
 820         __in            efx_evq_t *eep,
 821         __deref_out     efx_rxq_t **erpp)
 822 {
 823         return efx_rx_qcreate_internal(enp, index, label,
 824             EFX_RXQ_TYPE_PACKED_STREAM, ps_buf_size, esmp, ndescs,
 825             0 /* id unused on EF10 */, EFX_RXQ_FLAG_NONE, eep, erpp);
 826 }
 827
 828 #endif
 829
 830                         void
 831 efx_rx_qdestroy(
 832         __in            efx_rxq_t *erp)
 833 {
 834         efx_nic_t *enp = erp->er_enp;
 835         const efx_rx_ops_t *erxop = enp->en_erxop;
 836
 837         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 838
 839         erxop->erxo_qdestroy(erp);
 840 }
 841
 842         __checkReturn   efx_rc_t
 843 efx_pseudo_hdr_pkt_length_get(
 844         __in            efx_rxq_t *erp,
 845         __in            uint8_t *buffer,
 846         __out           uint16_t *lengthp)
 847 {
 848         efx_nic_t *enp = erp->er_enp;
 849         const efx_rx_ops_t *erxop = enp->en_erxop;
 850
 851         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 852
 853         return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
 854 }
 855
 856 #if EFSYS_OPT_RX_SCALE
 857         __checkReturn   uint32_t
 858 efx_pseudo_hdr_hash_get(
 859         __in            efx_rxq_t *erp,
 860         __in            efx_rx_hash_alg_t func,
 861         __in            uint8_t *buffer)
 862 {
 863         efx_nic_t *enp = erp->er_enp;
 864         const efx_rx_ops_t *erxop = enp->en_erxop;
 865
 866         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 867
 868         EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
 869         return (erxop->erxo_prefix_hash(enp, func, buffer));
 870 }
 871 #endif  /* EFSYS_OPT_RX_SCALE */
 872
 873 #if EFSYS_OPT_SIENA
 874
 875 static  __checkReturn   efx_rc_t
 876 siena_rx_init(
 877         __in            efx_nic_t *enp)
 878 {
 879         efx_oword_t oword;
 880         unsigned int index;
 881
 882         EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
 883
 884         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
 885         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
 886         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
 887         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
 888         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
 889         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
 890         EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
 891
 892         /* Zero the RSS table */
 893         for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
 894             index++) {
 895                 EFX_ZERO_OWORD(oword);
 896                 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
 897                                     index, &oword, B_TRUE);
 898         }
 899
 900 #if EFSYS_OPT_RX_SCALE
 901         /* The RSS key and indirection table are writable. */
 902         enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
 903
 904         /* Hardware can insert RX hash with/without RSS */
 905         enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
 906 #endif  /* EFSYS_OPT_RX_SCALE */
 907
 908         return (0);
 909 }
 910
 911 #if EFSYS_OPT_RX_SCATTER
 912 static  __checkReturn   efx_rc_t
 913 siena_rx_scatter_enable(
 914         __in            efx_nic_t *enp,
 915         __in            unsigned int buf_size)
 916 {
 917         unsigned int nbuf32;
 918         efx_oword_t oword;
 919         efx_rc_t rc;
 920
 921         nbuf32 = buf_size / 32;
 922         if ((nbuf32 == 0) ||
 923             (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
 924             ((buf_size % 32) != 0)) {
 925                 rc = EINVAL;
 926                 goto fail1;
 927         }
 928
 929         if (enp->en_rx_qcount > 0) {
 930                 rc = EBUSY;
 931                 goto fail2;
 932         }
 933
 934         /* Set scatter buffer size */
 935         EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
 936         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
 937         EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
 938
 939         /* Enable scatter for packets not matching a filter */
 940         EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
 941         EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
 942         EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
 943
 944         return (0);
 945
 946 fail2:
 947         EFSYS_PROBE(fail2);
 948 fail1:
 949         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 950
 951         return (rc);
 952 }
 953 #endif  /* EFSYS_OPT_RX_SCATTER */
 954
 955
 956 #define EFX_RX_LFSR_HASH(_enp, _insert)                                 \
 957         do {                                                            \
 958                 efx_oword_t oword;                                      \
 959                                                                         \
 960                 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword);        \
 961                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);      \
 962                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);       \
 963                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);       \
 964                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR,    \
 965                     (_insert) ? 1 : 0);                                 \
 966                 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword);       \
 967                                                                         \
 968                 if ((_enp)->en_family == EFX_FAMILY_SIENA) {            \
 969                         EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3,   \
 970                             &oword);                                    \
 971                         EFX_SET_OWORD_FIELD(oword,                      \
 972                             FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0);        \
 973                         EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3,  \
 974                             &oword);                                    \
 975                 }                                                       \
 976                                                                         \
 977                 _NOTE(CONSTANTCONDITION)                                \
 978         } while (B_FALSE)
 979
 980 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp)             \
 981         do {                                                            \
 982                 efx_oword_t oword;                                      \
 983                                                                         \
 984                 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword);        \
 985                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1);      \
 986                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH,           \
 987                     (_ip) ? 1 : 0);                                     \
 988                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP,           \
 989                     (_tcp) ? 0 : 1);                                    \
 990                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR,    \
 991                     (_insert) ? 1 : 0);                                 \
 992                 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword);       \
 993                                                                         \
 994                 _NOTE(CONSTANTCONDITION)                                \
 995         } while (B_FALSE)
 996
 997 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc)                 \
 998         do {                                                            \
 999                 efx_oword_t oword;                                      \
1000                                                                         \
1001                 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword);  \
1002                 EFX_SET_OWORD_FIELD(oword,                              \
1003                     FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1);                \
1004                 EFX_SET_OWORD_FIELD(oword,                              \
1005                     FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
1006                 EFX_SET_OWORD_FIELD(oword,                              \
1007                     FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1);   \
1008                 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1009                                                                         \
1010                 (_rc) = 0;                                              \
1011                                                                         \
1012                 _NOTE(CONSTANTCONDITION)                                \
1013         } while (B_FALSE)
1014
1015
1016 #if EFSYS_OPT_RX_SCALE
1017
1018 static  __checkReturn   efx_rc_t
1019 siena_rx_scale_mode_set(
1020         __in            efx_nic_t *enp,
1021         __in            uint32_t rss_context,
1022         __in            efx_rx_hash_alg_t alg,
1023         __in            efx_rx_hash_type_t type,
1024         __in            boolean_t insert)
1025 {
1026         efx_rx_hash_type_t type_ipv4 = EFX_RX_HASH(IPV4, 2TUPLE);
1027         efx_rx_hash_type_t type_ipv4_tcp = EFX_RX_HASH(IPV4_TCP, 4TUPLE);
1028         efx_rx_hash_type_t type_ipv6 = EFX_RX_HASH(IPV6, 2TUPLE);
1029         efx_rx_hash_type_t type_ipv6_tcp = EFX_RX_HASH(IPV6_TCP, 4TUPLE);
1030         efx_rc_t rc;
1031
1032         if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1033                 rc = EINVAL;
1034                 goto fail1;
1035         }
1036
1037         switch (alg) {
1038         case EFX_RX_HASHALG_LFSR:
1039                 EFX_RX_LFSR_HASH(enp, insert);
1040                 break;
1041
1042         case EFX_RX_HASHALG_TOEPLITZ:
1043                 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
1044                     (type & type_ipv4) == type_ipv4,
1045                     (type & type_ipv4_tcp) == type_ipv4_tcp);
1046
1047                 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
1048                     (type & type_ipv6) == type_ipv6,
1049                     (type & type_ipv6_tcp) == type_ipv6_tcp,
1050                     rc);
1051                 if (rc != 0)
1052                         goto fail2;
1053
1054                 break;
1055
1056         default:
1057                 rc = EINVAL;
1058                 goto fail3;
1059         }
1060
1061         return (0);
1062
1063 fail3:
1064         EFSYS_PROBE(fail3);
1065 fail2:
1066         EFSYS_PROBE(fail2);
1067 fail1:
1068         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1069
1070         EFX_RX_LFSR_HASH(enp, B_FALSE);
1071
1072         return (rc);
1073 }
1074 #endif
1075
1076 #if EFSYS_OPT_RX_SCALE
1077 static  __checkReturn   efx_rc_t
1078 siena_rx_scale_key_set(
1079         __in            efx_nic_t *enp,
1080         __in            uint32_t rss_context,
1081         __in_ecount(n)  uint8_t *key,
1082         __in            size_t n)
1083 {
1084         efx_oword_t oword;
1085         unsigned int byte;
1086         unsigned int offset;
1087         efx_rc_t rc;
1088
1089         if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1090                 rc = EINVAL;
1091                 goto fail1;
1092         }
1093
1094         byte = 0;
1095
1096         /* Write Toeplitz IPv4 hash key */
1097         EFX_ZERO_OWORD(oword);
1098         for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1099             offset > 0 && byte < n;
1100             --offset)
1101                 oword.eo_u8[offset - 1] = key[byte++];
1102
1103         EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1104
1105         byte = 0;
1106
1107         /* Verify Toeplitz IPv4 hash key */
1108         EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1109         for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1110             offset > 0 && byte < n;
1111             --offset) {
1112                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1113                         rc = EFAULT;
1114                         goto fail2;
1115                 }
1116         }
1117
1118         if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
1119                 goto done;
1120
1121         byte = 0;
1122
1123         /* Write Toeplitz IPv6 hash key 3 */
1124         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1125         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1126             FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1127             offset > 0 && byte < n;
1128             --offset)
1129                 oword.eo_u8[offset - 1] = key[byte++];
1130
1131         EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1132
1133         /* Write Toeplitz IPv6 hash key 2 */
1134         EFX_ZERO_OWORD(oword);
1135         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1136             FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1137             offset > 0 && byte < n;
1138             --offset)
1139                 oword.eo_u8[offset - 1] = key[byte++];
1140
1141         EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1142
1143         /* Write Toeplitz IPv6 hash key 1 */
1144         EFX_ZERO_OWORD(oword);
1145         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1146             FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1147             offset > 0 && byte < n;
1148             --offset)
1149                 oword.eo_u8[offset - 1] = key[byte++];
1150
1151         EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1152
1153         byte = 0;
1154
1155         /* Verify Toeplitz IPv6 hash key 3 */
1156         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1157         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1158             FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1159             offset > 0 && byte < n;
1160             --offset) {
1161                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1162                         rc = EFAULT;
1163                         goto fail3;
1164                 }
1165         }
1166
1167         /* Verify Toeplitz IPv6 hash key 2 */
1168         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1169         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1170             FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1171             offset > 0 && byte < n;
1172             --offset) {
1173                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1174                         rc = EFAULT;
1175                         goto fail4;
1176                 }
1177         }
1178
1179         /* Verify Toeplitz IPv6 hash key 1 */
1180         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1181         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1182             FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1183             offset > 0 && byte < n;
1184             --offset) {
1185                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1186                         rc = EFAULT;
1187                         goto fail5;
1188                 }
1189         }
1190
1191 done:
1192         return (0);
1193
1194 fail5:
1195         EFSYS_PROBE(fail5);
1196 fail4:
1197         EFSYS_PROBE(fail4);
1198 fail3:
1199         EFSYS_PROBE(fail3);
1200 fail2:
1201         EFSYS_PROBE(fail2);
1202 fail1:
1203         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1204
1205         return (rc);
1206 }
1207 #endif
1208
1209 #if EFSYS_OPT_RX_SCALE
1210 static  __checkReturn   efx_rc_t
1211 siena_rx_scale_tbl_set(
1212         __in            efx_nic_t *enp,
1213         __in            uint32_t rss_context,
1214         __in_ecount(n)  unsigned int *table,
1215         __in            size_t n)
1216 {
1217         efx_oword_t oword;
1218         int index;
1219         efx_rc_t rc;
1220
1221         EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
1222         EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
1223
1224         if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1225                 rc = EINVAL;
1226                 goto fail1;
1227         }
1228
1229         if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
1230                 rc = EINVAL;
1231                 goto fail2;
1232         }
1233
1234         for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
1235                 uint32_t byte;
1236
1237                 /* Calculate the entry to place in the table */
1238                 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1239
1240                 EFSYS_PROBE2(table, int, index, uint32_t, byte);
1241
1242                 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
1243
1244                 /* Write the table */
1245                 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1246                                     index, &oword, B_TRUE);
1247         }
1248
1249         for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
1250                 uint32_t byte;
1251
1252                 /* Determine if we're starting a new batch */
1253                 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1254
1255                 /* Read the table */
1256                 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
1257                                     index, &oword, B_TRUE);
1258
1259                 /* Verify the entry */
1260                 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1261                         rc = EFAULT;
1262                         goto fail3;
1263                 }
1264         }
1265
1266         return (0);
1267
1268 fail3:
1269         EFSYS_PROBE(fail3);
1270 fail2:
1271         EFSYS_PROBE(fail2);
1272 fail1:
1273         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1274
1275         return (rc);
1276 }
1277 #endif
1278
1279 /*
1280  * Falcon/Siena pseudo-header
1281  * --------------------------
1282  *
1283  * Receive packets are prefixed by an optional 16 byte pseudo-header.
1284  * The pseudo-header is a byte array of one of the forms:
1285  *
1286  *  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15
1287  * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1288  * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1289  *
1290  * where:
1291  *   TT.TT.TT.TT   Toeplitz hash (32-bit big-endian)
1292  *   LL.LL         LFSR hash     (16-bit big-endian)
1293  */
1294
1295 #if EFSYS_OPT_RX_SCALE
1296 static  __checkReturn   uint32_t
1297 siena_rx_prefix_hash(
1298         __in            efx_nic_t *enp,
1299         __in            efx_rx_hash_alg_t func,
1300         __in            uint8_t *buffer)
1301 {
1302         _NOTE(ARGUNUSED(enp))
1303
1304         switch (func) {
1305         case EFX_RX_HASHALG_TOEPLITZ:
1306                 return ((buffer[12] << 24) |
1307                     (buffer[13] << 16) |
1308                     (buffer[14] <<  8) |
1309                     buffer[15]);
1310
1311         case EFX_RX_HASHALG_LFSR:
1312                 return ((buffer[14] << 8) | buffer[15]);
1313
1314         default:
1315                 EFSYS_ASSERT(0);
1316                 return (0);
1317         }
1318 }
1319 #endif /* EFSYS_OPT_RX_SCALE */
1320
1321 static  __checkReturn   efx_rc_t
1322 siena_rx_prefix_pktlen(
1323         __in            efx_nic_t *enp,
1324         __in            uint8_t *buffer,
1325         __out           uint16_t *lengthp)
1326 {
1327         _NOTE(ARGUNUSED(enp, buffer, lengthp))
1328
1329         /* Not supported by Falcon/Siena hardware */
1330         EFSYS_ASSERT(0);
1331         return (ENOTSUP);
1332 }
1333
1334
1335 static                          void
1336 siena_rx_qpost(
1337         __in                    efx_rxq_t *erp,
1338         __in_ecount(ndescs)     efsys_dma_addr_t *addrp,
1339         __in                    size_t size,
1340         __in                    unsigned int ndescs,
1341         __in                    unsigned int completed,
1342         __in                    unsigned int added)
1343 {
1344         efx_qword_t qword;
1345         unsigned int i;
1346         unsigned int offset;
1347         unsigned int id;
1348
1349         /* The client driver must not overfill the queue */
1350         EFSYS_ASSERT3U(added - completed + ndescs, <=,
1351             EFX_RXQ_LIMIT(erp->er_mask + 1));
1352
1353         id = added & (erp->er_mask);
1354         for (i = 0; i < ndescs; i++) {
1355                 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1356                     unsigned int, id, efsys_dma_addr_t, addrp[i],
1357                     size_t, size);
1358
1359                 EFX_POPULATE_QWORD_3(qword,
1360                     FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1361                     FSF_AZ_RX_KER_BUF_ADDR_DW0,
1362                     (uint32_t)(addrp[i] & 0xffffffff),
1363                     FSF_AZ_RX_KER_BUF_ADDR_DW1,
1364                     (uint32_t)(addrp[i] >> 32));
1365
1366                 offset = id * sizeof (efx_qword_t);
1367                 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1368
1369                 id = (id + 1) & (erp->er_mask);
1370         }
1371 }
1372
1373 static                  void
1374 siena_rx_qpush(
1375         __in    efx_rxq_t *erp,
1376         __in    unsigned int added,
1377         __inout unsigned int *pushedp)
1378 {
1379         efx_nic_t *enp = erp->er_enp;
1380         unsigned int pushed = *pushedp;
1381         uint32_t wptr;
1382         efx_oword_t oword;
1383         efx_dword_t dword;
1384
1385         /* All descriptors are pushed */
1386         *pushedp = added;
1387
1388         /* Push the populated descriptors out */
1389         wptr = added & erp->er_mask;
1390
1391         EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1392
1393         /* Only write the third DWORD */
1394         EFX_POPULATE_DWORD_1(dword,
1395             EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1396
1397         /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1398         EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1399             wptr, pushed & erp->er_mask);
1400         EFSYS_PIO_WRITE_BARRIER();
1401         EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1402                             erp->er_index, &dword, B_FALSE);
1403 }
1404
1405 #if EFSYS_OPT_RX_PACKED_STREAM
1406 static          void
1407 siena_rx_qpush_ps_credits(
1408         __in            efx_rxq_t *erp)
1409 {
1410         /* Not supported by Siena hardware */
1411         EFSYS_ASSERT(0);
1412 }
1413
1414 static          uint8_t *
1415 siena_rx_qps_packet_info(
1416         __in            efx_rxq_t *erp,
1417         __in            uint8_t *buffer,
1418         __in            uint32_t buffer_length,
1419         __in            uint32_t current_offset,
1420         __out           uint16_t *lengthp,
1421         __out           uint32_t *next_offsetp,
1422         __out           uint32_t *timestamp)
1423 {
1424         /* Not supported by Siena hardware */
1425         EFSYS_ASSERT(0);
1426
1427         return (NULL);
1428 }
1429 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1430
1431 static  __checkReturn   efx_rc_t
1432 siena_rx_qflush(
1433         __in    efx_rxq_t *erp)
1434 {
1435         efx_nic_t *enp = erp->er_enp;
1436         efx_oword_t oword;
1437         uint32_t label;
1438
1439         label = erp->er_index;
1440
1441         /* Flush the queue */
1442         EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1443             FRF_AZ_RX_FLUSH_DESCQ, label);
1444         EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1445
1446         return (0);
1447 }
1448
1449 static          void
1450 siena_rx_qenable(
1451         __in    efx_rxq_t *erp)
1452 {
1453         efx_nic_t *enp = erp->er_enp;
1454         efx_oword_t oword;
1455
1456         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1457
1458         EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1459                             erp->er_index, &oword, B_TRUE);
1460
1461         EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1462         EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1463         EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1464
1465         EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1466                             erp->er_index, &oword, B_TRUE);
1467 }
1468
1469 static  __checkReturn   efx_rc_t
1470 siena_rx_qcreate(
1471         __in            efx_nic_t *enp,
1472         __in            unsigned int index,
1473         __in            unsigned int label,
1474         __in            efx_rxq_type_t type,
1475         __in            uint32_t type_data,
1476         __in            efsys_mem_t *esmp,
1477         __in            size_t ndescs,
1478         __in            uint32_t id,
1479         __in            unsigned int flags,
1480         __in            efx_evq_t *eep,
1481         __in            efx_rxq_t *erp)
1482 {
1483         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1484         efx_oword_t oword;
1485         uint32_t size;
1486         boolean_t jumbo = B_FALSE;
1487         efx_rc_t rc;
1488
1489         _NOTE(ARGUNUSED(esmp))
1490         _NOTE(ARGUNUSED(type_data))
1491
1492         EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1493             (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1494         EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1495         EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1496
1497         EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1498         EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1499
1500         if (!ISP2(ndescs) ||
1501             (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
1502                 rc = EINVAL;
1503                 goto fail1;
1504         }
1505         if (index >= encp->enc_rxq_limit) {
1506                 rc = EINVAL;
1507                 goto fail2;
1508         }
1509         for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1510             size++)
1511                 if ((1 << size) == (int)(ndescs / EFX_RXQ_MINNDESCS))
1512                         break;
1513         if (id + (1 << size) >= encp->enc_buftbl_limit) {
1514                 rc = EINVAL;
1515                 goto fail3;
1516         }
1517
1518         switch (type) {
1519         case EFX_RXQ_TYPE_DEFAULT:
1520                 break;
1521
1522         default:
1523                 rc = EINVAL;
1524                 goto fail4;
1525         }
1526
1527         if (flags & EFX_RXQ_FLAG_SCATTER) {
1528 #if EFSYS_OPT_RX_SCATTER
1529                 jumbo = B_TRUE;
1530 #else
1531                 rc = EINVAL;
1532                 goto fail5;
1533 #endif  /* EFSYS_OPT_RX_SCATTER */
1534         }
1535
1536         /* Set up the new descriptor queue */
1537         EFX_POPULATE_OWORD_7(oword,
1538             FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1539             FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1540             FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1541             FRF_AZ_RX_DESCQ_LABEL, label,
1542             FRF_AZ_RX_DESCQ_SIZE, size,
1543             FRF_AZ_RX_DESCQ_TYPE, 0,
1544             FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1545
1546         EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1547                             erp->er_index, &oword, B_TRUE);
1548
1549         return (0);
1550
1551 #if !EFSYS_OPT_RX_SCATTER
1552 fail5:
1553         EFSYS_PROBE(fail5);
1554 #endif
1555 fail4:
1556         EFSYS_PROBE(fail4);
1557 fail3:
1558         EFSYS_PROBE(fail3);
1559 fail2:
1560         EFSYS_PROBE(fail2);
1561 fail1:
1562         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1563
1564         return (rc);
1565 }
1566
1567 static          void
1568 siena_rx_qdestroy(
1569         __in    efx_rxq_t *erp)
1570 {
1571         efx_nic_t *enp = erp->er_enp;
1572         efx_oword_t oword;
1573
1574         EFSYS_ASSERT(enp->en_rx_qcount != 0);
1575         --enp->en_rx_qcount;
1576
1577         /* Purge descriptor queue */
1578         EFX_ZERO_OWORD(oword);
1579
1580         EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1581                             erp->er_index, &oword, B_TRUE);
1582
1583         /* Free the RXQ object */
1584         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1585 }
1586
1587 static          void
1588 siena_rx_fini(
1589         __in    efx_nic_t *enp)
1590 {
1591         _NOTE(ARGUNUSED(enp))
1592 }
1593
1594 #endif /* EFSYS_OPT_SIENA */