1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
13 static __checkReturn efx_rc_t
21 #if EFSYS_OPT_RX_SCATTER
22 static __checkReturn efx_rc_t
23 siena_rx_scatter_enable(
25 __in unsigned int buf_size);
26 #endif /* EFSYS_OPT_RX_SCATTER */
28 #if EFSYS_OPT_RX_SCALE
29 static __checkReturn efx_rc_t
30 siena_rx_scale_mode_set(
32 __in uint32_t rss_context,
33 __in efx_rx_hash_alg_t alg,
34 __in efx_rx_hash_type_t type,
35 __in boolean_t insert);
37 static __checkReturn efx_rc_t
38 siena_rx_scale_key_set(
40 __in uint32_t rss_context,
41 __in_ecount(n) uint8_t *key,
44 static __checkReturn efx_rc_t
45 siena_rx_scale_tbl_set(
47 __in uint32_t rss_context,
48 __in_ecount(n) unsigned int *table,
51 static __checkReturn uint32_t
54 __in efx_rx_hash_alg_t func,
55 __in uint8_t *buffer);
57 #endif /* EFSYS_OPT_RX_SCALE */
59 static __checkReturn efx_rc_t
60 siena_rx_prefix_pktlen(
63 __out uint16_t *lengthp);
68 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
70 __in unsigned int ndescs,
71 __in unsigned int completed,
72 __in unsigned int added);
77 __in unsigned int added,
78 __inout unsigned int *pushedp);
80 #if EFSYS_OPT_RX_PACKED_STREAM
82 siena_rx_qpush_ps_credits(
85 static __checkReturn uint8_t *
86 siena_rx_qps_packet_info(
89 __in uint32_t buffer_length,
90 __in uint32_t current_offset,
91 __out uint16_t *lengthp,
92 __out uint32_t *next_offsetp,
93 __out uint32_t *timestamp);
96 static __checkReturn efx_rc_t
102 __in efx_rxq_t *erp);
104 static __checkReturn efx_rc_t
107 __in unsigned int index,
108 __in unsigned int label,
109 __in efx_rxq_type_t type,
110 __in const efx_rxq_type_data_t *type_data,
111 __in efsys_mem_t *esmp,
114 __in unsigned int flags,
116 __in efx_rxq_t *erp);
120 __in efx_rxq_t *erp);
122 #endif /* EFSYS_OPT_SIENA */
126 static const efx_rx_ops_t __efx_rx_siena_ops = {
127 siena_rx_init, /* erxo_init */
128 siena_rx_fini, /* erxo_fini */
129 #if EFSYS_OPT_RX_SCATTER
130 siena_rx_scatter_enable, /* erxo_scatter_enable */
132 #if EFSYS_OPT_RX_SCALE
133 NULL, /* erxo_scale_context_alloc */
134 NULL, /* erxo_scale_context_free */
135 siena_rx_scale_mode_set, /* erxo_scale_mode_set */
136 siena_rx_scale_key_set, /* erxo_scale_key_set */
137 siena_rx_scale_tbl_set, /* erxo_scale_tbl_set */
138 siena_rx_prefix_hash, /* erxo_prefix_hash */
140 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
141 siena_rx_qpost, /* erxo_qpost */
142 siena_rx_qpush, /* erxo_qpush */
143 #if EFSYS_OPT_RX_PACKED_STREAM
144 siena_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
145 siena_rx_qps_packet_info, /* erxo_qps_packet_info */
147 siena_rx_qflush, /* erxo_qflush */
148 siena_rx_qenable, /* erxo_qenable */
149 siena_rx_qcreate, /* erxo_qcreate */
150 siena_rx_qdestroy, /* erxo_qdestroy */
152 #endif /* EFSYS_OPT_SIENA */
154 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
155 static const efx_rx_ops_t __efx_rx_ef10_ops = {
156 ef10_rx_init, /* erxo_init */
157 ef10_rx_fini, /* erxo_fini */
158 #if EFSYS_OPT_RX_SCATTER
159 ef10_rx_scatter_enable, /* erxo_scatter_enable */
161 #if EFSYS_OPT_RX_SCALE
162 ef10_rx_scale_context_alloc, /* erxo_scale_context_alloc */
163 ef10_rx_scale_context_free, /* erxo_scale_context_free */
164 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */
165 ef10_rx_scale_key_set, /* erxo_scale_key_set */
166 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */
167 ef10_rx_prefix_hash, /* erxo_prefix_hash */
169 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
170 ef10_rx_qpost, /* erxo_qpost */
171 ef10_rx_qpush, /* erxo_qpush */
172 #if EFSYS_OPT_RX_PACKED_STREAM
173 ef10_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
174 ef10_rx_qps_packet_info, /* erxo_qps_packet_info */
176 ef10_rx_qflush, /* erxo_qflush */
177 ef10_rx_qenable, /* erxo_qenable */
178 ef10_rx_qcreate, /* erxo_qcreate */
179 ef10_rx_qdestroy, /* erxo_qdestroy */
181 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
184 __checkReturn efx_rc_t
186 __inout efx_nic_t *enp)
188 const efx_rx_ops_t *erxop;
191 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
192 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
194 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
199 if (enp->en_mod_flags & EFX_MOD_RX) {
204 switch (enp->en_family) {
206 case EFX_FAMILY_SIENA:
207 erxop = &__efx_rx_siena_ops;
209 #endif /* EFSYS_OPT_SIENA */
211 #if EFSYS_OPT_HUNTINGTON
212 case EFX_FAMILY_HUNTINGTON:
213 erxop = &__efx_rx_ef10_ops;
215 #endif /* EFSYS_OPT_HUNTINGTON */
217 #if EFSYS_OPT_MEDFORD
218 case EFX_FAMILY_MEDFORD:
219 erxop = &__efx_rx_ef10_ops;
221 #endif /* EFSYS_OPT_MEDFORD */
223 #if EFSYS_OPT_MEDFORD2
224 case EFX_FAMILY_MEDFORD2:
225 erxop = &__efx_rx_ef10_ops;
227 #endif /* EFSYS_OPT_MEDFORD2 */
235 if ((rc = erxop->erxo_init(enp)) != 0)
238 enp->en_erxop = erxop;
239 enp->en_mod_flags |= EFX_MOD_RX;
249 EFSYS_PROBE1(fail1, efx_rc_t, rc);
251 enp->en_erxop = NULL;
252 enp->en_mod_flags &= ~EFX_MOD_RX;
260 const efx_rx_ops_t *erxop = enp->en_erxop;
262 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
263 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
264 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
265 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
267 erxop->erxo_fini(enp);
269 enp->en_erxop = NULL;
270 enp->en_mod_flags &= ~EFX_MOD_RX;
273 #if EFSYS_OPT_RX_SCATTER
274 __checkReturn efx_rc_t
275 efx_rx_scatter_enable(
277 __in unsigned int buf_size)
279 const efx_rx_ops_t *erxop = enp->en_erxop;
282 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
283 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
285 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
291 EFSYS_PROBE1(fail1, efx_rc_t, rc);
294 #endif /* EFSYS_OPT_RX_SCATTER */
296 #if EFSYS_OPT_RX_SCALE
297 __checkReturn efx_rc_t
298 efx_rx_scale_hash_flags_get(
300 __in efx_rx_hash_alg_t hash_alg,
301 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
302 __in unsigned int max_nflags,
303 __out unsigned int *nflagsp)
305 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
306 unsigned int nflags = 0;
309 if (flagsp == NULL || nflagsp == NULL) {
314 if ((encp->enc_rx_scale_hash_alg_mask & (1U << hash_alg)) == 0) {
319 /* Helper to add flags word to flags array without buffer overflow */
320 #define INSERT_FLAGS(_flags) \
322 if (nflags >= max_nflags) { \
326 *(flagsp + nflags) = (_flags); \
329 _NOTE(CONSTANTCONDITION) \
332 if (encp->enc_rx_scale_l4_hash_supported != B_FALSE) {
333 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 4TUPLE));
334 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 4TUPLE));
337 if ((encp->enc_rx_scale_l4_hash_supported != B_FALSE) &&
338 (encp->enc_rx_scale_additional_modes_supported != B_FALSE)) {
339 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE_DST));
340 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE_SRC));
342 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE_DST));
343 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE_SRC));
345 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 4TUPLE));
346 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE_DST));
347 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE_SRC));
349 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 4TUPLE));
350 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE_DST));
351 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE_SRC));
354 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE));
355 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE));
357 INSERT_FLAGS(EFX_RX_HASH(IPV4, 2TUPLE));
358 INSERT_FLAGS(EFX_RX_HASH(IPV6, 2TUPLE));
360 if (encp->enc_rx_scale_additional_modes_supported != B_FALSE) {
361 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 1TUPLE_DST));
362 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 1TUPLE_SRC));
364 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 1TUPLE_DST));
365 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 1TUPLE_SRC));
367 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE));
368 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 1TUPLE_DST));
369 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 1TUPLE_SRC));
371 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE));
372 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 1TUPLE_DST));
373 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 1TUPLE_SRC));
375 INSERT_FLAGS(EFX_RX_HASH(IPV4, 1TUPLE_DST));
376 INSERT_FLAGS(EFX_RX_HASH(IPV4, 1TUPLE_SRC));
378 INSERT_FLAGS(EFX_RX_HASH(IPV6, 1TUPLE_DST));
379 INSERT_FLAGS(EFX_RX_HASH(IPV6, 1TUPLE_SRC));
382 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, DISABLE));
383 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, DISABLE));
385 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, DISABLE));
386 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, DISABLE));
388 INSERT_FLAGS(EFX_RX_HASH(IPV4, DISABLE));
389 INSERT_FLAGS(EFX_RX_HASH(IPV6, DISABLE));
400 EFSYS_PROBE1(fail1, efx_rc_t, rc);
405 __checkReturn efx_rc_t
406 efx_rx_hash_default_support_get(
408 __out efx_rx_hash_support_t *supportp)
412 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
413 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
415 if (supportp == NULL) {
421 * Report the hashing support the client gets by default if it
422 * does not allocate an RSS context itself.
424 *supportp = enp->en_hash_support;
429 EFSYS_PROBE1(fail1, efx_rc_t, rc);
434 __checkReturn efx_rc_t
435 efx_rx_scale_default_support_get(
437 __out efx_rx_scale_context_type_t *typep)
441 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
442 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
450 * Report the RSS support the client gets by default if it
451 * does not allocate an RSS context itself.
453 *typep = enp->en_rss_context_type;
458 EFSYS_PROBE1(fail1, efx_rc_t, rc);
462 #endif /* EFSYS_OPT_RX_SCALE */
464 #if EFSYS_OPT_RX_SCALE
465 __checkReturn efx_rc_t
466 efx_rx_scale_context_alloc(
468 __in efx_rx_scale_context_type_t type,
469 __in uint32_t num_queues,
470 __out uint32_t *rss_contextp)
472 const efx_rx_ops_t *erxop = enp->en_erxop;
475 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
476 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
478 if (erxop->erxo_scale_context_alloc == NULL) {
482 if ((rc = erxop->erxo_scale_context_alloc(enp, type,
483 num_queues, rss_contextp)) != 0) {
492 EFSYS_PROBE1(fail1, efx_rc_t, rc);
495 #endif /* EFSYS_OPT_RX_SCALE */
497 #if EFSYS_OPT_RX_SCALE
498 __checkReturn efx_rc_t
499 efx_rx_scale_context_free(
501 __in uint32_t rss_context)
503 const efx_rx_ops_t *erxop = enp->en_erxop;
506 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
507 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
509 if (erxop->erxo_scale_context_free == NULL) {
513 if ((rc = erxop->erxo_scale_context_free(enp, rss_context)) != 0)
521 EFSYS_PROBE1(fail1, efx_rc_t, rc);
524 #endif /* EFSYS_OPT_RX_SCALE */
526 #if EFSYS_OPT_RX_SCALE
527 __checkReturn efx_rc_t
528 efx_rx_scale_mode_set(
530 __in uint32_t rss_context,
531 __in efx_rx_hash_alg_t alg,
532 __in efx_rx_hash_type_t type,
533 __in boolean_t insert)
535 const efx_rx_ops_t *erxop = enp->en_erxop;
536 unsigned int type_flags[EFX_RX_HASH_NFLAGS];
537 unsigned int type_nflags;
538 efx_rx_hash_type_t type_check;
542 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
543 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
546 * Legacy flags and modern bits cannot be
547 * used at the same time in the hash type.
549 if ((type & EFX_RX_HASH_LEGACY_MASK) &&
550 (type & ~EFX_RX_HASH_LEGACY_MASK)) {
556 * Translate legacy flags to the new representation
557 * so that chip-specific handlers will consider the
560 if (type & EFX_RX_HASH_IPV4) {
561 type |= EFX_RX_HASH(IPV4, 2TUPLE);
562 type |= EFX_RX_HASH(IPV4_TCP, 2TUPLE);
563 type |= EFX_RX_HASH(IPV4_UDP, 2TUPLE);
566 if (type & EFX_RX_HASH_TCPIPV4)
567 type |= EFX_RX_HASH(IPV4_TCP, 4TUPLE);
569 if (type & EFX_RX_HASH_IPV6) {
570 type |= EFX_RX_HASH(IPV6, 2TUPLE);
571 type |= EFX_RX_HASH(IPV6_TCP, 2TUPLE);
572 type |= EFX_RX_HASH(IPV6_UDP, 2TUPLE);
575 if (type & EFX_RX_HASH_TCPIPV6)
576 type |= EFX_RX_HASH(IPV6_TCP, 4TUPLE);
578 type &= ~EFX_RX_HASH_LEGACY_MASK;
582 * Get the list of supported hash flags and sanitise the input.
584 rc = efx_rx_scale_hash_flags_get(enp, alg, type_flags,
585 EFX_ARRAY_SIZE(type_flags), &type_nflags);
589 for (i = 0; i < type_nflags; ++i) {
590 if ((type_check & type_flags[i]) == type_flags[i])
591 type_check &= ~(type_flags[i]);
594 if (type_check != 0) {
599 if (erxop->erxo_scale_mode_set != NULL) {
600 if ((rc = erxop->erxo_scale_mode_set(enp, rss_context, alg,
614 EFSYS_PROBE1(fail1, efx_rc_t, rc);
617 #endif /* EFSYS_OPT_RX_SCALE */
619 #if EFSYS_OPT_RX_SCALE
620 __checkReturn efx_rc_t
621 efx_rx_scale_key_set(
623 __in uint32_t rss_context,
624 __in_ecount(n) uint8_t *key,
627 const efx_rx_ops_t *erxop = enp->en_erxop;
630 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
631 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
633 if ((rc = erxop->erxo_scale_key_set(enp, rss_context, key, n)) != 0)
639 EFSYS_PROBE1(fail1, efx_rc_t, rc);
643 #endif /* EFSYS_OPT_RX_SCALE */
645 #if EFSYS_OPT_RX_SCALE
646 __checkReturn efx_rc_t
647 efx_rx_scale_tbl_set(
649 __in uint32_t rss_context,
650 __in_ecount(n) unsigned int *table,
653 const efx_rx_ops_t *erxop = enp->en_erxop;
656 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
657 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
659 if ((rc = erxop->erxo_scale_tbl_set(enp, rss_context, table, n)) != 0)
665 EFSYS_PROBE1(fail1, efx_rc_t, rc);
669 #endif /* EFSYS_OPT_RX_SCALE */
674 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
676 __in unsigned int ndescs,
677 __in unsigned int completed,
678 __in unsigned int added)
680 efx_nic_t *enp = erp->er_enp;
681 const efx_rx_ops_t *erxop = enp->en_erxop;
683 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
685 erxop->erxo_qpost(erp, addrp, size, ndescs, completed, added);
688 #if EFSYS_OPT_RX_PACKED_STREAM
691 efx_rx_qpush_ps_credits(
694 efx_nic_t *enp = erp->er_enp;
695 const efx_rx_ops_t *erxop = enp->en_erxop;
697 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
699 erxop->erxo_qpush_ps_credits(erp);
702 __checkReturn uint8_t *
703 efx_rx_qps_packet_info(
705 __in uint8_t *buffer,
706 __in uint32_t buffer_length,
707 __in uint32_t current_offset,
708 __out uint16_t *lengthp,
709 __out uint32_t *next_offsetp,
710 __out uint32_t *timestamp)
712 efx_nic_t *enp = erp->er_enp;
713 const efx_rx_ops_t *erxop = enp->en_erxop;
715 return (erxop->erxo_qps_packet_info(erp, buffer,
716 buffer_length, current_offset, lengthp,
717 next_offsetp, timestamp));
720 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
725 __in unsigned int added,
726 __inout unsigned int *pushedp)
728 efx_nic_t *enp = erp->er_enp;
729 const efx_rx_ops_t *erxop = enp->en_erxop;
731 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
733 erxop->erxo_qpush(erp, added, pushedp);
736 __checkReturn efx_rc_t
740 efx_nic_t *enp = erp->er_enp;
741 const efx_rx_ops_t *erxop = enp->en_erxop;
744 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
746 if ((rc = erxop->erxo_qflush(erp)) != 0)
752 EFSYS_PROBE1(fail1, efx_rc_t, rc);
761 efx_nic_t *enp = erp->er_enp;
762 const efx_rx_ops_t *erxop = enp->en_erxop;
764 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
766 erxop->erxo_qenable(erp);
769 static __checkReturn efx_rc_t
770 efx_rx_qcreate_internal(
772 __in unsigned int index,
773 __in unsigned int label,
774 __in efx_rxq_type_t type,
775 __in const efx_rxq_type_data_t *type_data,
776 __in efsys_mem_t *esmp,
779 __in unsigned int flags,
781 __deref_out efx_rxq_t **erpp)
783 const efx_rx_ops_t *erxop = enp->en_erxop;
787 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
788 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
790 /* Allocate an RXQ object */
791 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
798 erp->er_magic = EFX_RXQ_MAGIC;
800 erp->er_index = index;
801 erp->er_mask = ndescs - 1;
804 if ((rc = erxop->erxo_qcreate(enp, index, label, type, type_data, esmp,
805 ndescs, id, flags, eep, erp)) != 0)
816 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
818 EFSYS_PROBE1(fail1, efx_rc_t, rc);
823 __checkReturn efx_rc_t
826 __in unsigned int index,
827 __in unsigned int label,
828 __in efx_rxq_type_t type,
829 __in efsys_mem_t *esmp,
832 __in unsigned int flags,
834 __deref_out efx_rxq_t **erpp)
836 return efx_rx_qcreate_internal(enp, index, label, type, NULL,
837 esmp, ndescs, id, flags, eep, erpp);
840 #if EFSYS_OPT_RX_PACKED_STREAM
842 __checkReturn efx_rc_t
843 efx_rx_qcreate_packed_stream(
845 __in unsigned int index,
846 __in unsigned int label,
847 __in uint32_t ps_buf_size,
848 __in efsys_mem_t *esmp,
851 __deref_out efx_rxq_t **erpp)
853 efx_rxq_type_data_t type_data;
855 memset(&type_data, 0, sizeof (type_data));
857 type_data.ertd_packed_stream.eps_buf_size = ps_buf_size;
859 return efx_rx_qcreate_internal(enp, index, label,
860 EFX_RXQ_TYPE_PACKED_STREAM, &type_data, esmp, ndescs,
861 0 /* id unused on EF10 */, EFX_RXQ_FLAG_NONE, eep, erpp);
866 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
868 __checkReturn efx_rc_t
869 efx_rx_qcreate_es_super_buffer(
871 __in unsigned int index,
872 __in unsigned int label,
873 __in uint32_t n_bufs_per_desc,
874 __in uint32_t max_dma_len,
875 __in uint32_t buf_stride,
876 __in uint32_t hol_block_timeout,
877 __in efsys_mem_t *esmp,
879 __in unsigned int flags,
881 __deref_out efx_rxq_t **erpp)
884 efx_rxq_type_data_t type_data;
886 if (hol_block_timeout > EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX) {
891 memset(&type_data, 0, sizeof (type_data));
893 type_data.ertd_es_super_buffer.eessb_bufs_per_desc = n_bufs_per_desc;
894 type_data.ertd_es_super_buffer.eessb_max_dma_len = max_dma_len;
895 type_data.ertd_es_super_buffer.eessb_buf_stride = buf_stride;
896 type_data.ertd_es_super_buffer.eessb_hol_block_timeout =
899 rc = efx_rx_qcreate_internal(enp, index, label,
900 EFX_RXQ_TYPE_ES_SUPER_BUFFER, &type_data, esmp, ndescs,
901 0 /* id unused on EF10 */, flags, eep, erpp);
910 EFSYS_PROBE1(fail1, efx_rc_t, rc);
922 efx_nic_t *enp = erp->er_enp;
923 const efx_rx_ops_t *erxop = enp->en_erxop;
925 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
927 erxop->erxo_qdestroy(erp);
930 __checkReturn efx_rc_t
931 efx_pseudo_hdr_pkt_length_get(
933 __in uint8_t *buffer,
934 __out uint16_t *lengthp)
936 efx_nic_t *enp = erp->er_enp;
937 const efx_rx_ops_t *erxop = enp->en_erxop;
939 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
941 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
944 #if EFSYS_OPT_RX_SCALE
945 __checkReturn uint32_t
946 efx_pseudo_hdr_hash_get(
948 __in efx_rx_hash_alg_t func,
949 __in uint8_t *buffer)
951 efx_nic_t *enp = erp->er_enp;
952 const efx_rx_ops_t *erxop = enp->en_erxop;
954 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
956 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
957 return (erxop->erxo_prefix_hash(enp, func, buffer));
959 #endif /* EFSYS_OPT_RX_SCALE */
963 static __checkReturn efx_rc_t
970 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
972 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
973 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
974 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
975 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
976 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
977 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
978 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
980 /* Zero the RSS table */
981 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
983 EFX_ZERO_OWORD(oword);
984 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
985 index, &oword, B_TRUE);
988 #if EFSYS_OPT_RX_SCALE
989 /* The RSS key and indirection table are writable. */
990 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
992 /* Hardware can insert RX hash with/without RSS */
993 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
994 #endif /* EFSYS_OPT_RX_SCALE */
999 #if EFSYS_OPT_RX_SCATTER
1000 static __checkReturn efx_rc_t
1001 siena_rx_scatter_enable(
1002 __in efx_nic_t *enp,
1003 __in unsigned int buf_size)
1005 unsigned int nbuf32;
1009 nbuf32 = buf_size / 32;
1010 if ((nbuf32 == 0) ||
1011 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
1012 ((buf_size % 32) != 0)) {
1017 if (enp->en_rx_qcount > 0) {
1022 /* Set scatter buffer size */
1023 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
1024 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
1025 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
1027 /* Enable scatter for packets not matching a filter */
1028 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
1029 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
1030 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
1037 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1041 #endif /* EFSYS_OPT_RX_SCATTER */
1044 #define EFX_RX_LFSR_HASH(_enp, _insert) \
1046 efx_oword_t oword; \
1048 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1049 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
1050 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
1051 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
1052 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
1053 (_insert) ? 1 : 0); \
1054 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1056 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
1057 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
1059 EFX_SET_OWORD_FIELD(oword, \
1060 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
1061 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
1065 _NOTE(CONSTANTCONDITION) \
1068 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
1070 efx_oword_t oword; \
1072 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1073 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
1074 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
1076 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
1078 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
1079 (_insert) ? 1 : 0); \
1080 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1082 _NOTE(CONSTANTCONDITION) \
1085 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
1087 efx_oword_t oword; \
1089 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1090 EFX_SET_OWORD_FIELD(oword, \
1091 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
1092 EFX_SET_OWORD_FIELD(oword, \
1093 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
1094 EFX_SET_OWORD_FIELD(oword, \
1095 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
1096 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1100 _NOTE(CONSTANTCONDITION) \
1104 #if EFSYS_OPT_RX_SCALE
1106 static __checkReturn efx_rc_t
1107 siena_rx_scale_mode_set(
1108 __in efx_nic_t *enp,
1109 __in uint32_t rss_context,
1110 __in efx_rx_hash_alg_t alg,
1111 __in efx_rx_hash_type_t type,
1112 __in boolean_t insert)
1114 efx_rx_hash_type_t type_ipv4 = EFX_RX_HASH(IPV4, 2TUPLE);
1115 efx_rx_hash_type_t type_ipv4_tcp = EFX_RX_HASH(IPV4_TCP, 4TUPLE);
1116 efx_rx_hash_type_t type_ipv6 = EFX_RX_HASH(IPV6, 2TUPLE);
1117 efx_rx_hash_type_t type_ipv6_tcp = EFX_RX_HASH(IPV6_TCP, 4TUPLE);
1120 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1126 case EFX_RX_HASHALG_LFSR:
1127 EFX_RX_LFSR_HASH(enp, insert);
1130 case EFX_RX_HASHALG_TOEPLITZ:
1131 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
1132 (type & type_ipv4) == type_ipv4,
1133 (type & type_ipv4_tcp) == type_ipv4_tcp);
1135 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
1136 (type & type_ipv6) == type_ipv6,
1137 (type & type_ipv6_tcp) == type_ipv6_tcp,
1156 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1158 EFX_RX_LFSR_HASH(enp, B_FALSE);
1164 #if EFSYS_OPT_RX_SCALE
1165 static __checkReturn efx_rc_t
1166 siena_rx_scale_key_set(
1167 __in efx_nic_t *enp,
1168 __in uint32_t rss_context,
1169 __in_ecount(n) uint8_t *key,
1174 unsigned int offset;
1177 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1184 /* Write Toeplitz IPv4 hash key */
1185 EFX_ZERO_OWORD(oword);
1186 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1187 offset > 0 && byte < n;
1189 oword.eo_u8[offset - 1] = key[byte++];
1191 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1195 /* Verify Toeplitz IPv4 hash key */
1196 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1197 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1198 offset > 0 && byte < n;
1200 if (oword.eo_u8[offset - 1] != key[byte++]) {
1206 if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
1211 /* Write Toeplitz IPv6 hash key 3 */
1212 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1213 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1214 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1215 offset > 0 && byte < n;
1217 oword.eo_u8[offset - 1] = key[byte++];
1219 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1221 /* Write Toeplitz IPv6 hash key 2 */
1222 EFX_ZERO_OWORD(oword);
1223 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1224 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1225 offset > 0 && byte < n;
1227 oword.eo_u8[offset - 1] = key[byte++];
1229 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1231 /* Write Toeplitz IPv6 hash key 1 */
1232 EFX_ZERO_OWORD(oword);
1233 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1234 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1235 offset > 0 && byte < n;
1237 oword.eo_u8[offset - 1] = key[byte++];
1239 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1243 /* Verify Toeplitz IPv6 hash key 3 */
1244 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1245 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1246 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1247 offset > 0 && byte < n;
1249 if (oword.eo_u8[offset - 1] != key[byte++]) {
1255 /* Verify Toeplitz IPv6 hash key 2 */
1256 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1257 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1258 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1259 offset > 0 && byte < n;
1261 if (oword.eo_u8[offset - 1] != key[byte++]) {
1267 /* Verify Toeplitz IPv6 hash key 1 */
1268 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1269 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1270 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1271 offset > 0 && byte < n;
1273 if (oword.eo_u8[offset - 1] != key[byte++]) {
1291 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1297 #if EFSYS_OPT_RX_SCALE
1298 static __checkReturn efx_rc_t
1299 siena_rx_scale_tbl_set(
1300 __in efx_nic_t *enp,
1301 __in uint32_t rss_context,
1302 __in_ecount(n) unsigned int *table,
1309 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
1310 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
1312 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1317 if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
1322 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
1325 /* Calculate the entry to place in the table */
1326 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1328 EFSYS_PROBE2(table, int, index, uint32_t, byte);
1330 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
1332 /* Write the table */
1333 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1334 index, &oword, B_TRUE);
1337 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
1340 /* Determine if we're starting a new batch */
1341 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1343 /* Read the table */
1344 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
1345 index, &oword, B_TRUE);
1347 /* Verify the entry */
1348 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1361 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1368 * Falcon/Siena pseudo-header
1369 * --------------------------
1371 * Receive packets are prefixed by an optional 16 byte pseudo-header.
1372 * The pseudo-header is a byte array of one of the forms:
1374 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1375 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1376 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1379 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
1380 * LL.LL LFSR hash (16-bit big-endian)
1383 #if EFSYS_OPT_RX_SCALE
1384 static __checkReturn uint32_t
1385 siena_rx_prefix_hash(
1386 __in efx_nic_t *enp,
1387 __in efx_rx_hash_alg_t func,
1388 __in uint8_t *buffer)
1390 _NOTE(ARGUNUSED(enp))
1393 case EFX_RX_HASHALG_TOEPLITZ:
1394 return ((buffer[12] << 24) |
1395 (buffer[13] << 16) |
1399 case EFX_RX_HASHALG_LFSR:
1400 return ((buffer[14] << 8) | buffer[15]);
1407 #endif /* EFSYS_OPT_RX_SCALE */
1409 static __checkReturn efx_rc_t
1410 siena_rx_prefix_pktlen(
1411 __in efx_nic_t *enp,
1412 __in uint8_t *buffer,
1413 __out uint16_t *lengthp)
1415 _NOTE(ARGUNUSED(enp, buffer, lengthp))
1417 /* Not supported by Falcon/Siena hardware */
1425 __in efx_rxq_t *erp,
1426 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1428 __in unsigned int ndescs,
1429 __in unsigned int completed,
1430 __in unsigned int added)
1434 unsigned int offset;
1437 /* The client driver must not overfill the queue */
1438 EFSYS_ASSERT3U(added - completed + ndescs, <=,
1439 EFX_RXQ_LIMIT(erp->er_mask + 1));
1441 id = added & (erp->er_mask);
1442 for (i = 0; i < ndescs; i++) {
1443 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1444 unsigned int, id, efsys_dma_addr_t, addrp[i],
1447 EFX_POPULATE_QWORD_3(qword,
1448 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1449 FSF_AZ_RX_KER_BUF_ADDR_DW0,
1450 (uint32_t)(addrp[i] & 0xffffffff),
1451 FSF_AZ_RX_KER_BUF_ADDR_DW1,
1452 (uint32_t)(addrp[i] >> 32));
1454 offset = id * sizeof (efx_qword_t);
1455 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1457 id = (id + 1) & (erp->er_mask);
1463 __in efx_rxq_t *erp,
1464 __in unsigned int added,
1465 __inout unsigned int *pushedp)
1467 efx_nic_t *enp = erp->er_enp;
1468 unsigned int pushed = *pushedp;
1473 /* All descriptors are pushed */
1476 /* Push the populated descriptors out */
1477 wptr = added & erp->er_mask;
1479 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1481 /* Only write the third DWORD */
1482 EFX_POPULATE_DWORD_1(dword,
1483 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1485 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1486 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1487 wptr, pushed & erp->er_mask);
1488 EFSYS_PIO_WRITE_BARRIER();
1489 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1490 erp->er_index, &dword, B_FALSE);
1493 #if EFSYS_OPT_RX_PACKED_STREAM
1495 siena_rx_qpush_ps_credits(
1496 __in efx_rxq_t *erp)
1498 /* Not supported by Siena hardware */
1503 siena_rx_qps_packet_info(
1504 __in efx_rxq_t *erp,
1505 __in uint8_t *buffer,
1506 __in uint32_t buffer_length,
1507 __in uint32_t current_offset,
1508 __out uint16_t *lengthp,
1509 __out uint32_t *next_offsetp,
1510 __out uint32_t *timestamp)
1512 /* Not supported by Siena hardware */
1517 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1519 static __checkReturn efx_rc_t
1521 __in efx_rxq_t *erp)
1523 efx_nic_t *enp = erp->er_enp;
1527 label = erp->er_index;
1529 /* Flush the queue */
1530 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1531 FRF_AZ_RX_FLUSH_DESCQ, label);
1532 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1539 __in efx_rxq_t *erp)
1541 efx_nic_t *enp = erp->er_enp;
1544 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1546 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1547 erp->er_index, &oword, B_TRUE);
1549 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1550 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1551 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1553 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1554 erp->er_index, &oword, B_TRUE);
1557 static __checkReturn efx_rc_t
1559 __in efx_nic_t *enp,
1560 __in unsigned int index,
1561 __in unsigned int label,
1562 __in efx_rxq_type_t type,
1563 __in const efx_rxq_type_data_t *type_data,
1564 __in efsys_mem_t *esmp,
1567 __in unsigned int flags,
1568 __in efx_evq_t *eep,
1569 __in efx_rxq_t *erp)
1571 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1574 boolean_t jumbo = B_FALSE;
1577 _NOTE(ARGUNUSED(esmp))
1578 _NOTE(ARGUNUSED(type_data))
1580 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1581 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1582 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1583 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1585 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1586 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1588 if (!ISP2(ndescs) ||
1589 (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
1593 if (index >= encp->enc_rxq_limit) {
1597 for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1599 if ((1 << size) == (int)(ndescs / EFX_RXQ_MINNDESCS))
1601 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1607 case EFX_RXQ_TYPE_DEFAULT:
1615 if (flags & EFX_RXQ_FLAG_SCATTER) {
1616 #if EFSYS_OPT_RX_SCATTER
1621 #endif /* EFSYS_OPT_RX_SCATTER */
1624 /* Set up the new descriptor queue */
1625 EFX_POPULATE_OWORD_7(oword,
1626 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1627 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1628 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1629 FRF_AZ_RX_DESCQ_LABEL, label,
1630 FRF_AZ_RX_DESCQ_SIZE, size,
1631 FRF_AZ_RX_DESCQ_TYPE, 0,
1632 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1634 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1635 erp->er_index, &oword, B_TRUE);
1639 #if !EFSYS_OPT_RX_SCATTER
1650 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1657 __in efx_rxq_t *erp)
1659 efx_nic_t *enp = erp->er_enp;
1662 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1663 --enp->en_rx_qcount;
1665 /* Purge descriptor queue */
1666 EFX_ZERO_OWORD(oword);
1668 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1669 erp->er_index, &oword, B_TRUE);
1671 /* Free the RXQ object */
1672 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1677 __in efx_nic_t *enp)
1679 _NOTE(ARGUNUSED(enp))
1682 #endif /* EFSYS_OPT_SIENA */