1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
13 static __checkReturn efx_rc_t
21 #if EFSYS_OPT_RX_SCATTER
22 static __checkReturn efx_rc_t
23 siena_rx_scatter_enable(
25 __in unsigned int buf_size);
26 #endif /* EFSYS_OPT_RX_SCATTER */
28 #if EFSYS_OPT_RX_SCALE
29 static __checkReturn efx_rc_t
30 siena_rx_scale_mode_set(
32 __in uint32_t rss_context,
33 __in efx_rx_hash_alg_t alg,
34 __in efx_rx_hash_type_t type,
35 __in boolean_t insert);
37 static __checkReturn efx_rc_t
38 siena_rx_scale_key_set(
40 __in uint32_t rss_context,
41 __in_ecount(n) uint8_t *key,
44 static __checkReturn efx_rc_t
45 siena_rx_scale_tbl_set(
47 __in uint32_t rss_context,
48 __in_ecount(n) unsigned int *table,
51 static __checkReturn uint32_t
54 __in efx_rx_hash_alg_t func,
55 __in uint8_t *buffer);
57 #endif /* EFSYS_OPT_RX_SCALE */
59 static __checkReturn efx_rc_t
60 siena_rx_prefix_pktlen(
63 __out uint16_t *lengthp);
68 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
70 __in unsigned int ndescs,
71 __in unsigned int completed,
72 __in unsigned int added);
77 __in unsigned int added,
78 __inout unsigned int *pushedp);
80 #if EFSYS_OPT_RX_PACKED_STREAM
82 siena_rx_qpush_ps_credits(
85 static __checkReturn uint8_t *
86 siena_rx_qps_packet_info(
89 __in uint32_t buffer_length,
90 __in uint32_t current_offset,
91 __out uint16_t *lengthp,
92 __out uint32_t *next_offsetp,
93 __out uint32_t *timestamp);
96 static __checkReturn efx_rc_t
102 __in efx_rxq_t *erp);
104 static __checkReturn efx_rc_t
107 __in unsigned int index,
108 __in unsigned int label,
109 __in efx_rxq_type_t type,
110 __in uint32_t type_data,
111 __in efsys_mem_t *esmp,
114 __in unsigned int flags,
116 __in efx_rxq_t *erp);
120 __in efx_rxq_t *erp);
122 #endif /* EFSYS_OPT_SIENA */
126 static const efx_rx_ops_t __efx_rx_siena_ops = {
127 siena_rx_init, /* erxo_init */
128 siena_rx_fini, /* erxo_fini */
129 #if EFSYS_OPT_RX_SCATTER
130 siena_rx_scatter_enable, /* erxo_scatter_enable */
132 #if EFSYS_OPT_RX_SCALE
133 NULL, /* erxo_scale_context_alloc */
134 NULL, /* erxo_scale_context_free */
135 siena_rx_scale_mode_set, /* erxo_scale_mode_set */
136 siena_rx_scale_key_set, /* erxo_scale_key_set */
137 siena_rx_scale_tbl_set, /* erxo_scale_tbl_set */
138 siena_rx_prefix_hash, /* erxo_prefix_hash */
140 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
141 siena_rx_qpost, /* erxo_qpost */
142 siena_rx_qpush, /* erxo_qpush */
143 #if EFSYS_OPT_RX_PACKED_STREAM
144 siena_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
145 siena_rx_qps_packet_info, /* erxo_qps_packet_info */
147 siena_rx_qflush, /* erxo_qflush */
148 siena_rx_qenable, /* erxo_qenable */
149 siena_rx_qcreate, /* erxo_qcreate */
150 siena_rx_qdestroy, /* erxo_qdestroy */
152 #endif /* EFSYS_OPT_SIENA */
154 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
155 static const efx_rx_ops_t __efx_rx_ef10_ops = {
156 ef10_rx_init, /* erxo_init */
157 ef10_rx_fini, /* erxo_fini */
158 #if EFSYS_OPT_RX_SCATTER
159 ef10_rx_scatter_enable, /* erxo_scatter_enable */
161 #if EFSYS_OPT_RX_SCALE
162 ef10_rx_scale_context_alloc, /* erxo_scale_context_alloc */
163 ef10_rx_scale_context_free, /* erxo_scale_context_free */
164 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */
165 ef10_rx_scale_key_set, /* erxo_scale_key_set */
166 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */
167 ef10_rx_prefix_hash, /* erxo_prefix_hash */
169 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
170 ef10_rx_qpost, /* erxo_qpost */
171 ef10_rx_qpush, /* erxo_qpush */
172 #if EFSYS_OPT_RX_PACKED_STREAM
173 ef10_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
174 ef10_rx_qps_packet_info, /* erxo_qps_packet_info */
176 ef10_rx_qflush, /* erxo_qflush */
177 ef10_rx_qenable, /* erxo_qenable */
178 ef10_rx_qcreate, /* erxo_qcreate */
179 ef10_rx_qdestroy, /* erxo_qdestroy */
181 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
184 __checkReturn efx_rc_t
186 __inout efx_nic_t *enp)
188 const efx_rx_ops_t *erxop;
191 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
192 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
194 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
199 if (enp->en_mod_flags & EFX_MOD_RX) {
204 switch (enp->en_family) {
206 case EFX_FAMILY_SIENA:
207 erxop = &__efx_rx_siena_ops;
209 #endif /* EFSYS_OPT_SIENA */
211 #if EFSYS_OPT_HUNTINGTON
212 case EFX_FAMILY_HUNTINGTON:
213 erxop = &__efx_rx_ef10_ops;
215 #endif /* EFSYS_OPT_HUNTINGTON */
217 #if EFSYS_OPT_MEDFORD
218 case EFX_FAMILY_MEDFORD:
219 erxop = &__efx_rx_ef10_ops;
221 #endif /* EFSYS_OPT_MEDFORD */
229 if ((rc = erxop->erxo_init(enp)) != 0)
232 enp->en_erxop = erxop;
233 enp->en_mod_flags |= EFX_MOD_RX;
243 EFSYS_PROBE1(fail1, efx_rc_t, rc);
245 enp->en_erxop = NULL;
246 enp->en_mod_flags &= ~EFX_MOD_RX;
254 const efx_rx_ops_t *erxop = enp->en_erxop;
256 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
257 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
258 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
259 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
261 erxop->erxo_fini(enp);
263 enp->en_erxop = NULL;
264 enp->en_mod_flags &= ~EFX_MOD_RX;
267 #if EFSYS_OPT_RX_SCATTER
268 __checkReturn efx_rc_t
269 efx_rx_scatter_enable(
271 __in unsigned int buf_size)
273 const efx_rx_ops_t *erxop = enp->en_erxop;
276 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
277 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
279 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
285 EFSYS_PROBE1(fail1, efx_rc_t, rc);
288 #endif /* EFSYS_OPT_RX_SCATTER */
290 #if EFSYS_OPT_RX_SCALE
291 __checkReturn efx_rc_t
292 efx_rx_hash_default_support_get(
294 __out efx_rx_hash_support_t *supportp)
298 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
299 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
301 if (supportp == NULL) {
307 * Report the hashing support the client gets by default if it
308 * does not allocate an RSS context itself.
310 *supportp = enp->en_hash_support;
315 EFSYS_PROBE1(fail1, efx_rc_t, rc);
320 __checkReturn efx_rc_t
321 efx_rx_scale_default_support_get(
323 __out efx_rx_scale_context_type_t *typep)
327 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
328 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
336 * Report the RSS support the client gets by default if it
337 * does not allocate an RSS context itself.
339 *typep = enp->en_rss_context_type;
344 EFSYS_PROBE1(fail1, efx_rc_t, rc);
348 #endif /* EFSYS_OPT_RX_SCALE */
350 #if EFSYS_OPT_RX_SCALE
351 __checkReturn efx_rc_t
352 efx_rx_scale_context_alloc(
354 __in efx_rx_scale_context_type_t type,
355 __in uint32_t num_queues,
356 __out uint32_t *rss_contextp)
358 const efx_rx_ops_t *erxop = enp->en_erxop;
361 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
362 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
364 if (erxop->erxo_scale_context_alloc == NULL) {
368 if ((rc = erxop->erxo_scale_context_alloc(enp, type,
369 num_queues, rss_contextp)) != 0) {
378 EFSYS_PROBE1(fail1, efx_rc_t, rc);
381 #endif /* EFSYS_OPT_RX_SCALE */
383 #if EFSYS_OPT_RX_SCALE
384 __checkReturn efx_rc_t
385 efx_rx_scale_context_free(
387 __in uint32_t rss_context)
389 const efx_rx_ops_t *erxop = enp->en_erxop;
392 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
393 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
395 if (erxop->erxo_scale_context_free == NULL) {
399 if ((rc = erxop->erxo_scale_context_free(enp, rss_context)) != 0)
407 EFSYS_PROBE1(fail1, efx_rc_t, rc);
410 #endif /* EFSYS_OPT_RX_SCALE */
412 #if EFSYS_OPT_RX_SCALE
413 __checkReturn efx_rc_t
414 efx_rx_scale_mode_set(
416 __in uint32_t rss_context,
417 __in efx_rx_hash_alg_t alg,
418 __in efx_rx_hash_type_t type,
419 __in boolean_t insert)
421 const efx_rx_ops_t *erxop = enp->en_erxop;
424 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
425 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
427 if (erxop->erxo_scale_mode_set != NULL) {
428 if ((rc = erxop->erxo_scale_mode_set(enp, rss_context, alg,
436 EFSYS_PROBE1(fail1, efx_rc_t, rc);
439 #endif /* EFSYS_OPT_RX_SCALE */
441 #if EFSYS_OPT_RX_SCALE
442 __checkReturn efx_rc_t
443 efx_rx_scale_key_set(
445 __in uint32_t rss_context,
446 __in_ecount(n) uint8_t *key,
449 const efx_rx_ops_t *erxop = enp->en_erxop;
452 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
453 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
455 if ((rc = erxop->erxo_scale_key_set(enp, rss_context, key, n)) != 0)
461 EFSYS_PROBE1(fail1, efx_rc_t, rc);
465 #endif /* EFSYS_OPT_RX_SCALE */
467 #if EFSYS_OPT_RX_SCALE
468 __checkReturn efx_rc_t
469 efx_rx_scale_tbl_set(
471 __in uint32_t rss_context,
472 __in_ecount(n) unsigned int *table,
475 const efx_rx_ops_t *erxop = enp->en_erxop;
478 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
479 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
481 if ((rc = erxop->erxo_scale_tbl_set(enp, rss_context, table, n)) != 0)
487 EFSYS_PROBE1(fail1, efx_rc_t, rc);
491 #endif /* EFSYS_OPT_RX_SCALE */
496 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
498 __in unsigned int ndescs,
499 __in unsigned int completed,
500 __in unsigned int added)
502 efx_nic_t *enp = erp->er_enp;
503 const efx_rx_ops_t *erxop = enp->en_erxop;
505 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
507 erxop->erxo_qpost(erp, addrp, size, ndescs, completed, added);
510 #if EFSYS_OPT_RX_PACKED_STREAM
513 efx_rx_qpush_ps_credits(
516 efx_nic_t *enp = erp->er_enp;
517 const efx_rx_ops_t *erxop = enp->en_erxop;
519 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
521 erxop->erxo_qpush_ps_credits(erp);
524 __checkReturn uint8_t *
525 efx_rx_qps_packet_info(
527 __in uint8_t *buffer,
528 __in uint32_t buffer_length,
529 __in uint32_t current_offset,
530 __out uint16_t *lengthp,
531 __out uint32_t *next_offsetp,
532 __out uint32_t *timestamp)
534 efx_nic_t *enp = erp->er_enp;
535 const efx_rx_ops_t *erxop = enp->en_erxop;
537 return (erxop->erxo_qps_packet_info(erp, buffer,
538 buffer_length, current_offset, lengthp,
539 next_offsetp, timestamp));
542 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
547 __in unsigned int added,
548 __inout unsigned int *pushedp)
550 efx_nic_t *enp = erp->er_enp;
551 const efx_rx_ops_t *erxop = enp->en_erxop;
553 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
555 erxop->erxo_qpush(erp, added, pushedp);
558 __checkReturn efx_rc_t
562 efx_nic_t *enp = erp->er_enp;
563 const efx_rx_ops_t *erxop = enp->en_erxop;
566 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
568 if ((rc = erxop->erxo_qflush(erp)) != 0)
574 EFSYS_PROBE1(fail1, efx_rc_t, rc);
583 efx_nic_t *enp = erp->er_enp;
584 const efx_rx_ops_t *erxop = enp->en_erxop;
586 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
588 erxop->erxo_qenable(erp);
591 static __checkReturn efx_rc_t
592 efx_rx_qcreate_internal(
594 __in unsigned int index,
595 __in unsigned int label,
596 __in efx_rxq_type_t type,
597 __in uint32_t type_data,
598 __in efsys_mem_t *esmp,
601 __in unsigned int flags,
603 __deref_out efx_rxq_t **erpp)
605 const efx_rx_ops_t *erxop = enp->en_erxop;
609 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
610 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
612 /* Allocate an RXQ object */
613 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
620 erp->er_magic = EFX_RXQ_MAGIC;
622 erp->er_index = index;
623 erp->er_mask = ndescs - 1;
626 if ((rc = erxop->erxo_qcreate(enp, index, label, type, type_data, esmp,
627 ndescs, id, flags, eep, erp)) != 0)
638 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
640 EFSYS_PROBE1(fail1, efx_rc_t, rc);
645 __checkReturn efx_rc_t
648 __in unsigned int index,
649 __in unsigned int label,
650 __in efx_rxq_type_t type,
651 __in efsys_mem_t *esmp,
654 __in unsigned int flags,
656 __deref_out efx_rxq_t **erpp)
658 return efx_rx_qcreate_internal(enp, index, label, type, 0, esmp, ndescs,
659 id, flags, eep, erpp);
662 #if EFSYS_OPT_RX_PACKED_STREAM
664 __checkReturn efx_rc_t
665 efx_rx_qcreate_packed_stream(
667 __in unsigned int index,
668 __in unsigned int label,
669 __in uint32_t ps_buf_size,
670 __in efsys_mem_t *esmp,
673 __deref_out efx_rxq_t **erpp)
675 return efx_rx_qcreate_internal(enp, index, label,
676 EFX_RXQ_TYPE_PACKED_STREAM, ps_buf_size, esmp, ndescs,
677 0 /* id unused on EF10 */, EFX_RXQ_FLAG_NONE, eep, erpp);
686 efx_nic_t *enp = erp->er_enp;
687 const efx_rx_ops_t *erxop = enp->en_erxop;
689 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
691 erxop->erxo_qdestroy(erp);
694 __checkReturn efx_rc_t
695 efx_pseudo_hdr_pkt_length_get(
697 __in uint8_t *buffer,
698 __out uint16_t *lengthp)
700 efx_nic_t *enp = erp->er_enp;
701 const efx_rx_ops_t *erxop = enp->en_erxop;
703 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
705 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
708 #if EFSYS_OPT_RX_SCALE
709 __checkReturn uint32_t
710 efx_pseudo_hdr_hash_get(
712 __in efx_rx_hash_alg_t func,
713 __in uint8_t *buffer)
715 efx_nic_t *enp = erp->er_enp;
716 const efx_rx_ops_t *erxop = enp->en_erxop;
718 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
720 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
721 return (erxop->erxo_prefix_hash(enp, func, buffer));
723 #endif /* EFSYS_OPT_RX_SCALE */
727 static __checkReturn efx_rc_t
734 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
736 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
737 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
738 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
739 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
740 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
741 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
742 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
744 /* Zero the RSS table */
745 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
747 EFX_ZERO_OWORD(oword);
748 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
749 index, &oword, B_TRUE);
752 #if EFSYS_OPT_RX_SCALE
753 /* The RSS key and indirection table are writable. */
754 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
756 /* Hardware can insert RX hash with/without RSS */
757 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
758 #endif /* EFSYS_OPT_RX_SCALE */
763 #if EFSYS_OPT_RX_SCATTER
764 static __checkReturn efx_rc_t
765 siena_rx_scatter_enable(
767 __in unsigned int buf_size)
773 nbuf32 = buf_size / 32;
775 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
776 ((buf_size % 32) != 0)) {
781 if (enp->en_rx_qcount > 0) {
786 /* Set scatter buffer size */
787 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
788 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
789 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
791 /* Enable scatter for packets not matching a filter */
792 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
793 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
794 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
801 EFSYS_PROBE1(fail1, efx_rc_t, rc);
805 #endif /* EFSYS_OPT_RX_SCATTER */
808 #define EFX_RX_LFSR_HASH(_enp, _insert) \
812 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
813 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
814 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
815 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
816 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
817 (_insert) ? 1 : 0); \
818 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
820 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
821 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
823 EFX_SET_OWORD_FIELD(oword, \
824 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
825 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
829 _NOTE(CONSTANTCONDITION) \
832 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
836 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
837 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
838 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
840 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
842 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
843 (_insert) ? 1 : 0); \
844 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
846 _NOTE(CONSTANTCONDITION) \
849 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
853 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
854 EFX_SET_OWORD_FIELD(oword, \
855 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
856 EFX_SET_OWORD_FIELD(oword, \
857 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
858 EFX_SET_OWORD_FIELD(oword, \
859 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
860 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
864 _NOTE(CONSTANTCONDITION) \
868 #if EFSYS_OPT_RX_SCALE
870 static __checkReturn efx_rc_t
871 siena_rx_scale_mode_set(
873 __in uint32_t rss_context,
874 __in efx_rx_hash_alg_t alg,
875 __in efx_rx_hash_type_t type,
876 __in boolean_t insert)
880 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
886 case EFX_RX_HASHALG_LFSR:
887 EFX_RX_LFSR_HASH(enp, insert);
890 case EFX_RX_HASHALG_TOEPLITZ:
891 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
892 type & EFX_RX_HASH_IPV4,
893 type & EFX_RX_HASH_TCPIPV4);
895 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
896 type & EFX_RX_HASH_IPV6,
897 type & EFX_RX_HASH_TCPIPV6,
916 EFSYS_PROBE1(fail1, efx_rc_t, rc);
918 EFX_RX_LFSR_HASH(enp, B_FALSE);
924 #if EFSYS_OPT_RX_SCALE
925 static __checkReturn efx_rc_t
926 siena_rx_scale_key_set(
928 __in uint32_t rss_context,
929 __in_ecount(n) uint8_t *key,
937 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
944 /* Write Toeplitz IPv4 hash key */
945 EFX_ZERO_OWORD(oword);
946 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
947 offset > 0 && byte < n;
949 oword.eo_u8[offset - 1] = key[byte++];
951 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
955 /* Verify Toeplitz IPv4 hash key */
956 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
957 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
958 offset > 0 && byte < n;
960 if (oword.eo_u8[offset - 1] != key[byte++]) {
966 if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
971 /* Write Toeplitz IPv6 hash key 3 */
972 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
973 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
974 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
975 offset > 0 && byte < n;
977 oword.eo_u8[offset - 1] = key[byte++];
979 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
981 /* Write Toeplitz IPv6 hash key 2 */
982 EFX_ZERO_OWORD(oword);
983 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
984 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
985 offset > 0 && byte < n;
987 oword.eo_u8[offset - 1] = key[byte++];
989 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
991 /* Write Toeplitz IPv6 hash key 1 */
992 EFX_ZERO_OWORD(oword);
993 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
994 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
995 offset > 0 && byte < n;
997 oword.eo_u8[offset - 1] = key[byte++];
999 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1003 /* Verify Toeplitz IPv6 hash key 3 */
1004 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1005 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1006 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1007 offset > 0 && byte < n;
1009 if (oword.eo_u8[offset - 1] != key[byte++]) {
1015 /* Verify Toeplitz IPv6 hash key 2 */
1016 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1017 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1018 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1019 offset > 0 && byte < n;
1021 if (oword.eo_u8[offset - 1] != key[byte++]) {
1027 /* Verify Toeplitz IPv6 hash key 1 */
1028 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1029 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1030 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1031 offset > 0 && byte < n;
1033 if (oword.eo_u8[offset - 1] != key[byte++]) {
1051 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1057 #if EFSYS_OPT_RX_SCALE
1058 static __checkReturn efx_rc_t
1059 siena_rx_scale_tbl_set(
1060 __in efx_nic_t *enp,
1061 __in uint32_t rss_context,
1062 __in_ecount(n) unsigned int *table,
1069 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
1070 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
1072 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1077 if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
1082 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
1085 /* Calculate the entry to place in the table */
1086 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1088 EFSYS_PROBE2(table, int, index, uint32_t, byte);
1090 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
1092 /* Write the table */
1093 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1094 index, &oword, B_TRUE);
1097 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
1100 /* Determine if we're starting a new batch */
1101 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1103 /* Read the table */
1104 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
1105 index, &oword, B_TRUE);
1107 /* Verify the entry */
1108 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1121 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1128 * Falcon/Siena pseudo-header
1129 * --------------------------
1131 * Receive packets are prefixed by an optional 16 byte pseudo-header.
1132 * The pseudo-header is a byte array of one of the forms:
1134 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1135 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1136 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1139 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
1140 * LL.LL LFSR hash (16-bit big-endian)
1143 #if EFSYS_OPT_RX_SCALE
1144 static __checkReturn uint32_t
1145 siena_rx_prefix_hash(
1146 __in efx_nic_t *enp,
1147 __in efx_rx_hash_alg_t func,
1148 __in uint8_t *buffer)
1150 _NOTE(ARGUNUSED(enp))
1153 case EFX_RX_HASHALG_TOEPLITZ:
1154 return ((buffer[12] << 24) |
1155 (buffer[13] << 16) |
1159 case EFX_RX_HASHALG_LFSR:
1160 return ((buffer[14] << 8) | buffer[15]);
1167 #endif /* EFSYS_OPT_RX_SCALE */
1169 static __checkReturn efx_rc_t
1170 siena_rx_prefix_pktlen(
1171 __in efx_nic_t *enp,
1172 __in uint8_t *buffer,
1173 __out uint16_t *lengthp)
1175 _NOTE(ARGUNUSED(enp, buffer, lengthp))
1177 /* Not supported by Falcon/Siena hardware */
1185 __in efx_rxq_t *erp,
1186 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1188 __in unsigned int ndescs,
1189 __in unsigned int completed,
1190 __in unsigned int added)
1194 unsigned int offset;
1197 /* The client driver must not overfill the queue */
1198 EFSYS_ASSERT3U(added - completed + ndescs, <=,
1199 EFX_RXQ_LIMIT(erp->er_mask + 1));
1201 id = added & (erp->er_mask);
1202 for (i = 0; i < ndescs; i++) {
1203 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1204 unsigned int, id, efsys_dma_addr_t, addrp[i],
1207 EFX_POPULATE_QWORD_3(qword,
1208 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1209 FSF_AZ_RX_KER_BUF_ADDR_DW0,
1210 (uint32_t)(addrp[i] & 0xffffffff),
1211 FSF_AZ_RX_KER_BUF_ADDR_DW1,
1212 (uint32_t)(addrp[i] >> 32));
1214 offset = id * sizeof (efx_qword_t);
1215 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1217 id = (id + 1) & (erp->er_mask);
1223 __in efx_rxq_t *erp,
1224 __in unsigned int added,
1225 __inout unsigned int *pushedp)
1227 efx_nic_t *enp = erp->er_enp;
1228 unsigned int pushed = *pushedp;
1233 /* All descriptors are pushed */
1236 /* Push the populated descriptors out */
1237 wptr = added & erp->er_mask;
1239 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1241 /* Only write the third DWORD */
1242 EFX_POPULATE_DWORD_1(dword,
1243 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1245 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1246 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1247 wptr, pushed & erp->er_mask);
1248 EFSYS_PIO_WRITE_BARRIER();
1249 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1250 erp->er_index, &dword, B_FALSE);
1253 #if EFSYS_OPT_RX_PACKED_STREAM
1255 siena_rx_qpush_ps_credits(
1256 __in efx_rxq_t *erp)
1258 /* Not supported by Siena hardware */
1263 siena_rx_qps_packet_info(
1264 __in efx_rxq_t *erp,
1265 __in uint8_t *buffer,
1266 __in uint32_t buffer_length,
1267 __in uint32_t current_offset,
1268 __out uint16_t *lengthp,
1269 __out uint32_t *next_offsetp,
1270 __out uint32_t *timestamp)
1272 /* Not supported by Siena hardware */
1277 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1279 static __checkReturn efx_rc_t
1281 __in efx_rxq_t *erp)
1283 efx_nic_t *enp = erp->er_enp;
1287 label = erp->er_index;
1289 /* Flush the queue */
1290 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1291 FRF_AZ_RX_FLUSH_DESCQ, label);
1292 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1299 __in efx_rxq_t *erp)
1301 efx_nic_t *enp = erp->er_enp;
1304 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1306 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1307 erp->er_index, &oword, B_TRUE);
1309 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1310 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1311 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1313 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1314 erp->er_index, &oword, B_TRUE);
1317 static __checkReturn efx_rc_t
1319 __in efx_nic_t *enp,
1320 __in unsigned int index,
1321 __in unsigned int label,
1322 __in efx_rxq_type_t type,
1323 __in uint32_t type_data,
1324 __in efsys_mem_t *esmp,
1327 __in unsigned int flags,
1328 __in efx_evq_t *eep,
1329 __in efx_rxq_t *erp)
1331 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1334 boolean_t jumbo = B_FALSE;
1337 _NOTE(ARGUNUSED(esmp))
1338 _NOTE(ARGUNUSED(type_data))
1340 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1341 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1342 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1343 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1345 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1346 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1348 if (!ISP2(ndescs) ||
1349 (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
1353 if (index >= encp->enc_rxq_limit) {
1357 for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1359 if ((1 << size) == (int)(ndescs / EFX_RXQ_MINNDESCS))
1361 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1367 case EFX_RXQ_TYPE_DEFAULT:
1375 if (flags & EFX_RXQ_FLAG_SCATTER) {
1376 #if EFSYS_OPT_RX_SCATTER
1381 #endif /* EFSYS_OPT_RX_SCATTER */
1384 /* Set up the new descriptor queue */
1385 EFX_POPULATE_OWORD_7(oword,
1386 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1387 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1388 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1389 FRF_AZ_RX_DESCQ_LABEL, label,
1390 FRF_AZ_RX_DESCQ_SIZE, size,
1391 FRF_AZ_RX_DESCQ_TYPE, 0,
1392 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1394 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1395 erp->er_index, &oword, B_TRUE);
1399 #if !EFSYS_OPT_RX_SCATTER
1410 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1417 __in efx_rxq_t *erp)
1419 efx_nic_t *enp = erp->er_enp;
1422 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1423 --enp->en_rx_qcount;
1425 /* Purge descriptor queue */
1426 EFX_ZERO_OWORD(oword);
1428 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1429 erp->er_index, &oword, B_TRUE);
1431 /* Free the RXQ object */
1432 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1437 __in efx_nic_t *enp)
1439 _NOTE(ARGUNUSED(enp))
1442 #endif /* EFSYS_OPT_SIENA */