2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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37 static __checkReturn efx_rc_t
45 #if EFSYS_OPT_RX_SCATTER
46 static __checkReturn efx_rc_t
47 siena_rx_scatter_enable(
49 __in unsigned int buf_size);
50 #endif /* EFSYS_OPT_RX_SCATTER */
52 static __checkReturn efx_rc_t
53 siena_rx_prefix_pktlen(
56 __out uint16_t *lengthp);
61 __in_ecount(n) efsys_dma_addr_t *addrp,
64 __in unsigned int completed,
65 __in unsigned int added);
70 __in unsigned int added,
71 __inout unsigned int *pushedp);
73 static __checkReturn efx_rc_t
81 static __checkReturn efx_rc_t
84 __in unsigned int index,
85 __in unsigned int label,
86 __in efx_rxq_type_t type,
87 __in efsys_mem_t *esmp,
97 #endif /* EFSYS_OPT_SIENA */
101 static const efx_rx_ops_t __efx_rx_siena_ops = {
102 siena_rx_init, /* erxo_init */
103 siena_rx_fini, /* erxo_fini */
104 #if EFSYS_OPT_RX_SCATTER
105 siena_rx_scatter_enable, /* erxo_scatter_enable */
107 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
108 siena_rx_qpost, /* erxo_qpost */
109 siena_rx_qpush, /* erxo_qpush */
110 siena_rx_qflush, /* erxo_qflush */
111 siena_rx_qenable, /* erxo_qenable */
112 siena_rx_qcreate, /* erxo_qcreate */
113 siena_rx_qdestroy, /* erxo_qdestroy */
115 #endif /* EFSYS_OPT_SIENA */
117 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
118 static const efx_rx_ops_t __efx_rx_ef10_ops = {
119 ef10_rx_init, /* erxo_init */
120 ef10_rx_fini, /* erxo_fini */
121 #if EFSYS_OPT_RX_SCATTER
122 ef10_rx_scatter_enable, /* erxo_scatter_enable */
124 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
125 ef10_rx_qpost, /* erxo_qpost */
126 ef10_rx_qpush, /* erxo_qpush */
127 ef10_rx_qflush, /* erxo_qflush */
128 ef10_rx_qenable, /* erxo_qenable */
129 ef10_rx_qcreate, /* erxo_qcreate */
130 ef10_rx_qdestroy, /* erxo_qdestroy */
132 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
135 __checkReturn efx_rc_t
137 __inout efx_nic_t *enp)
139 const efx_rx_ops_t *erxop;
142 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
143 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
145 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
150 if (enp->en_mod_flags & EFX_MOD_RX) {
155 switch (enp->en_family) {
157 case EFX_FAMILY_SIENA:
158 erxop = &__efx_rx_siena_ops;
160 #endif /* EFSYS_OPT_SIENA */
162 #if EFSYS_OPT_HUNTINGTON
163 case EFX_FAMILY_HUNTINGTON:
164 erxop = &__efx_rx_ef10_ops;
166 #endif /* EFSYS_OPT_HUNTINGTON */
168 #if EFSYS_OPT_MEDFORD
169 case EFX_FAMILY_MEDFORD:
170 erxop = &__efx_rx_ef10_ops;
172 #endif /* EFSYS_OPT_MEDFORD */
180 if ((rc = erxop->erxo_init(enp)) != 0)
183 enp->en_erxop = erxop;
184 enp->en_mod_flags |= EFX_MOD_RX;
194 EFSYS_PROBE1(fail1, efx_rc_t, rc);
196 enp->en_erxop = NULL;
197 enp->en_mod_flags &= ~EFX_MOD_RX;
205 const efx_rx_ops_t *erxop = enp->en_erxop;
207 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
208 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
209 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
210 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
212 erxop->erxo_fini(enp);
214 enp->en_erxop = NULL;
215 enp->en_mod_flags &= ~EFX_MOD_RX;
218 #if EFSYS_OPT_RX_SCATTER
219 __checkReturn efx_rc_t
220 efx_rx_scatter_enable(
222 __in unsigned int buf_size)
224 const efx_rx_ops_t *erxop = enp->en_erxop;
227 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
228 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
230 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
236 EFSYS_PROBE1(fail1, efx_rc_t, rc);
239 #endif /* EFSYS_OPT_RX_SCATTER */
244 __in_ecount(n) efsys_dma_addr_t *addrp,
247 __in unsigned int completed,
248 __in unsigned int added)
250 efx_nic_t *enp = erp->er_enp;
251 const efx_rx_ops_t *erxop = enp->en_erxop;
253 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
255 erxop->erxo_qpost(erp, addrp, size, n, completed, added);
261 __in unsigned int added,
262 __inout unsigned int *pushedp)
264 efx_nic_t *enp = erp->er_enp;
265 const efx_rx_ops_t *erxop = enp->en_erxop;
267 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
269 erxop->erxo_qpush(erp, added, pushedp);
272 __checkReturn efx_rc_t
276 efx_nic_t *enp = erp->er_enp;
277 const efx_rx_ops_t *erxop = enp->en_erxop;
280 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
282 if ((rc = erxop->erxo_qflush(erp)) != 0)
288 EFSYS_PROBE1(fail1, efx_rc_t, rc);
297 efx_nic_t *enp = erp->er_enp;
298 const efx_rx_ops_t *erxop = enp->en_erxop;
300 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
302 erxop->erxo_qenable(erp);
305 __checkReturn efx_rc_t
308 __in unsigned int index,
309 __in unsigned int label,
310 __in efx_rxq_type_t type,
311 __in efsys_mem_t *esmp,
315 __deref_out efx_rxq_t **erpp)
317 const efx_rx_ops_t *erxop = enp->en_erxop;
321 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
322 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
324 /* Allocate an RXQ object */
325 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
332 erp->er_magic = EFX_RXQ_MAGIC;
334 erp->er_index = index;
335 erp->er_mask = n - 1;
338 if ((rc = erxop->erxo_qcreate(enp, index, label, type, esmp, n, id,
350 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
352 EFSYS_PROBE1(fail1, efx_rc_t, rc);
361 efx_nic_t *enp = erp->er_enp;
362 const efx_rx_ops_t *erxop = enp->en_erxop;
364 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
366 erxop->erxo_qdestroy(erp);
369 __checkReturn efx_rc_t
370 efx_pseudo_hdr_pkt_length_get(
372 __in uint8_t *buffer,
373 __out uint16_t *lengthp)
375 efx_nic_t *enp = erp->er_enp;
376 const efx_rx_ops_t *erxop = enp->en_erxop;
378 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
380 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
385 static __checkReturn efx_rc_t
392 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
394 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
395 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
396 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
397 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
398 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
399 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
400 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
402 /* Zero the RSS table */
403 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
405 EFX_ZERO_OWORD(oword);
406 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
407 index, &oword, B_TRUE);
413 #if EFSYS_OPT_RX_SCATTER
414 static __checkReturn efx_rc_t
415 siena_rx_scatter_enable(
417 __in unsigned int buf_size)
423 nbuf32 = buf_size / 32;
425 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
426 ((buf_size % 32) != 0)) {
431 if (enp->en_rx_qcount > 0) {
436 /* Set scatter buffer size */
437 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
438 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
439 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
441 /* Enable scatter for packets not matching a filter */
442 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
443 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
444 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
451 EFSYS_PROBE1(fail1, efx_rc_t, rc);
455 #endif /* EFSYS_OPT_RX_SCATTER */
458 #define EFX_RX_LFSR_HASH(_enp, _insert) \
462 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
463 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
464 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
465 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
466 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
467 (_insert) ? 1 : 0); \
468 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
470 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
471 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
473 EFX_SET_OWORD_FIELD(oword, \
474 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
475 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
479 _NOTE(CONSTANTCONDITION) \
482 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
486 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
487 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
488 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
490 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
492 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
493 (_insert) ? 1 : 0); \
494 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
496 _NOTE(CONSTANTCONDITION) \
499 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
503 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
504 EFX_SET_OWORD_FIELD(oword, \
505 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
506 EFX_SET_OWORD_FIELD(oword, \
507 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
508 EFX_SET_OWORD_FIELD(oword, \
509 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
510 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
514 _NOTE(CONSTANTCONDITION) \
519 * Falcon/Siena pseudo-header
520 * --------------------------
522 * Receive packets are prefixed by an optional 16 byte pseudo-header.
523 * The pseudo-header is a byte array of one of the forms:
525 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
526 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
527 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
530 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
531 * LL.LL LFSR hash (16-bit big-endian)
534 static __checkReturn efx_rc_t
535 siena_rx_prefix_pktlen(
537 __in uint8_t *buffer,
538 __out uint16_t *lengthp)
540 _NOTE(ARGUNUSED(enp, buffer, lengthp))
542 /* Not supported by Falcon/Siena hardware */
551 __in_ecount(n) efsys_dma_addr_t *addrp,
554 __in unsigned int completed,
555 __in unsigned int added)
562 /* The client driver must not overfill the queue */
563 EFSYS_ASSERT3U(added - completed + n, <=,
564 EFX_RXQ_LIMIT(erp->er_mask + 1));
566 id = added & (erp->er_mask);
567 for (i = 0; i < n; i++) {
568 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
569 unsigned int, id, efsys_dma_addr_t, addrp[i],
572 EFX_POPULATE_QWORD_3(qword,
573 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
574 FSF_AZ_RX_KER_BUF_ADDR_DW0,
575 (uint32_t)(addrp[i] & 0xffffffff),
576 FSF_AZ_RX_KER_BUF_ADDR_DW1,
577 (uint32_t)(addrp[i] >> 32));
579 offset = id * sizeof (efx_qword_t);
580 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
582 id = (id + 1) & (erp->er_mask);
589 __in unsigned int added,
590 __inout unsigned int *pushedp)
592 efx_nic_t *enp = erp->er_enp;
593 unsigned int pushed = *pushedp;
598 /* All descriptors are pushed */
601 /* Push the populated descriptors out */
602 wptr = added & erp->er_mask;
604 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
606 /* Only write the third DWORD */
607 EFX_POPULATE_DWORD_1(dword,
608 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
610 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
611 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
612 wptr, pushed & erp->er_mask);
613 EFSYS_PIO_WRITE_BARRIER();
614 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
615 erp->er_index, &dword, B_FALSE);
618 static __checkReturn efx_rc_t
622 efx_nic_t *enp = erp->er_enp;
626 label = erp->er_index;
628 /* Flush the queue */
629 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
630 FRF_AZ_RX_FLUSH_DESCQ, label);
631 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
640 efx_nic_t *enp = erp->er_enp;
643 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
645 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
646 erp->er_index, &oword, B_TRUE);
648 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
649 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
650 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
652 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
653 erp->er_index, &oword, B_TRUE);
656 static __checkReturn efx_rc_t
659 __in unsigned int index,
660 __in unsigned int label,
661 __in efx_rxq_type_t type,
662 __in efsys_mem_t *esmp,
668 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
674 _NOTE(ARGUNUSED(esmp))
676 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
677 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
678 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
679 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
681 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
682 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
684 if (!ISP2(n) || (n < EFX_RXQ_MINNDESCS) || (n > EFX_RXQ_MAXNDESCS)) {
688 if (index >= encp->enc_rxq_limit) {
692 for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
694 if ((1 << size) == (int)(n / EFX_RXQ_MINNDESCS))
696 if (id + (1 << size) >= encp->enc_buftbl_limit) {
702 case EFX_RXQ_TYPE_DEFAULT:
706 #if EFSYS_OPT_RX_SCATTER
707 case EFX_RXQ_TYPE_SCATTER:
708 if (enp->en_family < EFX_FAMILY_SIENA) {
714 #endif /* EFSYS_OPT_RX_SCATTER */
721 /* Set up the new descriptor queue */
722 EFX_POPULATE_OWORD_7(oword,
723 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
724 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
725 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
726 FRF_AZ_RX_DESCQ_LABEL, label,
727 FRF_AZ_RX_DESCQ_SIZE, size,
728 FRF_AZ_RX_DESCQ_TYPE, 0,
729 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
731 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
732 erp->er_index, &oword, B_TRUE);
743 EFSYS_PROBE1(fail1, efx_rc_t, rc);
752 efx_nic_t *enp = erp->er_enp;
755 EFSYS_ASSERT(enp->en_rx_qcount != 0);
758 /* Purge descriptor queue */
759 EFX_ZERO_OWORD(oword);
761 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
762 erp->er_index, &oword, B_TRUE);
764 /* Free the RXQ object */
765 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
772 _NOTE(ARGUNUSED(enp))
775 #endif /* EFSYS_OPT_SIENA */