1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
13 static __checkReturn efx_rc_t
21 #if EFSYS_OPT_RX_SCATTER
22 static __checkReturn efx_rc_t
23 siena_rx_scatter_enable(
25 __in unsigned int buf_size);
26 #endif /* EFSYS_OPT_RX_SCATTER */
28 #if EFSYS_OPT_RX_SCALE
29 static __checkReturn efx_rc_t
30 siena_rx_scale_mode_set(
32 __in uint32_t rss_context,
33 __in efx_rx_hash_alg_t alg,
34 __in efx_rx_hash_type_t type,
35 __in boolean_t insert);
37 static __checkReturn efx_rc_t
38 siena_rx_scale_key_set(
40 __in uint32_t rss_context,
41 __in_ecount(n) uint8_t *key,
44 static __checkReturn efx_rc_t
45 siena_rx_scale_tbl_set(
47 __in uint32_t rss_context,
48 __in_ecount(n) unsigned int *table,
51 static __checkReturn uint32_t
54 __in efx_rx_hash_alg_t func,
55 __in uint8_t *buffer);
57 #endif /* EFSYS_OPT_RX_SCALE */
59 static __checkReturn efx_rc_t
60 siena_rx_prefix_pktlen(
63 __out uint16_t *lengthp);
68 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
70 __in unsigned int ndescs,
71 __in unsigned int completed,
72 __in unsigned int added);
77 __in unsigned int added,
78 __inout unsigned int *pushedp);
80 #if EFSYS_OPT_RX_PACKED_STREAM
82 siena_rx_qpush_ps_credits(
85 static __checkReturn uint8_t *
86 siena_rx_qps_packet_info(
89 __in uint32_t buffer_length,
90 __in uint32_t current_offset,
91 __out uint16_t *lengthp,
92 __out uint32_t *next_offsetp,
93 __out uint32_t *timestamp);
96 static __checkReturn efx_rc_t
102 __in efx_rxq_t *erp);
104 static __checkReturn efx_rc_t
107 __in unsigned int index,
108 __in unsigned int label,
109 __in efx_rxq_type_t type,
110 __in_opt const efx_rxq_type_data_t *type_data,
111 __in efsys_mem_t *esmp,
114 __in unsigned int flags,
116 __in efx_rxq_t *erp);
120 __in efx_rxq_t *erp);
122 #endif /* EFSYS_OPT_SIENA */
126 static const efx_rx_ops_t __efx_rx_siena_ops = {
127 siena_rx_init, /* erxo_init */
128 siena_rx_fini, /* erxo_fini */
129 #if EFSYS_OPT_RX_SCATTER
130 siena_rx_scatter_enable, /* erxo_scatter_enable */
132 #if EFSYS_OPT_RX_SCALE
133 NULL, /* erxo_scale_context_alloc */
134 NULL, /* erxo_scale_context_free */
135 siena_rx_scale_mode_set, /* erxo_scale_mode_set */
136 siena_rx_scale_key_set, /* erxo_scale_key_set */
137 siena_rx_scale_tbl_set, /* erxo_scale_tbl_set */
138 siena_rx_prefix_hash, /* erxo_prefix_hash */
140 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
141 siena_rx_qpost, /* erxo_qpost */
142 siena_rx_qpush, /* erxo_qpush */
143 #if EFSYS_OPT_RX_PACKED_STREAM
144 siena_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
145 siena_rx_qps_packet_info, /* erxo_qps_packet_info */
147 siena_rx_qflush, /* erxo_qflush */
148 siena_rx_qenable, /* erxo_qenable */
149 siena_rx_qcreate, /* erxo_qcreate */
150 siena_rx_qdestroy, /* erxo_qdestroy */
152 #endif /* EFSYS_OPT_SIENA */
154 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
155 static const efx_rx_ops_t __efx_rx_ef10_ops = {
156 ef10_rx_init, /* erxo_init */
157 ef10_rx_fini, /* erxo_fini */
158 #if EFSYS_OPT_RX_SCATTER
159 ef10_rx_scatter_enable, /* erxo_scatter_enable */
161 #if EFSYS_OPT_RX_SCALE
162 ef10_rx_scale_context_alloc, /* erxo_scale_context_alloc */
163 ef10_rx_scale_context_free, /* erxo_scale_context_free */
164 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */
165 ef10_rx_scale_key_set, /* erxo_scale_key_set */
166 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */
167 ef10_rx_prefix_hash, /* erxo_prefix_hash */
169 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
170 ef10_rx_qpost, /* erxo_qpost */
171 ef10_rx_qpush, /* erxo_qpush */
172 #if EFSYS_OPT_RX_PACKED_STREAM
173 ef10_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
174 ef10_rx_qps_packet_info, /* erxo_qps_packet_info */
176 ef10_rx_qflush, /* erxo_qflush */
177 ef10_rx_qenable, /* erxo_qenable */
178 ef10_rx_qcreate, /* erxo_qcreate */
179 ef10_rx_qdestroy, /* erxo_qdestroy */
181 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
184 __checkReturn efx_rc_t
186 __inout efx_nic_t *enp)
188 const efx_rx_ops_t *erxop;
191 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
192 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
194 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
199 if (enp->en_mod_flags & EFX_MOD_RX) {
204 switch (enp->en_family) {
206 case EFX_FAMILY_SIENA:
207 erxop = &__efx_rx_siena_ops;
209 #endif /* EFSYS_OPT_SIENA */
211 #if EFSYS_OPT_HUNTINGTON
212 case EFX_FAMILY_HUNTINGTON:
213 erxop = &__efx_rx_ef10_ops;
215 #endif /* EFSYS_OPT_HUNTINGTON */
217 #if EFSYS_OPT_MEDFORD
218 case EFX_FAMILY_MEDFORD:
219 erxop = &__efx_rx_ef10_ops;
221 #endif /* EFSYS_OPT_MEDFORD */
223 #if EFSYS_OPT_MEDFORD2
224 case EFX_FAMILY_MEDFORD2:
225 erxop = &__efx_rx_ef10_ops;
227 #endif /* EFSYS_OPT_MEDFORD2 */
235 if ((rc = erxop->erxo_init(enp)) != 0)
238 enp->en_erxop = erxop;
239 enp->en_mod_flags |= EFX_MOD_RX;
249 EFSYS_PROBE1(fail1, efx_rc_t, rc);
251 enp->en_erxop = NULL;
252 enp->en_mod_flags &= ~EFX_MOD_RX;
260 const efx_rx_ops_t *erxop = enp->en_erxop;
262 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
263 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
264 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
265 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
267 erxop->erxo_fini(enp);
269 enp->en_erxop = NULL;
270 enp->en_mod_flags &= ~EFX_MOD_RX;
273 #if EFSYS_OPT_RX_SCATTER
274 __checkReturn efx_rc_t
275 efx_rx_scatter_enable(
277 __in unsigned int buf_size)
279 const efx_rx_ops_t *erxop = enp->en_erxop;
282 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
283 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
285 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
291 EFSYS_PROBE1(fail1, efx_rc_t, rc);
294 #endif /* EFSYS_OPT_RX_SCATTER */
296 #if EFSYS_OPT_RX_SCALE
297 __checkReturn efx_rc_t
298 efx_rx_scale_hash_flags_get(
300 __in efx_rx_hash_alg_t hash_alg,
301 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
302 __in unsigned int max_nflags,
303 __out unsigned int *nflagsp)
305 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
306 unsigned int nflags = 0;
309 if (flagsp == NULL || nflagsp == NULL) {
314 if ((encp->enc_rx_scale_hash_alg_mask & (1U << hash_alg)) == 0) {
319 /* Helper to add flags word to flags array without buffer overflow */
320 #define INSERT_FLAGS(_flags) \
322 if (nflags >= max_nflags) { \
326 *(flagsp + nflags) = (_flags); \
329 _NOTE(CONSTANTCONDITION) \
332 if (encp->enc_rx_scale_l4_hash_supported != B_FALSE) {
333 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 4TUPLE));
334 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 4TUPLE));
337 if ((encp->enc_rx_scale_l4_hash_supported != B_FALSE) &&
338 (encp->enc_rx_scale_additional_modes_supported != B_FALSE)) {
339 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE_DST));
340 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE_SRC));
342 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE_DST));
343 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE_SRC));
345 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 4TUPLE));
346 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE_DST));
347 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE_SRC));
349 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 4TUPLE));
350 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE_DST));
351 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE_SRC));
354 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE));
355 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE));
357 INSERT_FLAGS(EFX_RX_HASH(IPV4, 2TUPLE));
358 INSERT_FLAGS(EFX_RX_HASH(IPV6, 2TUPLE));
360 if (encp->enc_rx_scale_additional_modes_supported != B_FALSE) {
361 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 1TUPLE_DST));
362 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 1TUPLE_SRC));
364 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 1TUPLE_DST));
365 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 1TUPLE_SRC));
367 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE));
368 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 1TUPLE_DST));
369 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 1TUPLE_SRC));
371 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE));
372 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 1TUPLE_DST));
373 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 1TUPLE_SRC));
375 INSERT_FLAGS(EFX_RX_HASH(IPV4, 1TUPLE_DST));
376 INSERT_FLAGS(EFX_RX_HASH(IPV4, 1TUPLE_SRC));
378 INSERT_FLAGS(EFX_RX_HASH(IPV6, 1TUPLE_DST));
379 INSERT_FLAGS(EFX_RX_HASH(IPV6, 1TUPLE_SRC));
382 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, DISABLE));
383 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, DISABLE));
385 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, DISABLE));
386 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, DISABLE));
388 INSERT_FLAGS(EFX_RX_HASH(IPV4, DISABLE));
389 INSERT_FLAGS(EFX_RX_HASH(IPV6, DISABLE));
400 EFSYS_PROBE1(fail1, efx_rc_t, rc);
405 __checkReturn efx_rc_t
406 efx_rx_hash_default_support_get(
408 __out efx_rx_hash_support_t *supportp)
412 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
413 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
415 if (supportp == NULL) {
421 * Report the hashing support the client gets by default if it
422 * does not allocate an RSS context itself.
424 *supportp = enp->en_hash_support;
429 EFSYS_PROBE1(fail1, efx_rc_t, rc);
434 __checkReturn efx_rc_t
435 efx_rx_scale_default_support_get(
437 __out efx_rx_scale_context_type_t *typep)
441 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
442 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
450 * Report the RSS support the client gets by default if it
451 * does not allocate an RSS context itself.
453 *typep = enp->en_rss_context_type;
458 EFSYS_PROBE1(fail1, efx_rc_t, rc);
462 #endif /* EFSYS_OPT_RX_SCALE */
464 #if EFSYS_OPT_RX_SCALE
465 __checkReturn efx_rc_t
466 efx_rx_scale_context_alloc(
468 __in efx_rx_scale_context_type_t type,
469 __in uint32_t num_queues,
470 __out uint32_t *rss_contextp)
472 const efx_rx_ops_t *erxop = enp->en_erxop;
475 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
476 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
478 if (erxop->erxo_scale_context_alloc == NULL) {
482 if ((rc = erxop->erxo_scale_context_alloc(enp, type,
483 num_queues, rss_contextp)) != 0) {
492 EFSYS_PROBE1(fail1, efx_rc_t, rc);
495 #endif /* EFSYS_OPT_RX_SCALE */
497 #if EFSYS_OPT_RX_SCALE
498 __checkReturn efx_rc_t
499 efx_rx_scale_context_free(
501 __in uint32_t rss_context)
503 const efx_rx_ops_t *erxop = enp->en_erxop;
506 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
507 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
509 if (erxop->erxo_scale_context_free == NULL) {
513 if ((rc = erxop->erxo_scale_context_free(enp, rss_context)) != 0)
521 EFSYS_PROBE1(fail1, efx_rc_t, rc);
524 #endif /* EFSYS_OPT_RX_SCALE */
526 #if EFSYS_OPT_RX_SCALE
527 __checkReturn efx_rc_t
528 efx_rx_scale_mode_set(
530 __in uint32_t rss_context,
531 __in efx_rx_hash_alg_t alg,
532 __in efx_rx_hash_type_t type,
533 __in boolean_t insert)
535 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
536 const efx_rx_ops_t *erxop = enp->en_erxop;
537 efx_rx_hash_type_t type_check;
541 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
542 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
545 * Legacy flags and modern bits cannot be
546 * used at the same time in the hash type.
548 if ((type & EFX_RX_HASH_LEGACY_MASK) &&
549 (type & ~EFX_RX_HASH_LEGACY_MASK)) {
555 * If RSS hash type is represented by additional bits
556 * in the value, the latter need to be verified since
557 * not all bit combinations are valid RSS modes. Also,
558 * depending on the firmware, some valid combinations
559 * may be unsupported. Discern additional bits in the
560 * type value and try to recognise valid combinations.
561 * If some bits remain unrecognised, report the error.
563 type_check = type & ~EFX_RX_HASH_LEGACY_MASK;
564 if (type_check != 0) {
565 unsigned int type_flags[EFX_RX_HASH_NFLAGS];
566 unsigned int type_nflags;
568 rc = efx_rx_scale_hash_flags_get(enp, alg, type_flags,
569 EFX_ARRAY_SIZE(type_flags), &type_nflags);
573 for (i = 0; i < type_nflags; ++i) {
574 if ((type_check & type_flags[i]) == type_flags[i])
575 type_check &= ~(type_flags[i]);
578 if (type_check != 0) {
585 * Translate EFX_RX_HASH() flags to their legacy counterparts
586 * provided that the FW claims no support for additional modes.
588 if (encp->enc_rx_scale_additional_modes_supported == B_FALSE) {
589 efx_rx_hash_type_t t_ipv4 = EFX_RX_HASH(IPV4, 2TUPLE) |
590 EFX_RX_HASH(IPV4_TCP, 2TUPLE);
591 efx_rx_hash_type_t t_ipv6 = EFX_RX_HASH(IPV6, 2TUPLE) |
592 EFX_RX_HASH(IPV6_TCP, 2TUPLE);
593 efx_rx_hash_type_t t_ipv4_tcp = EFX_RX_HASH(IPV4_TCP, 4TUPLE);
594 efx_rx_hash_type_t t_ipv6_tcp = EFX_RX_HASH(IPV6_TCP, 4TUPLE);
596 if ((type & t_ipv4) == t_ipv4)
597 type |= EFX_RX_HASH_IPV4;
598 if ((type & t_ipv6) == t_ipv6)
599 type |= EFX_RX_HASH_IPV6;
601 if (encp->enc_rx_scale_l4_hash_supported == B_TRUE) {
602 if ((type & t_ipv4_tcp) == t_ipv4_tcp)
603 type |= EFX_RX_HASH_TCPIPV4;
604 if ((type & t_ipv6_tcp) == t_ipv6_tcp)
605 type |= EFX_RX_HASH_TCPIPV6;
608 type &= EFX_RX_HASH_LEGACY_MASK;
611 if (erxop->erxo_scale_mode_set != NULL) {
612 if ((rc = erxop->erxo_scale_mode_set(enp, rss_context, alg,
626 EFSYS_PROBE1(fail1, efx_rc_t, rc);
629 #endif /* EFSYS_OPT_RX_SCALE */
631 #if EFSYS_OPT_RX_SCALE
632 __checkReturn efx_rc_t
633 efx_rx_scale_key_set(
635 __in uint32_t rss_context,
636 __in_ecount(n) uint8_t *key,
639 const efx_rx_ops_t *erxop = enp->en_erxop;
642 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
643 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
645 if ((rc = erxop->erxo_scale_key_set(enp, rss_context, key, n)) != 0)
651 EFSYS_PROBE1(fail1, efx_rc_t, rc);
655 #endif /* EFSYS_OPT_RX_SCALE */
657 #if EFSYS_OPT_RX_SCALE
658 __checkReturn efx_rc_t
659 efx_rx_scale_tbl_set(
661 __in uint32_t rss_context,
662 __in_ecount(n) unsigned int *table,
665 const efx_rx_ops_t *erxop = enp->en_erxop;
668 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
669 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
671 if ((rc = erxop->erxo_scale_tbl_set(enp, rss_context, table, n)) != 0)
677 EFSYS_PROBE1(fail1, efx_rc_t, rc);
681 #endif /* EFSYS_OPT_RX_SCALE */
686 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
688 __in unsigned int ndescs,
689 __in unsigned int completed,
690 __in unsigned int added)
692 efx_nic_t *enp = erp->er_enp;
693 const efx_rx_ops_t *erxop = enp->en_erxop;
695 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
697 erxop->erxo_qpost(erp, addrp, size, ndescs, completed, added);
700 #if EFSYS_OPT_RX_PACKED_STREAM
703 efx_rx_qpush_ps_credits(
706 efx_nic_t *enp = erp->er_enp;
707 const efx_rx_ops_t *erxop = enp->en_erxop;
709 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
711 erxop->erxo_qpush_ps_credits(erp);
714 __checkReturn uint8_t *
715 efx_rx_qps_packet_info(
717 __in uint8_t *buffer,
718 __in uint32_t buffer_length,
719 __in uint32_t current_offset,
720 __out uint16_t *lengthp,
721 __out uint32_t *next_offsetp,
722 __out uint32_t *timestamp)
724 efx_nic_t *enp = erp->er_enp;
725 const efx_rx_ops_t *erxop = enp->en_erxop;
727 return (erxop->erxo_qps_packet_info(erp, buffer,
728 buffer_length, current_offset, lengthp,
729 next_offsetp, timestamp));
732 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
737 __in unsigned int added,
738 __inout unsigned int *pushedp)
740 efx_nic_t *enp = erp->er_enp;
741 const efx_rx_ops_t *erxop = enp->en_erxop;
743 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
745 erxop->erxo_qpush(erp, added, pushedp);
748 __checkReturn efx_rc_t
752 efx_nic_t *enp = erp->er_enp;
753 const efx_rx_ops_t *erxop = enp->en_erxop;
756 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
758 if ((rc = erxop->erxo_qflush(erp)) != 0)
764 EFSYS_PROBE1(fail1, efx_rc_t, rc);
773 efx_nic_t *enp = erp->er_enp;
774 const efx_rx_ops_t *erxop = enp->en_erxop;
776 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
778 erxop->erxo_qenable(erp);
781 static __checkReturn efx_rc_t
782 efx_rx_qcreate_internal(
784 __in unsigned int index,
785 __in unsigned int label,
786 __in efx_rxq_type_t type,
787 __in_opt const efx_rxq_type_data_t *type_data,
788 __in efsys_mem_t *esmp,
791 __in unsigned int flags,
793 __deref_out efx_rxq_t **erpp)
795 const efx_rx_ops_t *erxop = enp->en_erxop;
797 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
800 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
801 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
803 EFSYS_ASSERT(ISP2(encp->enc_rxq_max_ndescs));
804 EFSYS_ASSERT(ISP2(encp->enc_rxq_min_ndescs));
807 ndescs < encp->enc_rxq_min_ndescs ||
808 ndescs > encp->enc_rxq_max_ndescs) {
813 /* Allocate an RXQ object */
814 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
821 erp->er_magic = EFX_RXQ_MAGIC;
823 erp->er_index = index;
824 erp->er_mask = ndescs - 1;
827 if ((rc = erxop->erxo_qcreate(enp, index, label, type, type_data, esmp,
828 ndescs, id, flags, eep, erp)) != 0)
839 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
843 EFSYS_PROBE1(fail1, efx_rc_t, rc);
848 __checkReturn efx_rc_t
851 __in unsigned int index,
852 __in unsigned int label,
853 __in efx_rxq_type_t type,
854 __in efsys_mem_t *esmp,
857 __in unsigned int flags,
859 __deref_out efx_rxq_t **erpp)
861 return efx_rx_qcreate_internal(enp, index, label, type, NULL,
862 esmp, ndescs, id, flags, eep, erpp);
865 #if EFSYS_OPT_RX_PACKED_STREAM
867 __checkReturn efx_rc_t
868 efx_rx_qcreate_packed_stream(
870 __in unsigned int index,
871 __in unsigned int label,
872 __in uint32_t ps_buf_size,
873 __in efsys_mem_t *esmp,
876 __deref_out efx_rxq_t **erpp)
878 efx_rxq_type_data_t type_data;
880 memset(&type_data, 0, sizeof (type_data));
882 type_data.ertd_packed_stream.eps_buf_size = ps_buf_size;
884 return efx_rx_qcreate_internal(enp, index, label,
885 EFX_RXQ_TYPE_PACKED_STREAM, &type_data, esmp, ndescs,
886 0 /* id unused on EF10 */, EFX_RXQ_FLAG_NONE, eep, erpp);
891 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
893 __checkReturn efx_rc_t
894 efx_rx_qcreate_es_super_buffer(
896 __in unsigned int index,
897 __in unsigned int label,
898 __in uint32_t n_bufs_per_desc,
899 __in uint32_t max_dma_len,
900 __in uint32_t buf_stride,
901 __in uint32_t hol_block_timeout,
902 __in efsys_mem_t *esmp,
904 __in unsigned int flags,
906 __deref_out efx_rxq_t **erpp)
909 efx_rxq_type_data_t type_data;
911 if (hol_block_timeout > EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX) {
916 memset(&type_data, 0, sizeof (type_data));
918 type_data.ertd_es_super_buffer.eessb_bufs_per_desc = n_bufs_per_desc;
919 type_data.ertd_es_super_buffer.eessb_max_dma_len = max_dma_len;
920 type_data.ertd_es_super_buffer.eessb_buf_stride = buf_stride;
921 type_data.ertd_es_super_buffer.eessb_hol_block_timeout =
924 rc = efx_rx_qcreate_internal(enp, index, label,
925 EFX_RXQ_TYPE_ES_SUPER_BUFFER, &type_data, esmp, ndescs,
926 0 /* id unused on EF10 */, flags, eep, erpp);
935 EFSYS_PROBE1(fail1, efx_rc_t, rc);
947 efx_nic_t *enp = erp->er_enp;
948 const efx_rx_ops_t *erxop = enp->en_erxop;
950 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
952 erxop->erxo_qdestroy(erp);
955 __checkReturn efx_rc_t
956 efx_pseudo_hdr_pkt_length_get(
958 __in uint8_t *buffer,
959 __out uint16_t *lengthp)
961 efx_nic_t *enp = erp->er_enp;
962 const efx_rx_ops_t *erxop = enp->en_erxop;
964 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
966 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
969 #if EFSYS_OPT_RX_SCALE
970 __checkReturn uint32_t
971 efx_pseudo_hdr_hash_get(
973 __in efx_rx_hash_alg_t func,
974 __in uint8_t *buffer)
976 efx_nic_t *enp = erp->er_enp;
977 const efx_rx_ops_t *erxop = enp->en_erxop;
979 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
981 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
982 return (erxop->erxo_prefix_hash(enp, func, buffer));
984 #endif /* EFSYS_OPT_RX_SCALE */
988 static __checkReturn efx_rc_t
995 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
997 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
998 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
999 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
1000 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
1001 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
1002 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
1003 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
1005 /* Zero the RSS table */
1006 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
1008 EFX_ZERO_OWORD(oword);
1009 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1010 index, &oword, B_TRUE);
1013 #if EFSYS_OPT_RX_SCALE
1014 /* The RSS key and indirection table are writable. */
1015 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
1017 /* Hardware can insert RX hash with/without RSS */
1018 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
1019 #endif /* EFSYS_OPT_RX_SCALE */
1024 #if EFSYS_OPT_RX_SCATTER
1025 static __checkReturn efx_rc_t
1026 siena_rx_scatter_enable(
1027 __in efx_nic_t *enp,
1028 __in unsigned int buf_size)
1030 unsigned int nbuf32;
1034 nbuf32 = buf_size / 32;
1035 if ((nbuf32 == 0) ||
1036 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
1037 ((buf_size % 32) != 0)) {
1042 if (enp->en_rx_qcount > 0) {
1047 /* Set scatter buffer size */
1048 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
1049 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
1050 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
1052 /* Enable scatter for packets not matching a filter */
1053 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
1054 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
1055 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
1062 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1066 #endif /* EFSYS_OPT_RX_SCATTER */
1069 #define EFX_RX_LFSR_HASH(_enp, _insert) \
1071 efx_oword_t oword; \
1073 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1074 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
1075 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
1076 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
1077 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
1078 (_insert) ? 1 : 0); \
1079 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1081 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
1082 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
1084 EFX_SET_OWORD_FIELD(oword, \
1085 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
1086 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
1090 _NOTE(CONSTANTCONDITION) \
1093 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
1095 efx_oword_t oword; \
1097 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1098 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
1099 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
1101 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
1103 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
1104 (_insert) ? 1 : 0); \
1105 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1107 _NOTE(CONSTANTCONDITION) \
1110 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
1112 efx_oword_t oword; \
1114 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1115 EFX_SET_OWORD_FIELD(oword, \
1116 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
1117 EFX_SET_OWORD_FIELD(oword, \
1118 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
1119 EFX_SET_OWORD_FIELD(oword, \
1120 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
1121 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1125 _NOTE(CONSTANTCONDITION) \
1129 #if EFSYS_OPT_RX_SCALE
1131 static __checkReturn efx_rc_t
1132 siena_rx_scale_mode_set(
1133 __in efx_nic_t *enp,
1134 __in uint32_t rss_context,
1135 __in efx_rx_hash_alg_t alg,
1136 __in efx_rx_hash_type_t type,
1137 __in boolean_t insert)
1141 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1147 case EFX_RX_HASHALG_LFSR:
1148 EFX_RX_LFSR_HASH(enp, insert);
1151 case EFX_RX_HASHALG_TOEPLITZ:
1152 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
1153 (type & EFX_RX_HASH_IPV4) ? B_TRUE : B_FALSE,
1154 (type & EFX_RX_HASH_TCPIPV4) ? B_TRUE : B_FALSE);
1156 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
1157 (type & EFX_RX_HASH_IPV6) ? B_TRUE : B_FALSE,
1158 (type & EFX_RX_HASH_TCPIPV6) ? B_TRUE : B_FALSE,
1177 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1179 EFX_RX_LFSR_HASH(enp, B_FALSE);
1185 #if EFSYS_OPT_RX_SCALE
1186 static __checkReturn efx_rc_t
1187 siena_rx_scale_key_set(
1188 __in efx_nic_t *enp,
1189 __in uint32_t rss_context,
1190 __in_ecount(n) uint8_t *key,
1195 unsigned int offset;
1198 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1205 /* Write Toeplitz IPv4 hash key */
1206 EFX_ZERO_OWORD(oword);
1207 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1208 offset > 0 && byte < n;
1210 oword.eo_u8[offset - 1] = key[byte++];
1212 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1216 /* Verify Toeplitz IPv4 hash key */
1217 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1218 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1219 offset > 0 && byte < n;
1221 if (oword.eo_u8[offset - 1] != key[byte++]) {
1227 if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
1232 /* Write Toeplitz IPv6 hash key 3 */
1233 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1234 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1235 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1236 offset > 0 && byte < n;
1238 oword.eo_u8[offset - 1] = key[byte++];
1240 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1242 /* Write Toeplitz IPv6 hash key 2 */
1243 EFX_ZERO_OWORD(oword);
1244 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1245 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1246 offset > 0 && byte < n;
1248 oword.eo_u8[offset - 1] = key[byte++];
1250 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1252 /* Write Toeplitz IPv6 hash key 1 */
1253 EFX_ZERO_OWORD(oword);
1254 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1255 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1256 offset > 0 && byte < n;
1258 oword.eo_u8[offset - 1] = key[byte++];
1260 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1264 /* Verify Toeplitz IPv6 hash key 3 */
1265 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1266 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1267 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1268 offset > 0 && byte < n;
1270 if (oword.eo_u8[offset - 1] != key[byte++]) {
1276 /* Verify Toeplitz IPv6 hash key 2 */
1277 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1278 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1279 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1280 offset > 0 && byte < n;
1282 if (oword.eo_u8[offset - 1] != key[byte++]) {
1288 /* Verify Toeplitz IPv6 hash key 1 */
1289 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1290 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1291 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1292 offset > 0 && byte < n;
1294 if (oword.eo_u8[offset - 1] != key[byte++]) {
1312 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1318 #if EFSYS_OPT_RX_SCALE
1319 static __checkReturn efx_rc_t
1320 siena_rx_scale_tbl_set(
1321 __in efx_nic_t *enp,
1322 __in uint32_t rss_context,
1323 __in_ecount(n) unsigned int *table,
1330 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
1331 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
1333 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1338 if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
1343 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
1346 /* Calculate the entry to place in the table */
1347 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1349 EFSYS_PROBE2(table, int, index, uint32_t, byte);
1351 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
1353 /* Write the table */
1354 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1355 index, &oword, B_TRUE);
1358 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
1361 /* Determine if we're starting a new batch */
1362 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1364 /* Read the table */
1365 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
1366 index, &oword, B_TRUE);
1368 /* Verify the entry */
1369 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1382 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1389 * Falcon/Siena pseudo-header
1390 * --------------------------
1392 * Receive packets are prefixed by an optional 16 byte pseudo-header.
1393 * The pseudo-header is a byte array of one of the forms:
1395 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1396 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1397 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1400 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
1401 * LL.LL LFSR hash (16-bit big-endian)
1404 #if EFSYS_OPT_RX_SCALE
1405 static __checkReturn uint32_t
1406 siena_rx_prefix_hash(
1407 __in efx_nic_t *enp,
1408 __in efx_rx_hash_alg_t func,
1409 __in uint8_t *buffer)
1411 _NOTE(ARGUNUSED(enp))
1414 case EFX_RX_HASHALG_TOEPLITZ:
1415 return ((buffer[12] << 24) |
1416 (buffer[13] << 16) |
1420 case EFX_RX_HASHALG_LFSR:
1421 return ((buffer[14] << 8) | buffer[15]);
1428 #endif /* EFSYS_OPT_RX_SCALE */
1430 static __checkReturn efx_rc_t
1431 siena_rx_prefix_pktlen(
1432 __in efx_nic_t *enp,
1433 __in uint8_t *buffer,
1434 __out uint16_t *lengthp)
1436 _NOTE(ARGUNUSED(enp, buffer, lengthp))
1438 /* Not supported by Falcon/Siena hardware */
1446 __in efx_rxq_t *erp,
1447 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1449 __in unsigned int ndescs,
1450 __in unsigned int completed,
1451 __in unsigned int added)
1455 unsigned int offset;
1458 /* The client driver must not overfill the queue */
1459 EFSYS_ASSERT3U(added - completed + ndescs, <=,
1460 EFX_RXQ_LIMIT(erp->er_mask + 1));
1462 id = added & (erp->er_mask);
1463 for (i = 0; i < ndescs; i++) {
1464 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1465 unsigned int, id, efsys_dma_addr_t, addrp[i],
1468 EFX_POPULATE_QWORD_3(qword,
1469 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1470 FSF_AZ_RX_KER_BUF_ADDR_DW0,
1471 (uint32_t)(addrp[i] & 0xffffffff),
1472 FSF_AZ_RX_KER_BUF_ADDR_DW1,
1473 (uint32_t)(addrp[i] >> 32));
1475 offset = id * sizeof (efx_qword_t);
1476 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1478 id = (id + 1) & (erp->er_mask);
1484 __in efx_rxq_t *erp,
1485 __in unsigned int added,
1486 __inout unsigned int *pushedp)
1488 efx_nic_t *enp = erp->er_enp;
1489 unsigned int pushed = *pushedp;
1494 /* All descriptors are pushed */
1497 /* Push the populated descriptors out */
1498 wptr = added & erp->er_mask;
1500 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1502 /* Only write the third DWORD */
1503 EFX_POPULATE_DWORD_1(dword,
1504 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1506 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1507 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1508 wptr, pushed & erp->er_mask);
1509 EFSYS_PIO_WRITE_BARRIER();
1510 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1511 erp->er_index, &dword, B_FALSE);
1514 #if EFSYS_OPT_RX_PACKED_STREAM
1516 siena_rx_qpush_ps_credits(
1517 __in efx_rxq_t *erp)
1519 /* Not supported by Siena hardware */
1524 siena_rx_qps_packet_info(
1525 __in efx_rxq_t *erp,
1526 __in uint8_t *buffer,
1527 __in uint32_t buffer_length,
1528 __in uint32_t current_offset,
1529 __out uint16_t *lengthp,
1530 __out uint32_t *next_offsetp,
1531 __out uint32_t *timestamp)
1533 /* Not supported by Siena hardware */
1538 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1540 static __checkReturn efx_rc_t
1542 __in efx_rxq_t *erp)
1544 efx_nic_t *enp = erp->er_enp;
1548 label = erp->er_index;
1550 /* Flush the queue */
1551 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1552 FRF_AZ_RX_FLUSH_DESCQ, label);
1553 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1560 __in efx_rxq_t *erp)
1562 efx_nic_t *enp = erp->er_enp;
1565 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1567 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1568 erp->er_index, &oword, B_TRUE);
1570 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1571 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1572 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1574 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1575 erp->er_index, &oword, B_TRUE);
1578 static __checkReturn efx_rc_t
1580 __in efx_nic_t *enp,
1581 __in unsigned int index,
1582 __in unsigned int label,
1583 __in efx_rxq_type_t type,
1584 __in_opt const efx_rxq_type_data_t *type_data,
1585 __in efsys_mem_t *esmp,
1588 __in unsigned int flags,
1589 __in efx_evq_t *eep,
1590 __in efx_rxq_t *erp)
1592 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1595 boolean_t jumbo = B_FALSE;
1598 _NOTE(ARGUNUSED(esmp))
1599 _NOTE(ARGUNUSED(type_data))
1601 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1602 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1603 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1604 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1606 if (index >= encp->enc_rxq_limit) {
1611 (1U << size) <= encp->enc_rxq_max_ndescs / encp->enc_rxq_min_ndescs;
1613 if ((1U << size) == (uint32_t)ndescs / encp->enc_rxq_min_ndescs)
1615 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1621 case EFX_RXQ_TYPE_DEFAULT:
1629 if (flags & EFX_RXQ_FLAG_SCATTER) {
1630 #if EFSYS_OPT_RX_SCATTER
1635 #endif /* EFSYS_OPT_RX_SCATTER */
1638 /* Set up the new descriptor queue */
1639 EFX_POPULATE_OWORD_7(oword,
1640 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1641 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1642 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1643 FRF_AZ_RX_DESCQ_LABEL, label,
1644 FRF_AZ_RX_DESCQ_SIZE, size,
1645 FRF_AZ_RX_DESCQ_TYPE, 0,
1646 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1648 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1649 erp->er_index, &oword, B_TRUE);
1653 #if !EFSYS_OPT_RX_SCATTER
1662 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1669 __in efx_rxq_t *erp)
1671 efx_nic_t *enp = erp->er_enp;
1674 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1675 --enp->en_rx_qcount;
1677 /* Purge descriptor queue */
1678 EFX_ZERO_OWORD(oword);
1680 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1681 erp->er_index, &oword, B_TRUE);
1683 /* Free the RXQ object */
1684 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1689 __in efx_nic_t *enp)
1691 _NOTE(ARGUNUSED(enp))
1694 #endif /* EFSYS_OPT_SIENA */