2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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28 * policies, either expressed or implied, of the FreeBSD Project.
37 static __checkReturn efx_rc_t
45 #if EFSYS_OPT_RX_SCATTER
46 static __checkReturn efx_rc_t
47 siena_rx_scatter_enable(
49 __in unsigned int buf_size);
50 #endif /* EFSYS_OPT_RX_SCATTER */
52 #if EFSYS_OPT_RX_SCALE
53 static __checkReturn efx_rc_t
54 siena_rx_scale_mode_set(
56 __in uint32_t rss_context,
57 __in efx_rx_hash_alg_t alg,
58 __in efx_rx_hash_type_t type,
59 __in boolean_t insert);
61 static __checkReturn efx_rc_t
62 siena_rx_scale_key_set(
64 __in uint32_t rss_context,
65 __in_ecount(n) uint8_t *key,
68 static __checkReturn efx_rc_t
69 siena_rx_scale_tbl_set(
71 __in uint32_t rss_context,
72 __in_ecount(n) unsigned int *table,
75 static __checkReturn uint32_t
78 __in efx_rx_hash_alg_t func,
79 __in uint8_t *buffer);
81 #endif /* EFSYS_OPT_RX_SCALE */
83 static __checkReturn efx_rc_t
84 siena_rx_prefix_pktlen(
87 __out uint16_t *lengthp);
92 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
94 __in unsigned int ndescs,
95 __in unsigned int completed,
96 __in unsigned int added);
101 __in unsigned int added,
102 __inout unsigned int *pushedp);
104 #if EFSYS_OPT_RX_PACKED_STREAM
106 siena_rx_qpush_ps_credits(
107 __in efx_rxq_t *erp);
109 static __checkReturn uint8_t *
110 siena_rx_qps_packet_info(
112 __in uint8_t *buffer,
113 __in uint32_t buffer_length,
114 __in uint32_t current_offset,
115 __out uint16_t *lengthp,
116 __out uint32_t *next_offsetp,
117 __out uint32_t *timestamp);
120 static __checkReturn efx_rc_t
122 __in efx_rxq_t *erp);
126 __in efx_rxq_t *erp);
128 static __checkReturn efx_rc_t
131 __in unsigned int index,
132 __in unsigned int label,
133 __in efx_rxq_type_t type,
134 __in uint32_t type_data,
135 __in efsys_mem_t *esmp,
138 __in unsigned int flags,
140 __in efx_rxq_t *erp);
144 __in efx_rxq_t *erp);
146 #endif /* EFSYS_OPT_SIENA */
150 static const efx_rx_ops_t __efx_rx_siena_ops = {
151 siena_rx_init, /* erxo_init */
152 siena_rx_fini, /* erxo_fini */
153 #if EFSYS_OPT_RX_SCATTER
154 siena_rx_scatter_enable, /* erxo_scatter_enable */
156 #if EFSYS_OPT_RX_SCALE
157 NULL, /* erxo_scale_context_alloc */
158 NULL, /* erxo_scale_context_free */
159 siena_rx_scale_mode_set, /* erxo_scale_mode_set */
160 siena_rx_scale_key_set, /* erxo_scale_key_set */
161 siena_rx_scale_tbl_set, /* erxo_scale_tbl_set */
162 siena_rx_prefix_hash, /* erxo_prefix_hash */
164 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
165 siena_rx_qpost, /* erxo_qpost */
166 siena_rx_qpush, /* erxo_qpush */
167 #if EFSYS_OPT_RX_PACKED_STREAM
168 siena_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
169 siena_rx_qps_packet_info, /* erxo_qps_packet_info */
171 siena_rx_qflush, /* erxo_qflush */
172 siena_rx_qenable, /* erxo_qenable */
173 siena_rx_qcreate, /* erxo_qcreate */
174 siena_rx_qdestroy, /* erxo_qdestroy */
176 #endif /* EFSYS_OPT_SIENA */
178 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
179 static const efx_rx_ops_t __efx_rx_ef10_ops = {
180 ef10_rx_init, /* erxo_init */
181 ef10_rx_fini, /* erxo_fini */
182 #if EFSYS_OPT_RX_SCATTER
183 ef10_rx_scatter_enable, /* erxo_scatter_enable */
185 #if EFSYS_OPT_RX_SCALE
186 ef10_rx_scale_context_alloc, /* erxo_scale_context_alloc */
187 ef10_rx_scale_context_free, /* erxo_scale_context_free */
188 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */
189 ef10_rx_scale_key_set, /* erxo_scale_key_set */
190 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */
191 ef10_rx_prefix_hash, /* erxo_prefix_hash */
193 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
194 ef10_rx_qpost, /* erxo_qpost */
195 ef10_rx_qpush, /* erxo_qpush */
196 #if EFSYS_OPT_RX_PACKED_STREAM
197 ef10_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
198 ef10_rx_qps_packet_info, /* erxo_qps_packet_info */
200 ef10_rx_qflush, /* erxo_qflush */
201 ef10_rx_qenable, /* erxo_qenable */
202 ef10_rx_qcreate, /* erxo_qcreate */
203 ef10_rx_qdestroy, /* erxo_qdestroy */
205 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
208 __checkReturn efx_rc_t
210 __inout efx_nic_t *enp)
212 const efx_rx_ops_t *erxop;
215 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
216 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
218 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
223 if (enp->en_mod_flags & EFX_MOD_RX) {
228 switch (enp->en_family) {
230 case EFX_FAMILY_SIENA:
231 erxop = &__efx_rx_siena_ops;
233 #endif /* EFSYS_OPT_SIENA */
235 #if EFSYS_OPT_HUNTINGTON
236 case EFX_FAMILY_HUNTINGTON:
237 erxop = &__efx_rx_ef10_ops;
239 #endif /* EFSYS_OPT_HUNTINGTON */
241 #if EFSYS_OPT_MEDFORD
242 case EFX_FAMILY_MEDFORD:
243 erxop = &__efx_rx_ef10_ops;
245 #endif /* EFSYS_OPT_MEDFORD */
253 if ((rc = erxop->erxo_init(enp)) != 0)
256 enp->en_erxop = erxop;
257 enp->en_mod_flags |= EFX_MOD_RX;
267 EFSYS_PROBE1(fail1, efx_rc_t, rc);
269 enp->en_erxop = NULL;
270 enp->en_mod_flags &= ~EFX_MOD_RX;
278 const efx_rx_ops_t *erxop = enp->en_erxop;
280 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
281 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
282 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
283 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
285 erxop->erxo_fini(enp);
287 enp->en_erxop = NULL;
288 enp->en_mod_flags &= ~EFX_MOD_RX;
291 #if EFSYS_OPT_RX_SCATTER
292 __checkReturn efx_rc_t
293 efx_rx_scatter_enable(
295 __in unsigned int buf_size)
297 const efx_rx_ops_t *erxop = enp->en_erxop;
300 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
301 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
303 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
309 EFSYS_PROBE1(fail1, efx_rc_t, rc);
312 #endif /* EFSYS_OPT_RX_SCATTER */
314 #if EFSYS_OPT_RX_SCALE
315 __checkReturn efx_rc_t
316 efx_rx_hash_default_support_get(
318 __out efx_rx_hash_support_t *supportp)
322 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
323 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
325 if (supportp == NULL) {
331 * Report the hashing support the client gets by default if it
332 * does not allocate an RSS context itself.
334 *supportp = enp->en_hash_support;
339 EFSYS_PROBE1(fail1, efx_rc_t, rc);
344 __checkReturn efx_rc_t
345 efx_rx_scale_default_support_get(
347 __out efx_rx_scale_context_type_t *typep)
351 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
352 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
360 * Report the RSS support the client gets by default if it
361 * does not allocate an RSS context itself.
363 *typep = enp->en_rss_context_type;
368 EFSYS_PROBE1(fail1, efx_rc_t, rc);
372 #endif /* EFSYS_OPT_RX_SCALE */
374 #if EFSYS_OPT_RX_SCALE
375 __checkReturn efx_rc_t
376 efx_rx_scale_context_alloc(
378 __in efx_rx_scale_context_type_t type,
379 __in uint32_t num_queues,
380 __out uint32_t *rss_contextp)
382 const efx_rx_ops_t *erxop = enp->en_erxop;
385 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
386 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
388 if (erxop->erxo_scale_context_alloc == NULL) {
392 if ((rc = erxop->erxo_scale_context_alloc(enp, type,
393 num_queues, rss_contextp)) != 0) {
402 EFSYS_PROBE1(fail1, efx_rc_t, rc);
405 #endif /* EFSYS_OPT_RX_SCALE */
407 #if EFSYS_OPT_RX_SCALE
408 __checkReturn efx_rc_t
409 efx_rx_scale_context_free(
411 __in uint32_t rss_context)
413 const efx_rx_ops_t *erxop = enp->en_erxop;
416 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
417 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
419 if (erxop->erxo_scale_context_free == NULL) {
423 if ((rc = erxop->erxo_scale_context_free(enp, rss_context)) != 0)
431 EFSYS_PROBE1(fail1, efx_rc_t, rc);
434 #endif /* EFSYS_OPT_RX_SCALE */
436 #if EFSYS_OPT_RX_SCALE
437 __checkReturn efx_rc_t
438 efx_rx_scale_mode_set(
440 __in uint32_t rss_context,
441 __in efx_rx_hash_alg_t alg,
442 __in efx_rx_hash_type_t type,
443 __in boolean_t insert)
445 const efx_rx_ops_t *erxop = enp->en_erxop;
448 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
449 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
451 if (erxop->erxo_scale_mode_set != NULL) {
452 if ((rc = erxop->erxo_scale_mode_set(enp, rss_context, alg,
460 EFSYS_PROBE1(fail1, efx_rc_t, rc);
463 #endif /* EFSYS_OPT_RX_SCALE */
465 #if EFSYS_OPT_RX_SCALE
466 __checkReturn efx_rc_t
467 efx_rx_scale_key_set(
469 __in uint32_t rss_context,
470 __in_ecount(n) uint8_t *key,
473 const efx_rx_ops_t *erxop = enp->en_erxop;
476 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
477 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
479 if ((rc = erxop->erxo_scale_key_set(enp, rss_context, key, n)) != 0)
485 EFSYS_PROBE1(fail1, efx_rc_t, rc);
489 #endif /* EFSYS_OPT_RX_SCALE */
491 #if EFSYS_OPT_RX_SCALE
492 __checkReturn efx_rc_t
493 efx_rx_scale_tbl_set(
495 __in uint32_t rss_context,
496 __in_ecount(n) unsigned int *table,
499 const efx_rx_ops_t *erxop = enp->en_erxop;
502 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
503 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
505 if ((rc = erxop->erxo_scale_tbl_set(enp, rss_context, table, n)) != 0)
511 EFSYS_PROBE1(fail1, efx_rc_t, rc);
515 #endif /* EFSYS_OPT_RX_SCALE */
520 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
522 __in unsigned int ndescs,
523 __in unsigned int completed,
524 __in unsigned int added)
526 efx_nic_t *enp = erp->er_enp;
527 const efx_rx_ops_t *erxop = enp->en_erxop;
529 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
531 erxop->erxo_qpost(erp, addrp, size, ndescs, completed, added);
534 #if EFSYS_OPT_RX_PACKED_STREAM
537 efx_rx_qpush_ps_credits(
540 efx_nic_t *enp = erp->er_enp;
541 const efx_rx_ops_t *erxop = enp->en_erxop;
543 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
545 erxop->erxo_qpush_ps_credits(erp);
548 __checkReturn uint8_t *
549 efx_rx_qps_packet_info(
551 __in uint8_t *buffer,
552 __in uint32_t buffer_length,
553 __in uint32_t current_offset,
554 __out uint16_t *lengthp,
555 __out uint32_t *next_offsetp,
556 __out uint32_t *timestamp)
558 efx_nic_t *enp = erp->er_enp;
559 const efx_rx_ops_t *erxop = enp->en_erxop;
561 return (erxop->erxo_qps_packet_info(erp, buffer,
562 buffer_length, current_offset, lengthp,
563 next_offsetp, timestamp));
566 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
571 __in unsigned int added,
572 __inout unsigned int *pushedp)
574 efx_nic_t *enp = erp->er_enp;
575 const efx_rx_ops_t *erxop = enp->en_erxop;
577 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
579 erxop->erxo_qpush(erp, added, pushedp);
582 __checkReturn efx_rc_t
586 efx_nic_t *enp = erp->er_enp;
587 const efx_rx_ops_t *erxop = enp->en_erxop;
590 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
592 if ((rc = erxop->erxo_qflush(erp)) != 0)
598 EFSYS_PROBE1(fail1, efx_rc_t, rc);
607 efx_nic_t *enp = erp->er_enp;
608 const efx_rx_ops_t *erxop = enp->en_erxop;
610 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
612 erxop->erxo_qenable(erp);
615 static __checkReturn efx_rc_t
616 efx_rx_qcreate_internal(
618 __in unsigned int index,
619 __in unsigned int label,
620 __in efx_rxq_type_t type,
621 __in uint32_t type_data,
622 __in efsys_mem_t *esmp,
625 __in unsigned int flags,
627 __deref_out efx_rxq_t **erpp)
629 const efx_rx_ops_t *erxop = enp->en_erxop;
633 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
634 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
636 /* Allocate an RXQ object */
637 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
644 erp->er_magic = EFX_RXQ_MAGIC;
646 erp->er_index = index;
647 erp->er_mask = ndescs - 1;
650 if ((rc = erxop->erxo_qcreate(enp, index, label, type, type_data, esmp,
651 ndescs, id, flags, eep, erp)) != 0)
662 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
664 EFSYS_PROBE1(fail1, efx_rc_t, rc);
669 __checkReturn efx_rc_t
672 __in unsigned int index,
673 __in unsigned int label,
674 __in efx_rxq_type_t type,
675 __in efsys_mem_t *esmp,
678 __in unsigned int flags,
680 __deref_out efx_rxq_t **erpp)
682 return efx_rx_qcreate_internal(enp, index, label, type, 0, esmp, ndescs,
683 id, flags, eep, erpp);
686 #if EFSYS_OPT_RX_PACKED_STREAM
688 __checkReturn efx_rc_t
689 efx_rx_qcreate_packed_stream(
691 __in unsigned int index,
692 __in unsigned int label,
693 __in uint32_t ps_buf_size,
694 __in efsys_mem_t *esmp,
697 __deref_out efx_rxq_t **erpp)
699 return efx_rx_qcreate_internal(enp, index, label,
700 EFX_RXQ_TYPE_PACKED_STREAM, ps_buf_size, esmp, ndescs,
701 0 /* id unused on EF10 */, EFX_RXQ_FLAG_NONE, eep, erpp);
710 efx_nic_t *enp = erp->er_enp;
711 const efx_rx_ops_t *erxop = enp->en_erxop;
713 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
715 erxop->erxo_qdestroy(erp);
718 __checkReturn efx_rc_t
719 efx_pseudo_hdr_pkt_length_get(
721 __in uint8_t *buffer,
722 __out uint16_t *lengthp)
724 efx_nic_t *enp = erp->er_enp;
725 const efx_rx_ops_t *erxop = enp->en_erxop;
727 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
729 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
732 #if EFSYS_OPT_RX_SCALE
733 __checkReturn uint32_t
734 efx_pseudo_hdr_hash_get(
736 __in efx_rx_hash_alg_t func,
737 __in uint8_t *buffer)
739 efx_nic_t *enp = erp->er_enp;
740 const efx_rx_ops_t *erxop = enp->en_erxop;
742 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
744 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
745 return (erxop->erxo_prefix_hash(enp, func, buffer));
747 #endif /* EFSYS_OPT_RX_SCALE */
751 static __checkReturn efx_rc_t
758 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
760 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
761 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
762 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
763 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
764 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
765 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
766 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
768 /* Zero the RSS table */
769 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
771 EFX_ZERO_OWORD(oword);
772 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
773 index, &oword, B_TRUE);
776 #if EFSYS_OPT_RX_SCALE
777 /* The RSS key and indirection table are writable. */
778 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
780 /* Hardware can insert RX hash with/without RSS */
781 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
782 #endif /* EFSYS_OPT_RX_SCALE */
787 #if EFSYS_OPT_RX_SCATTER
788 static __checkReturn efx_rc_t
789 siena_rx_scatter_enable(
791 __in unsigned int buf_size)
797 nbuf32 = buf_size / 32;
799 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
800 ((buf_size % 32) != 0)) {
805 if (enp->en_rx_qcount > 0) {
810 /* Set scatter buffer size */
811 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
812 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
813 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
815 /* Enable scatter for packets not matching a filter */
816 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
817 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
818 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
825 EFSYS_PROBE1(fail1, efx_rc_t, rc);
829 #endif /* EFSYS_OPT_RX_SCATTER */
832 #define EFX_RX_LFSR_HASH(_enp, _insert) \
836 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
837 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
838 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
839 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
840 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
841 (_insert) ? 1 : 0); \
842 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
844 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
845 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
847 EFX_SET_OWORD_FIELD(oword, \
848 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
849 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
853 _NOTE(CONSTANTCONDITION) \
856 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
860 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
861 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
862 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
864 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
866 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
867 (_insert) ? 1 : 0); \
868 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
870 _NOTE(CONSTANTCONDITION) \
873 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
877 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
878 EFX_SET_OWORD_FIELD(oword, \
879 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
880 EFX_SET_OWORD_FIELD(oword, \
881 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
882 EFX_SET_OWORD_FIELD(oword, \
883 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
884 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
888 _NOTE(CONSTANTCONDITION) \
892 #if EFSYS_OPT_RX_SCALE
894 static __checkReturn efx_rc_t
895 siena_rx_scale_mode_set(
897 __in uint32_t rss_context,
898 __in efx_rx_hash_alg_t alg,
899 __in efx_rx_hash_type_t type,
900 __in boolean_t insert)
904 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
910 case EFX_RX_HASHALG_LFSR:
911 EFX_RX_LFSR_HASH(enp, insert);
914 case EFX_RX_HASHALG_TOEPLITZ:
915 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
916 type & EFX_RX_HASH_IPV4,
917 type & EFX_RX_HASH_TCPIPV4);
919 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
920 type & EFX_RX_HASH_IPV6,
921 type & EFX_RX_HASH_TCPIPV6,
940 EFSYS_PROBE1(fail1, efx_rc_t, rc);
942 EFX_RX_LFSR_HASH(enp, B_FALSE);
948 #if EFSYS_OPT_RX_SCALE
949 static __checkReturn efx_rc_t
950 siena_rx_scale_key_set(
952 __in uint32_t rss_context,
953 __in_ecount(n) uint8_t *key,
961 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
968 /* Write Toeplitz IPv4 hash key */
969 EFX_ZERO_OWORD(oword);
970 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
971 offset > 0 && byte < n;
973 oword.eo_u8[offset - 1] = key[byte++];
975 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
979 /* Verify Toeplitz IPv4 hash key */
980 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
981 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
982 offset > 0 && byte < n;
984 if (oword.eo_u8[offset - 1] != key[byte++]) {
990 if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
995 /* Write Toeplitz IPv6 hash key 3 */
996 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
997 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
998 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
999 offset > 0 && byte < n;
1001 oword.eo_u8[offset - 1] = key[byte++];
1003 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1005 /* Write Toeplitz IPv6 hash key 2 */
1006 EFX_ZERO_OWORD(oword);
1007 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1008 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1009 offset > 0 && byte < n;
1011 oword.eo_u8[offset - 1] = key[byte++];
1013 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1015 /* Write Toeplitz IPv6 hash key 1 */
1016 EFX_ZERO_OWORD(oword);
1017 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1018 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1019 offset > 0 && byte < n;
1021 oword.eo_u8[offset - 1] = key[byte++];
1023 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1027 /* Verify Toeplitz IPv6 hash key 3 */
1028 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1029 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1030 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1031 offset > 0 && byte < n;
1033 if (oword.eo_u8[offset - 1] != key[byte++]) {
1039 /* Verify Toeplitz IPv6 hash key 2 */
1040 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1041 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1042 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1043 offset > 0 && byte < n;
1045 if (oword.eo_u8[offset - 1] != key[byte++]) {
1051 /* Verify Toeplitz IPv6 hash key 1 */
1052 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1053 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1054 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1055 offset > 0 && byte < n;
1057 if (oword.eo_u8[offset - 1] != key[byte++]) {
1075 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1081 #if EFSYS_OPT_RX_SCALE
1082 static __checkReturn efx_rc_t
1083 siena_rx_scale_tbl_set(
1084 __in efx_nic_t *enp,
1085 __in uint32_t rss_context,
1086 __in_ecount(n) unsigned int *table,
1093 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
1094 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
1096 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1101 if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
1106 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
1109 /* Calculate the entry to place in the table */
1110 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1112 EFSYS_PROBE2(table, int, index, uint32_t, byte);
1114 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
1116 /* Write the table */
1117 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1118 index, &oword, B_TRUE);
1121 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
1124 /* Determine if we're starting a new batch */
1125 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1127 /* Read the table */
1128 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
1129 index, &oword, B_TRUE);
1131 /* Verify the entry */
1132 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1145 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1152 * Falcon/Siena pseudo-header
1153 * --------------------------
1155 * Receive packets are prefixed by an optional 16 byte pseudo-header.
1156 * The pseudo-header is a byte array of one of the forms:
1158 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1159 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1160 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1163 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
1164 * LL.LL LFSR hash (16-bit big-endian)
1167 #if EFSYS_OPT_RX_SCALE
1168 static __checkReturn uint32_t
1169 siena_rx_prefix_hash(
1170 __in efx_nic_t *enp,
1171 __in efx_rx_hash_alg_t func,
1172 __in uint8_t *buffer)
1174 _NOTE(ARGUNUSED(enp))
1177 case EFX_RX_HASHALG_TOEPLITZ:
1178 return ((buffer[12] << 24) |
1179 (buffer[13] << 16) |
1183 case EFX_RX_HASHALG_LFSR:
1184 return ((buffer[14] << 8) | buffer[15]);
1191 #endif /* EFSYS_OPT_RX_SCALE */
1193 static __checkReturn efx_rc_t
1194 siena_rx_prefix_pktlen(
1195 __in efx_nic_t *enp,
1196 __in uint8_t *buffer,
1197 __out uint16_t *lengthp)
1199 _NOTE(ARGUNUSED(enp, buffer, lengthp))
1201 /* Not supported by Falcon/Siena hardware */
1209 __in efx_rxq_t *erp,
1210 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1212 __in unsigned int ndescs,
1213 __in unsigned int completed,
1214 __in unsigned int added)
1218 unsigned int offset;
1221 /* The client driver must not overfill the queue */
1222 EFSYS_ASSERT3U(added - completed + ndescs, <=,
1223 EFX_RXQ_LIMIT(erp->er_mask + 1));
1225 id = added & (erp->er_mask);
1226 for (i = 0; i < ndescs; i++) {
1227 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1228 unsigned int, id, efsys_dma_addr_t, addrp[i],
1231 EFX_POPULATE_QWORD_3(qword,
1232 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1233 FSF_AZ_RX_KER_BUF_ADDR_DW0,
1234 (uint32_t)(addrp[i] & 0xffffffff),
1235 FSF_AZ_RX_KER_BUF_ADDR_DW1,
1236 (uint32_t)(addrp[i] >> 32));
1238 offset = id * sizeof (efx_qword_t);
1239 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1241 id = (id + 1) & (erp->er_mask);
1247 __in efx_rxq_t *erp,
1248 __in unsigned int added,
1249 __inout unsigned int *pushedp)
1251 efx_nic_t *enp = erp->er_enp;
1252 unsigned int pushed = *pushedp;
1257 /* All descriptors are pushed */
1260 /* Push the populated descriptors out */
1261 wptr = added & erp->er_mask;
1263 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1265 /* Only write the third DWORD */
1266 EFX_POPULATE_DWORD_1(dword,
1267 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1269 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1270 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1271 wptr, pushed & erp->er_mask);
1272 EFSYS_PIO_WRITE_BARRIER();
1273 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1274 erp->er_index, &dword, B_FALSE);
1277 #if EFSYS_OPT_RX_PACKED_STREAM
1279 siena_rx_qpush_ps_credits(
1280 __in efx_rxq_t *erp)
1282 /* Not supported by Siena hardware */
1287 siena_rx_qps_packet_info(
1288 __in efx_rxq_t *erp,
1289 __in uint8_t *buffer,
1290 __in uint32_t buffer_length,
1291 __in uint32_t current_offset,
1292 __out uint16_t *lengthp,
1293 __out uint32_t *next_offsetp,
1294 __out uint32_t *timestamp)
1296 /* Not supported by Siena hardware */
1301 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1303 static __checkReturn efx_rc_t
1305 __in efx_rxq_t *erp)
1307 efx_nic_t *enp = erp->er_enp;
1311 label = erp->er_index;
1313 /* Flush the queue */
1314 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1315 FRF_AZ_RX_FLUSH_DESCQ, label);
1316 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1323 __in efx_rxq_t *erp)
1325 efx_nic_t *enp = erp->er_enp;
1328 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1330 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1331 erp->er_index, &oword, B_TRUE);
1333 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1334 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1335 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1337 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1338 erp->er_index, &oword, B_TRUE);
1341 static __checkReturn efx_rc_t
1343 __in efx_nic_t *enp,
1344 __in unsigned int index,
1345 __in unsigned int label,
1346 __in efx_rxq_type_t type,
1347 __in uint32_t type_data,
1348 __in efsys_mem_t *esmp,
1351 __in unsigned int flags,
1352 __in efx_evq_t *eep,
1353 __in efx_rxq_t *erp)
1355 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1358 boolean_t jumbo = B_FALSE;
1361 _NOTE(ARGUNUSED(esmp))
1362 _NOTE(ARGUNUSED(type_data))
1364 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1365 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1366 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1367 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1369 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1370 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1372 if (!ISP2(ndescs) ||
1373 (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
1377 if (index >= encp->enc_rxq_limit) {
1381 for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1383 if ((1 << size) == (int)(ndescs / EFX_RXQ_MINNDESCS))
1385 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1391 case EFX_RXQ_TYPE_DEFAULT:
1399 if (flags & EFX_RXQ_FLAG_SCATTER) {
1400 #if EFSYS_OPT_RX_SCATTER
1405 #endif /* EFSYS_OPT_RX_SCATTER */
1408 /* Set up the new descriptor queue */
1409 EFX_POPULATE_OWORD_7(oword,
1410 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1411 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1412 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1413 FRF_AZ_RX_DESCQ_LABEL, label,
1414 FRF_AZ_RX_DESCQ_SIZE, size,
1415 FRF_AZ_RX_DESCQ_TYPE, 0,
1416 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1418 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1419 erp->er_index, &oword, B_TRUE);
1423 #if !EFSYS_OPT_RX_SCATTER
1434 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1441 __in efx_rxq_t *erp)
1443 efx_nic_t *enp = erp->er_enp;
1446 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1447 --enp->en_rx_qcount;
1449 /* Purge descriptor queue */
1450 EFX_ZERO_OWORD(oword);
1452 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1453 erp->er_index, &oword, B_TRUE);
1455 /* Free the RXQ object */
1456 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1461 __in efx_nic_t *enp)
1463 _NOTE(ARGUNUSED(enp))
1466 #endif /* EFSYS_OPT_SIENA */