2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
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6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
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14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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37 static __checkReturn efx_rc_t
45 #if EFSYS_OPT_RX_SCATTER
46 static __checkReturn efx_rc_t
47 siena_rx_scatter_enable(
49 __in unsigned int buf_size);
50 #endif /* EFSYS_OPT_RX_SCATTER */
52 #if EFSYS_OPT_RX_SCALE
53 static __checkReturn efx_rc_t
54 siena_rx_scale_mode_set(
56 __in efx_rx_hash_alg_t alg,
57 __in efx_rx_hash_type_t type,
58 __in boolean_t insert);
60 static __checkReturn efx_rc_t
61 siena_rx_scale_key_set(
63 __in_ecount(n) uint8_t *key,
66 static __checkReturn efx_rc_t
67 siena_rx_scale_tbl_set(
69 __in_ecount(n) unsigned int *table,
72 static __checkReturn uint32_t
75 __in efx_rx_hash_alg_t func,
76 __in uint8_t *buffer);
78 #endif /* EFSYS_OPT_RX_SCALE */
80 static __checkReturn efx_rc_t
81 siena_rx_prefix_pktlen(
84 __out uint16_t *lengthp);
89 __in_ecount(n) efsys_dma_addr_t *addrp,
92 __in unsigned int completed,
93 __in unsigned int added);
98 __in unsigned int added,
99 __inout unsigned int *pushedp);
101 #if EFSYS_OPT_RX_PACKED_STREAM
103 siena_rx_qps_update_credits(
104 __in efx_rxq_t *erp);
106 static __checkReturn uint8_t *
107 siena_rx_qps_packet_info(
109 __in uint8_t *buffer,
110 __in uint32_t buffer_length,
111 __in uint32_t current_offset,
112 __out uint16_t *lengthp,
113 __out uint32_t *next_offsetp,
114 __out uint32_t *timestamp);
117 static __checkReturn efx_rc_t
119 __in efx_rxq_t *erp);
123 __in efx_rxq_t *erp);
125 static __checkReturn efx_rc_t
128 __in unsigned int index,
129 __in unsigned int label,
130 __in efx_rxq_type_t type,
131 __in efsys_mem_t *esmp,
135 __in efx_rxq_t *erp);
139 __in efx_rxq_t *erp);
141 #endif /* EFSYS_OPT_SIENA */
145 static const efx_rx_ops_t __efx_rx_siena_ops = {
146 siena_rx_init, /* erxo_init */
147 siena_rx_fini, /* erxo_fini */
148 #if EFSYS_OPT_RX_SCATTER
149 siena_rx_scatter_enable, /* erxo_scatter_enable */
151 #if EFSYS_OPT_RX_SCALE
152 siena_rx_scale_mode_set, /* erxo_scale_mode_set */
153 siena_rx_scale_key_set, /* erxo_scale_key_set */
154 siena_rx_scale_tbl_set, /* erxo_scale_tbl_set */
155 siena_rx_prefix_hash, /* erxo_prefix_hash */
157 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
158 siena_rx_qpost, /* erxo_qpost */
159 siena_rx_qpush, /* erxo_qpush */
160 #if EFSYS_OPT_RX_PACKED_STREAM
161 siena_rx_qps_update_credits, /* erxo_qps_update_credits */
162 siena_rx_qps_packet_info, /* erxo_qps_packet_info */
164 siena_rx_qflush, /* erxo_qflush */
165 siena_rx_qenable, /* erxo_qenable */
166 siena_rx_qcreate, /* erxo_qcreate */
167 siena_rx_qdestroy, /* erxo_qdestroy */
169 #endif /* EFSYS_OPT_SIENA */
171 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
172 static const efx_rx_ops_t __efx_rx_ef10_ops = {
173 ef10_rx_init, /* erxo_init */
174 ef10_rx_fini, /* erxo_fini */
175 #if EFSYS_OPT_RX_SCATTER
176 ef10_rx_scatter_enable, /* erxo_scatter_enable */
178 #if EFSYS_OPT_RX_SCALE
179 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */
180 ef10_rx_scale_key_set, /* erxo_scale_key_set */
181 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */
182 ef10_rx_prefix_hash, /* erxo_prefix_hash */
184 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
185 ef10_rx_qpost, /* erxo_qpost */
186 ef10_rx_qpush, /* erxo_qpush */
187 #if EFSYS_OPT_RX_PACKED_STREAM
188 ef10_rx_qps_update_credits, /* erxo_qps_update_credits */
189 ef10_rx_qps_packet_info, /* erxo_qps_packet_info */
191 ef10_rx_qflush, /* erxo_qflush */
192 ef10_rx_qenable, /* erxo_qenable */
193 ef10_rx_qcreate, /* erxo_qcreate */
194 ef10_rx_qdestroy, /* erxo_qdestroy */
196 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
199 __checkReturn efx_rc_t
201 __inout efx_nic_t *enp)
203 const efx_rx_ops_t *erxop;
206 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
207 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
209 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
214 if (enp->en_mod_flags & EFX_MOD_RX) {
219 switch (enp->en_family) {
221 case EFX_FAMILY_SIENA:
222 erxop = &__efx_rx_siena_ops;
224 #endif /* EFSYS_OPT_SIENA */
226 #if EFSYS_OPT_HUNTINGTON
227 case EFX_FAMILY_HUNTINGTON:
228 erxop = &__efx_rx_ef10_ops;
230 #endif /* EFSYS_OPT_HUNTINGTON */
232 #if EFSYS_OPT_MEDFORD
233 case EFX_FAMILY_MEDFORD:
234 erxop = &__efx_rx_ef10_ops;
236 #endif /* EFSYS_OPT_MEDFORD */
244 if ((rc = erxop->erxo_init(enp)) != 0)
247 enp->en_erxop = erxop;
248 enp->en_mod_flags |= EFX_MOD_RX;
258 EFSYS_PROBE1(fail1, efx_rc_t, rc);
260 enp->en_erxop = NULL;
261 enp->en_mod_flags &= ~EFX_MOD_RX;
269 const efx_rx_ops_t *erxop = enp->en_erxop;
271 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
272 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
273 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
274 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
276 erxop->erxo_fini(enp);
278 enp->en_erxop = NULL;
279 enp->en_mod_flags &= ~EFX_MOD_RX;
282 #if EFSYS_OPT_RX_SCATTER
283 __checkReturn efx_rc_t
284 efx_rx_scatter_enable(
286 __in unsigned int buf_size)
288 const efx_rx_ops_t *erxop = enp->en_erxop;
291 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
292 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
294 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
300 EFSYS_PROBE1(fail1, efx_rc_t, rc);
303 #endif /* EFSYS_OPT_RX_SCATTER */
305 #if EFSYS_OPT_RX_SCALE
306 __checkReturn efx_rc_t
307 efx_rx_hash_default_support_get(
309 __out efx_rx_hash_support_t *supportp)
313 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
314 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
316 if (supportp == NULL) {
322 * Report the hashing support the client gets by default if it
323 * does not allocate an RSS context itself.
325 *supportp = enp->en_hash_support;
330 EFSYS_PROBE1(fail1, efx_rc_t, rc);
335 __checkReturn efx_rc_t
336 efx_rx_scale_default_support_get(
338 __out efx_rx_scale_context_type_t *typep)
342 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
343 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
351 * Report the RSS support the client gets by default if it
352 * does not allocate an RSS context itself.
354 *typep = enp->en_rss_context_type;
359 EFSYS_PROBE1(fail1, efx_rc_t, rc);
364 __checkReturn efx_rc_t
365 efx_rx_scale_mode_set(
367 __in efx_rx_hash_alg_t alg,
368 __in efx_rx_hash_type_t type,
369 __in boolean_t insert)
371 const efx_rx_ops_t *erxop = enp->en_erxop;
374 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
375 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
377 if (erxop->erxo_scale_mode_set != NULL) {
378 if ((rc = erxop->erxo_scale_mode_set(enp, alg,
386 EFSYS_PROBE1(fail1, efx_rc_t, rc);
389 #endif /* EFSYS_OPT_RX_SCALE */
391 #if EFSYS_OPT_RX_SCALE
392 __checkReturn efx_rc_t
393 efx_rx_scale_key_set(
395 __in_ecount(n) uint8_t *key,
398 const efx_rx_ops_t *erxop = enp->en_erxop;
401 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
402 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
404 if ((rc = erxop->erxo_scale_key_set(enp, key, n)) != 0)
410 EFSYS_PROBE1(fail1, efx_rc_t, rc);
414 #endif /* EFSYS_OPT_RX_SCALE */
416 #if EFSYS_OPT_RX_SCALE
417 __checkReturn efx_rc_t
418 efx_rx_scale_tbl_set(
420 __in_ecount(n) unsigned int *table,
423 const efx_rx_ops_t *erxop = enp->en_erxop;
426 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
427 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
429 if ((rc = erxop->erxo_scale_tbl_set(enp, table, n)) != 0)
435 EFSYS_PROBE1(fail1, efx_rc_t, rc);
439 #endif /* EFSYS_OPT_RX_SCALE */
444 __in_ecount(n) efsys_dma_addr_t *addrp,
447 __in unsigned int completed,
448 __in unsigned int added)
450 efx_nic_t *enp = erp->er_enp;
451 const efx_rx_ops_t *erxop = enp->en_erxop;
453 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
455 erxop->erxo_qpost(erp, addrp, size, n, completed, added);
458 #if EFSYS_OPT_RX_PACKED_STREAM
461 efx_rx_qps_update_credits(
464 efx_nic_t *enp = erp->er_enp;
465 const efx_rx_ops_t *erxop = enp->en_erxop;
467 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
469 erxop->erxo_qps_update_credits(erp);
472 __checkReturn uint8_t *
473 efx_rx_qps_packet_info(
475 __in uint8_t *buffer,
476 __in uint32_t buffer_length,
477 __in uint32_t current_offset,
478 __out uint16_t *lengthp,
479 __out uint32_t *next_offsetp,
480 __out uint32_t *timestamp)
482 efx_nic_t *enp = erp->er_enp;
483 const efx_rx_ops_t *erxop = enp->en_erxop;
485 return (erxop->erxo_qps_packet_info(erp, buffer,
486 buffer_length, current_offset, lengthp,
487 next_offsetp, timestamp));
490 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
495 __in unsigned int added,
496 __inout unsigned int *pushedp)
498 efx_nic_t *enp = erp->er_enp;
499 const efx_rx_ops_t *erxop = enp->en_erxop;
501 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
503 erxop->erxo_qpush(erp, added, pushedp);
506 __checkReturn efx_rc_t
510 efx_nic_t *enp = erp->er_enp;
511 const efx_rx_ops_t *erxop = enp->en_erxop;
514 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
516 if ((rc = erxop->erxo_qflush(erp)) != 0)
522 EFSYS_PROBE1(fail1, efx_rc_t, rc);
531 efx_nic_t *enp = erp->er_enp;
532 const efx_rx_ops_t *erxop = enp->en_erxop;
534 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
536 erxop->erxo_qenable(erp);
539 __checkReturn efx_rc_t
542 __in unsigned int index,
543 __in unsigned int label,
544 __in efx_rxq_type_t type,
545 __in efsys_mem_t *esmp,
549 __deref_out efx_rxq_t **erpp)
551 const efx_rx_ops_t *erxop = enp->en_erxop;
555 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
556 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
558 /* Allocate an RXQ object */
559 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
566 erp->er_magic = EFX_RXQ_MAGIC;
568 erp->er_index = index;
569 erp->er_mask = n - 1;
572 if ((rc = erxop->erxo_qcreate(enp, index, label, type, esmp, n, id,
584 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
586 EFSYS_PROBE1(fail1, efx_rc_t, rc);
595 efx_nic_t *enp = erp->er_enp;
596 const efx_rx_ops_t *erxop = enp->en_erxop;
598 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
600 erxop->erxo_qdestroy(erp);
603 __checkReturn efx_rc_t
604 efx_pseudo_hdr_pkt_length_get(
606 __in uint8_t *buffer,
607 __out uint16_t *lengthp)
609 efx_nic_t *enp = erp->er_enp;
610 const efx_rx_ops_t *erxop = enp->en_erxop;
612 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
614 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
617 #if EFSYS_OPT_RX_SCALE
618 __checkReturn uint32_t
619 efx_pseudo_hdr_hash_get(
621 __in efx_rx_hash_alg_t func,
622 __in uint8_t *buffer)
624 efx_nic_t *enp = erp->er_enp;
625 const efx_rx_ops_t *erxop = enp->en_erxop;
627 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
629 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
630 return (erxop->erxo_prefix_hash(enp, func, buffer));
632 #endif /* EFSYS_OPT_RX_SCALE */
636 static __checkReturn efx_rc_t
643 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
645 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
646 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
647 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
648 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
649 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
650 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
651 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
653 /* Zero the RSS table */
654 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
656 EFX_ZERO_OWORD(oword);
657 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
658 index, &oword, B_TRUE);
661 #if EFSYS_OPT_RX_SCALE
662 /* The RSS key and indirection table are writable. */
663 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
665 /* Hardware can insert RX hash with/without RSS */
666 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
667 #endif /* EFSYS_OPT_RX_SCALE */
672 #if EFSYS_OPT_RX_SCATTER
673 static __checkReturn efx_rc_t
674 siena_rx_scatter_enable(
676 __in unsigned int buf_size)
682 nbuf32 = buf_size / 32;
684 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
685 ((buf_size % 32) != 0)) {
690 if (enp->en_rx_qcount > 0) {
695 /* Set scatter buffer size */
696 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
697 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
698 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
700 /* Enable scatter for packets not matching a filter */
701 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
702 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
703 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
710 EFSYS_PROBE1(fail1, efx_rc_t, rc);
714 #endif /* EFSYS_OPT_RX_SCATTER */
717 #define EFX_RX_LFSR_HASH(_enp, _insert) \
721 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
722 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
723 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
724 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
725 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
726 (_insert) ? 1 : 0); \
727 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
729 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
730 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
732 EFX_SET_OWORD_FIELD(oword, \
733 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
734 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
738 _NOTE(CONSTANTCONDITION) \
741 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
745 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
746 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
747 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
749 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
751 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
752 (_insert) ? 1 : 0); \
753 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
755 _NOTE(CONSTANTCONDITION) \
758 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
762 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
763 EFX_SET_OWORD_FIELD(oword, \
764 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
765 EFX_SET_OWORD_FIELD(oword, \
766 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
767 EFX_SET_OWORD_FIELD(oword, \
768 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
769 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
773 _NOTE(CONSTANTCONDITION) \
777 #if EFSYS_OPT_RX_SCALE
779 static __checkReturn efx_rc_t
780 siena_rx_scale_mode_set(
782 __in efx_rx_hash_alg_t alg,
783 __in efx_rx_hash_type_t type,
784 __in boolean_t insert)
789 case EFX_RX_HASHALG_LFSR:
790 EFX_RX_LFSR_HASH(enp, insert);
793 case EFX_RX_HASHALG_TOEPLITZ:
794 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
795 type & EFX_RX_HASH_IPV4,
796 type & EFX_RX_HASH_TCPIPV4);
798 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
799 type & EFX_RX_HASH_IPV6,
800 type & EFX_RX_HASH_TCPIPV6,
817 EFSYS_PROBE1(fail1, efx_rc_t, rc);
819 EFX_RX_LFSR_HASH(enp, B_FALSE);
825 #if EFSYS_OPT_RX_SCALE
826 static __checkReturn efx_rc_t
827 siena_rx_scale_key_set(
829 __in_ecount(n) uint8_t *key,
839 /* Write Toeplitz IPv4 hash key */
840 EFX_ZERO_OWORD(oword);
841 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
842 offset > 0 && byte < n;
844 oword.eo_u8[offset - 1] = key[byte++];
846 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
850 /* Verify Toeplitz IPv4 hash key */
851 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
852 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
853 offset > 0 && byte < n;
855 if (oword.eo_u8[offset - 1] != key[byte++]) {
861 if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
866 /* Write Toeplitz IPv6 hash key 3 */
867 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
868 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
869 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
870 offset > 0 && byte < n;
872 oword.eo_u8[offset - 1] = key[byte++];
874 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
876 /* Write Toeplitz IPv6 hash key 2 */
877 EFX_ZERO_OWORD(oword);
878 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
879 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
880 offset > 0 && byte < n;
882 oword.eo_u8[offset - 1] = key[byte++];
884 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
886 /* Write Toeplitz IPv6 hash key 1 */
887 EFX_ZERO_OWORD(oword);
888 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
889 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
890 offset > 0 && byte < n;
892 oword.eo_u8[offset - 1] = key[byte++];
894 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
898 /* Verify Toeplitz IPv6 hash key 3 */
899 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
900 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
901 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
902 offset > 0 && byte < n;
904 if (oword.eo_u8[offset - 1] != key[byte++]) {
910 /* Verify Toeplitz IPv6 hash key 2 */
911 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
912 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
913 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
914 offset > 0 && byte < n;
916 if (oword.eo_u8[offset - 1] != key[byte++]) {
922 /* Verify Toeplitz IPv6 hash key 1 */
923 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
924 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
925 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
926 offset > 0 && byte < n;
928 if (oword.eo_u8[offset - 1] != key[byte++]) {
944 EFSYS_PROBE1(fail1, efx_rc_t, rc);
950 #if EFSYS_OPT_RX_SCALE
951 static __checkReturn efx_rc_t
952 siena_rx_scale_tbl_set(
954 __in_ecount(n) unsigned int *table,
961 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
962 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
964 if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
969 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
972 /* Calculate the entry to place in the table */
973 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
975 EFSYS_PROBE2(table, int, index, uint32_t, byte);
977 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
979 /* Write the table */
980 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
981 index, &oword, B_TRUE);
984 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
987 /* Determine if we're starting a new batch */
988 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
991 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
992 index, &oword, B_TRUE);
994 /* Verify the entry */
995 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1006 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1013 * Falcon/Siena pseudo-header
1014 * --------------------------
1016 * Receive packets are prefixed by an optional 16 byte pseudo-header.
1017 * The pseudo-header is a byte array of one of the forms:
1019 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1020 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1021 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1024 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
1025 * LL.LL LFSR hash (16-bit big-endian)
1028 #if EFSYS_OPT_RX_SCALE
1029 static __checkReturn uint32_t
1030 siena_rx_prefix_hash(
1031 __in efx_nic_t *enp,
1032 __in efx_rx_hash_alg_t func,
1033 __in uint8_t *buffer)
1035 _NOTE(ARGUNUSED(enp))
1038 case EFX_RX_HASHALG_TOEPLITZ:
1039 return ((buffer[12] << 24) |
1040 (buffer[13] << 16) |
1044 case EFX_RX_HASHALG_LFSR:
1045 return ((buffer[14] << 8) | buffer[15]);
1052 #endif /* EFSYS_OPT_RX_SCALE */
1054 static __checkReturn efx_rc_t
1055 siena_rx_prefix_pktlen(
1056 __in efx_nic_t *enp,
1057 __in uint8_t *buffer,
1058 __out uint16_t *lengthp)
1060 _NOTE(ARGUNUSED(enp, buffer, lengthp))
1062 /* Not supported by Falcon/Siena hardware */
1070 __in efx_rxq_t *erp,
1071 __in_ecount(n) efsys_dma_addr_t *addrp,
1073 __in unsigned int n,
1074 __in unsigned int completed,
1075 __in unsigned int added)
1079 unsigned int offset;
1082 /* The client driver must not overfill the queue */
1083 EFSYS_ASSERT3U(added - completed + n, <=,
1084 EFX_RXQ_LIMIT(erp->er_mask + 1));
1086 id = added & (erp->er_mask);
1087 for (i = 0; i < n; i++) {
1088 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1089 unsigned int, id, efsys_dma_addr_t, addrp[i],
1092 EFX_POPULATE_QWORD_3(qword,
1093 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1094 FSF_AZ_RX_KER_BUF_ADDR_DW0,
1095 (uint32_t)(addrp[i] & 0xffffffff),
1096 FSF_AZ_RX_KER_BUF_ADDR_DW1,
1097 (uint32_t)(addrp[i] >> 32));
1099 offset = id * sizeof (efx_qword_t);
1100 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1102 id = (id + 1) & (erp->er_mask);
1108 __in efx_rxq_t *erp,
1109 __in unsigned int added,
1110 __inout unsigned int *pushedp)
1112 efx_nic_t *enp = erp->er_enp;
1113 unsigned int pushed = *pushedp;
1118 /* All descriptors are pushed */
1121 /* Push the populated descriptors out */
1122 wptr = added & erp->er_mask;
1124 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1126 /* Only write the third DWORD */
1127 EFX_POPULATE_DWORD_1(dword,
1128 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1130 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1131 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1132 wptr, pushed & erp->er_mask);
1133 EFSYS_PIO_WRITE_BARRIER();
1134 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1135 erp->er_index, &dword, B_FALSE);
1138 #if EFSYS_OPT_RX_PACKED_STREAM
1140 siena_rx_qps_update_credits(
1141 __in efx_rxq_t *erp)
1143 /* Not supported by Siena hardware */
1148 siena_rx_qps_packet_info(
1149 __in efx_rxq_t *erp,
1150 __in uint8_t *buffer,
1151 __in uint32_t buffer_length,
1152 __in uint32_t current_offset,
1153 __out uint16_t *lengthp,
1154 __out uint32_t *next_offsetp,
1155 __out uint32_t *timestamp)
1157 /* Not supported by Siena hardware */
1162 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1164 static __checkReturn efx_rc_t
1166 __in efx_rxq_t *erp)
1168 efx_nic_t *enp = erp->er_enp;
1172 label = erp->er_index;
1174 /* Flush the queue */
1175 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1176 FRF_AZ_RX_FLUSH_DESCQ, label);
1177 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1184 __in efx_rxq_t *erp)
1186 efx_nic_t *enp = erp->er_enp;
1189 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1191 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1192 erp->er_index, &oword, B_TRUE);
1194 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1195 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1196 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1198 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1199 erp->er_index, &oword, B_TRUE);
1202 static __checkReturn efx_rc_t
1204 __in efx_nic_t *enp,
1205 __in unsigned int index,
1206 __in unsigned int label,
1207 __in efx_rxq_type_t type,
1208 __in efsys_mem_t *esmp,
1211 __in efx_evq_t *eep,
1212 __in efx_rxq_t *erp)
1214 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1220 _NOTE(ARGUNUSED(esmp))
1222 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1223 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1224 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1225 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1227 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1228 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1230 if (!ISP2(n) || (n < EFX_RXQ_MINNDESCS) || (n > EFX_RXQ_MAXNDESCS)) {
1234 if (index >= encp->enc_rxq_limit) {
1238 for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1240 if ((1 << size) == (int)(n / EFX_RXQ_MINNDESCS))
1242 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1248 case EFX_RXQ_TYPE_DEFAULT:
1252 #if EFSYS_OPT_RX_SCATTER
1253 case EFX_RXQ_TYPE_SCATTER:
1254 if (enp->en_family < EFX_FAMILY_SIENA) {
1260 #endif /* EFSYS_OPT_RX_SCATTER */
1267 /* Set up the new descriptor queue */
1268 EFX_POPULATE_OWORD_7(oword,
1269 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1270 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1271 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1272 FRF_AZ_RX_DESCQ_LABEL, label,
1273 FRF_AZ_RX_DESCQ_SIZE, size,
1274 FRF_AZ_RX_DESCQ_TYPE, 0,
1275 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1277 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1278 erp->er_index, &oword, B_TRUE);
1289 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1296 __in efx_rxq_t *erp)
1298 efx_nic_t *enp = erp->er_enp;
1301 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1302 --enp->en_rx_qcount;
1304 /* Purge descriptor queue */
1305 EFX_ZERO_OWORD(oword);
1307 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1308 erp->er_index, &oword, B_TRUE);
1310 /* Free the RXQ object */
1311 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1316 __in efx_nic_t *enp)
1318 _NOTE(ARGUNUSED(enp))
1321 #endif /* EFSYS_OPT_SIENA */