1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
10 __checkReturn efx_rc_t
14 __in efsys_mem_t *esmp,
19 uint32_t stop = start + n;
20 efsys_dma_addr_t addr;
25 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
26 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
28 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
29 if (enp->en_family == EFX_FAMILY_HUNTINGTON ||
30 enp->en_family == EFX_FAMILY_MEDFORD) {
32 * FIXME: the efx_sram_buf_tbl_*() functionality needs to be
33 * pulled inside the Falcon/Siena queue create/destroy code,
34 * and then the original functions can be removed (see bug30834
35 * comment #1). But, for now, we just ensure that they are
36 * no-ops for EF10, to allow bringing up existing drivers
37 * without modification.
42 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
44 if (stop >= EFX_BUF_TBL_SIZE) {
49 /* Add the entries into the buffer table */
50 addr = EFSYS_MEM_ADDR(esmp);
51 for (id = start; id != stop; id++) {
52 EFX_POPULATE_QWORD_5(qword,
53 FRF_AZ_IP_DAT_BUF_SIZE, 0, FRF_AZ_BUF_ADR_REGION, 0,
54 FRF_AZ_BUF_ADR_FBUF_DW0,
55 (uint32_t)((addr >> 12) & 0xffffffff),
56 FRF_AZ_BUF_ADR_FBUF_DW1,
57 (uint32_t)((addr >> 12) >> 32),
58 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
60 EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_FULL_TBL,
66 EFSYS_PROBE2(buf, uint32_t, start, uint32_t, stop - 1);
68 /* Flush the write buffer */
69 EFX_POPULATE_OWORD_2(oword, FRF_AZ_BUF_UPD_CMD, 1,
70 FRF_AZ_BUF_CLR_CMD, 0);
71 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_UPD_REG, &oword);
73 /* Poll for the last entry being written to the buffer table */
74 EFSYS_ASSERT3U(id, ==, stop);
79 EFSYS_PROBE1(wait, unsigned int, count);
84 EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_FULL_TBL,
87 if (EFX_QWORD_FIELD(qword, FRF_AZ_BUF_ADR_FBUF_DW0) ==
88 (uint32_t)((addr >> 12) & 0xffffffff) &&
89 EFX_QWORD_FIELD(qword, FRF_AZ_BUF_ADR_FBUF_DW1) ==
90 (uint32_t)((addr >> 12) >> 32))
93 } while (++count < 100);
99 /* Verify the rest of the entries in the buffer table */
100 while (--id != start) {
101 addr -= EFX_BUF_SIZE;
103 /* Read the buffer table entry */
104 EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_FULL_TBL,
107 if (EFX_QWORD_FIELD(qword, FRF_AZ_BUF_ADR_FBUF_DW0) !=
108 (uint32_t)((addr >> 12) & 0xffffffff) ||
109 EFX_QWORD_FIELD(qword, FRF_AZ_BUF_ADR_FBUF_DW1) !=
110 (uint32_t)((addr >> 12) >> 32)) {
126 EFX_POPULATE_OWORD_4(oword, FRF_AZ_BUF_UPD_CMD, 0,
127 FRF_AZ_BUF_CLR_CMD, 1, FRF_AZ_BUF_CLR_END_ID, id - 1,
128 FRF_AZ_BUF_CLR_START_ID, start);
129 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_UPD_REG, &oword);
132 EFSYS_PROBE1(fail1, efx_rc_t, rc);
138 efx_sram_buf_tbl_clear(
145 uint32_t stop = start + n;
147 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
148 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
150 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
151 if (enp->en_family == EFX_FAMILY_HUNTINGTON ||
152 enp->en_family == EFX_FAMILY_MEDFORD) {
154 * FIXME: the efx_sram_buf_tbl_*() functionality needs to be
155 * pulled inside the Falcon/Siena queue create/destroy code,
156 * and then the original functions can be removed (see bug30834
157 * comment #1). But, for now, we just ensure that they are
158 * no-ops for EF10, to allow bringing up existing drivers
159 * without modification.
164 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
166 EFSYS_ASSERT3U(stop, <, EFX_BUF_TBL_SIZE);
168 EFSYS_PROBE2(buf, uint32_t, start, uint32_t, stop - 1);
170 EFX_POPULATE_OWORD_4(oword, FRF_AZ_BUF_UPD_CMD, 0,
171 FRF_AZ_BUF_CLR_CMD, 1, FRF_AZ_BUF_CLR_END_ID, stop - 1,
172 FRF_AZ_BUF_CLR_START_ID, start);
173 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_UPD_REG, &oword);
180 efx_sram_byte_increment_set(
182 __in boolean_t negate,
183 __out efx_qword_t *eqp)
185 size_t offset = row * FR_AZ_SRM_DBG_REG_STEP;
188 _NOTE(ARGUNUSED(negate))
190 for (index = 0; index < sizeof (efx_qword_t); index++)
191 eqp->eq_u8[index] = offset + index;
195 efx_sram_all_the_same_set(
197 __in boolean_t negate,
198 __out efx_qword_t *eqp)
200 _NOTE(ARGUNUSED(row))
205 EFX_ZERO_QWORD(*eqp);
209 efx_sram_bit_alternate_set(
211 __in boolean_t negate,
212 __out efx_qword_t *eqp)
214 _NOTE(ARGUNUSED(row))
216 EFX_POPULATE_QWORD_2(*eqp,
217 EFX_DWORD_0, (negate) ? 0x55555555 : 0xaaaaaaaa,
218 EFX_DWORD_1, (negate) ? 0x55555555 : 0xaaaaaaaa);
222 efx_sram_byte_alternate_set(
224 __in boolean_t negate,
225 __out efx_qword_t *eqp)
227 _NOTE(ARGUNUSED(row))
229 EFX_POPULATE_QWORD_2(*eqp,
230 EFX_DWORD_0, (negate) ? 0x00ff00ff : 0xff00ff00,
231 EFX_DWORD_1, (negate) ? 0x00ff00ff : 0xff00ff00);
235 efx_sram_byte_changing_set(
237 __in boolean_t negate,
238 __out efx_qword_t *eqp)
240 size_t offset = row * FR_AZ_SRM_DBG_REG_STEP;
243 for (index = 0; index < sizeof (efx_qword_t); index++) {
246 if (offset / 256 == 0)
247 byte = (uint8_t)((offset % 257) % 256);
249 byte = (uint8_t)(~((offset - 8) % 257) % 256);
251 eqp->eq_u8[index] = (negate) ? ~byte : byte;
256 efx_sram_bit_sweep_set(
258 __in boolean_t negate,
259 __out efx_qword_t *eqp)
261 size_t offset = row * FR_AZ_SRM_DBG_REG_STEP;
265 EFX_CLEAR_QWORD_BIT(*eqp, (offset / sizeof (efx_qword_t)) % 64);
267 EFX_ZERO_QWORD(*eqp);
268 EFX_SET_QWORD_BIT(*eqp, (offset / sizeof (efx_qword_t)) % 64);
272 efx_sram_pattern_fn_t __efx_sram_pattern_fns[] = {
273 efx_sram_byte_increment_set,
274 efx_sram_all_the_same_set,
275 efx_sram_bit_alternate_set,
276 efx_sram_byte_alternate_set,
277 efx_sram_byte_changing_set,
278 efx_sram_bit_sweep_set
281 __checkReturn efx_rc_t
284 __in efx_pattern_type_t type)
286 efx_sram_pattern_fn_t func;
288 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
290 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
292 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
293 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
294 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
296 /* SRAM testing is only available on Siena. */
297 if (enp->en_family != EFX_FAMILY_SIENA)
300 /* Select pattern generator */
301 EFSYS_ASSERT3U(type, <, EFX_PATTERN_NTYPES);
302 func = __efx_sram_pattern_fns[type];
304 return (siena_sram_test(enp, func));
307 #endif /* EFSYS_OPT_DIAG */