1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2007-2019 Solarflare Communications Inc.
10 __checkReturn efx_rc_t
14 __in efsys_mem_t *esmp,
19 uint32_t stop = start + n;
20 efsys_dma_addr_t addr;
25 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
26 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
29 if (EFX_FAMILY_IS_EF10(enp)) {
31 * FIXME: the efx_sram_buf_tbl_*() functionality needs to be
32 * pulled inside the Falcon/Siena queue create/destroy code,
33 * and then the original functions can be removed (see bug30834
34 * comment #1). But, for now, we just ensure that they are
35 * no-ops for EF10, to allow bringing up existing drivers
36 * without modification.
41 #endif /* EFX_OPTS_EF10() */
43 if (stop >= EFX_BUF_TBL_SIZE) {
48 /* Add the entries into the buffer table */
49 addr = EFSYS_MEM_ADDR(esmp);
50 for (id = start; id != stop; id++) {
51 EFX_POPULATE_QWORD_5(qword,
52 FRF_AZ_IP_DAT_BUF_SIZE, 0, FRF_AZ_BUF_ADR_REGION, 0,
53 FRF_AZ_BUF_ADR_FBUF_DW0,
54 (uint32_t)((addr >> 12) & 0xffffffff),
55 FRF_AZ_BUF_ADR_FBUF_DW1,
56 (uint32_t)((addr >> 12) >> 32),
57 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
59 EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_FULL_TBL,
65 EFSYS_PROBE2(buf, uint32_t, start, uint32_t, stop - 1);
67 /* Flush the write buffer */
68 EFX_POPULATE_OWORD_2(oword, FRF_AZ_BUF_UPD_CMD, 1,
69 FRF_AZ_BUF_CLR_CMD, 0);
70 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_UPD_REG, &oword);
72 /* Poll for the last entry being written to the buffer table */
73 EFSYS_ASSERT3U(id, ==, stop);
78 EFSYS_PROBE1(wait, unsigned int, count);
83 EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_FULL_TBL,
86 if (EFX_QWORD_FIELD(qword, FRF_AZ_BUF_ADR_FBUF_DW0) ==
87 (uint32_t)((addr >> 12) & 0xffffffff) &&
88 EFX_QWORD_FIELD(qword, FRF_AZ_BUF_ADR_FBUF_DW1) ==
89 (uint32_t)((addr >> 12) >> 32))
92 } while (++count < 100);
98 /* Verify the rest of the entries in the buffer table */
99 while (--id != start) {
100 addr -= EFX_BUF_SIZE;
102 /* Read the buffer table entry */
103 EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_FULL_TBL,
106 if (EFX_QWORD_FIELD(qword, FRF_AZ_BUF_ADR_FBUF_DW0) !=
107 (uint32_t)((addr >> 12) & 0xffffffff) ||
108 EFX_QWORD_FIELD(qword, FRF_AZ_BUF_ADR_FBUF_DW1) !=
109 (uint32_t)((addr >> 12) >> 32)) {
125 EFX_POPULATE_OWORD_4(oword, FRF_AZ_BUF_UPD_CMD, 0,
126 FRF_AZ_BUF_CLR_CMD, 1, FRF_AZ_BUF_CLR_END_ID, id - 1,
127 FRF_AZ_BUF_CLR_START_ID, start);
128 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_UPD_REG, &oword);
131 EFSYS_PROBE1(fail1, efx_rc_t, rc);
137 efx_sram_buf_tbl_clear(
144 uint32_t stop = start + n;
146 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
147 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
150 if (EFX_FAMILY_IS_EF10(enp)) {
152 * FIXME: the efx_sram_buf_tbl_*() functionality needs to be
153 * pulled inside the Falcon/Siena queue create/destroy code,
154 * and then the original functions can be removed (see bug30834
155 * comment #1). But, for now, we just ensure that they are
156 * no-ops for EF10, to allow bringing up existing drivers
157 * without modification.
162 #endif /* EFX_OPTS_EF10() */
164 EFSYS_ASSERT3U(stop, <, EFX_BUF_TBL_SIZE);
166 EFSYS_PROBE2(buf, uint32_t, start, uint32_t, stop - 1);
168 EFX_POPULATE_OWORD_4(oword, FRF_AZ_BUF_UPD_CMD, 0,
169 FRF_AZ_BUF_CLR_CMD, 1, FRF_AZ_BUF_CLR_END_ID, stop - 1,
170 FRF_AZ_BUF_CLR_START_ID, start);
171 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_UPD_REG, &oword);
178 efx_sram_byte_increment_set(
180 __in boolean_t negate,
181 __out efx_qword_t *eqp)
183 size_t offset = row * FR_AZ_SRM_DBG_REG_STEP;
186 _NOTE(ARGUNUSED(negate))
188 for (index = 0; index < sizeof (efx_qword_t); index++)
189 eqp->eq_u8[index] = offset + index;
193 efx_sram_all_the_same_set(
195 __in boolean_t negate,
196 __out efx_qword_t *eqp)
198 _NOTE(ARGUNUSED(row))
203 EFX_ZERO_QWORD(*eqp);
207 efx_sram_bit_alternate_set(
209 __in boolean_t negate,
210 __out efx_qword_t *eqp)
212 _NOTE(ARGUNUSED(row))
214 EFX_POPULATE_QWORD_2(*eqp,
215 EFX_DWORD_0, (negate) ? 0x55555555 : 0xaaaaaaaa,
216 EFX_DWORD_1, (negate) ? 0x55555555 : 0xaaaaaaaa);
220 efx_sram_byte_alternate_set(
222 __in boolean_t negate,
223 __out efx_qword_t *eqp)
225 _NOTE(ARGUNUSED(row))
227 EFX_POPULATE_QWORD_2(*eqp,
228 EFX_DWORD_0, (negate) ? 0x00ff00ff : 0xff00ff00,
229 EFX_DWORD_1, (negate) ? 0x00ff00ff : 0xff00ff00);
233 efx_sram_byte_changing_set(
235 __in boolean_t negate,
236 __out efx_qword_t *eqp)
238 size_t offset = row * FR_AZ_SRM_DBG_REG_STEP;
241 for (index = 0; index < sizeof (efx_qword_t); index++) {
244 if (offset / 256 == 0)
245 byte = (uint8_t)((offset % 257) % 256);
247 byte = (uint8_t)(~((offset - 8) % 257) % 256);
249 eqp->eq_u8[index] = (negate) ? ~byte : byte;
254 efx_sram_bit_sweep_set(
256 __in boolean_t negate,
257 __out efx_qword_t *eqp)
259 size_t offset = row * FR_AZ_SRM_DBG_REG_STEP;
263 EFX_CLEAR_QWORD_BIT(*eqp, (offset / sizeof (efx_qword_t)) % 64);
265 EFX_ZERO_QWORD(*eqp);
266 EFX_SET_QWORD_BIT(*eqp, (offset / sizeof (efx_qword_t)) % 64);
270 efx_sram_pattern_fn_t __efx_sram_pattern_fns[] = {
271 efx_sram_byte_increment_set,
272 efx_sram_all_the_same_set,
273 efx_sram_bit_alternate_set,
274 efx_sram_byte_alternate_set,
275 efx_sram_byte_changing_set,
276 efx_sram_bit_sweep_set
279 __checkReturn efx_rc_t
282 __in efx_pattern_type_t type)
284 efx_sram_pattern_fn_t func;
286 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
288 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
290 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
291 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
292 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
294 /* SRAM testing is only available on Siena. */
295 if (enp->en_family != EFX_FAMILY_SIENA)
298 /* Select pattern generator */
299 EFSYS_ASSERT3U(type, <, EFX_PATTERN_NTYPES);
300 func = __efx_sram_pattern_fns[type];
302 return (siena_sram_test(enp, func));
305 #endif /* EFSYS_OPT_DIAG */