1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
13 #if EFSYS_OPT_HUNTINGTON
15 #include "ef10_tlv_layout.h"
17 static __checkReturn efx_rc_t
18 hunt_nic_get_required_pcie_bandwidth(
20 __out uint32_t *bandwidth_mbpsp)
23 uint32_t max_port_mode;
28 * On Huntington, the firmware may not give us the current port mode, so
29 * we need to go by the set of available port modes and assume the most
30 * capable mode is in use.
33 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, NULL)) != 0) {
34 /* No port mode info available */
39 if (port_modes & (1 << TLV_PORT_MODE_40G_40G)) {
41 * This needs the full PCIe bandwidth (and could use
42 * more) - roughly 64 Gbit/s for 8 lanes of Gen3.
44 if ((rc = efx_nic_calculate_pcie_link_bandwidth(8,
45 EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)
48 if (port_modes & (1 << TLV_PORT_MODE_40G)) {
49 max_port_mode = TLV_PORT_MODE_40G;
50 } else if (port_modes & (1 << TLV_PORT_MODE_10G_10G_10G_10G)) {
51 max_port_mode = TLV_PORT_MODE_10G_10G_10G_10G;
53 /* Assume two 10G ports */
54 max_port_mode = TLV_PORT_MODE_10G_10G;
57 if ((rc = ef10_nic_get_port_mode_bandwidth(max_port_mode,
63 *bandwidth_mbpsp = bandwidth;
70 EFSYS_PROBE1(fail1, efx_rc_t, rc);
75 __checkReturn efx_rc_t
79 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
80 efx_port_t *epp = &(enp->en_port);
82 uint32_t sysclk, dpcpu_clk;
86 /* Huntington has a fixed 8Kbyte VI window size */
87 EFX_STATIC_ASSERT(ER_DZ_EVQ_RPTR_REG_STEP == 8192);
88 EFX_STATIC_ASSERT(ER_DZ_EVQ_TMR_REG_STEP == 8192);
89 EFX_STATIC_ASSERT(ER_DZ_RX_DESC_UPD_REG_STEP == 8192);
90 EFX_STATIC_ASSERT(ER_DZ_TX_DESC_UPD_REG_STEP == 8192);
91 EFX_STATIC_ASSERT(ER_DZ_TX_PIOBUF_STEP == 8192);
93 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
94 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
97 * Enable firmware workarounds for hardware errata.
98 * Expected responses are:
100 * Success: workaround enabled or disabled as requested.
101 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
102 * Firmware does not support the MC_CMD_WORKAROUND request.
103 * (assume that the workaround is not supported).
104 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
105 * Firmware does not support the requested workaround.
106 * - MC_CMD_ERR_EPERM (reported as EACCES):
107 * Unprivileged function cannot enable/disable workarounds.
109 * See efx_mcdi_request_errcode() for MCDI error translations.
113 * If the bug35388 workaround is enabled, then use an indirect access
114 * method to avoid unsafe EVQ writes.
116 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
118 if ((rc == 0) || (rc == EACCES))
119 encp->enc_bug35388_workaround = B_TRUE;
120 else if ((rc == ENOTSUP) || (rc == ENOENT))
121 encp->enc_bug35388_workaround = B_FALSE;
126 * If the bug41750 workaround is enabled, then do not test interrupts,
127 * as the test will fail (seen with Greenport controllers).
129 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
132 encp->enc_bug41750_workaround = B_TRUE;
133 } else if (rc == EACCES) {
134 /* Assume a controller with 40G ports needs the workaround. */
135 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
136 encp->enc_bug41750_workaround = B_TRUE;
138 encp->enc_bug41750_workaround = B_FALSE;
139 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
140 encp->enc_bug41750_workaround = B_FALSE;
144 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
145 /* Interrupt testing does not work for VFs. See bug50084. */
146 encp->enc_bug41750_workaround = B_TRUE;
150 * If the bug26807 workaround is enabled, then firmware has enabled
151 * support for chained multicast filters. Firmware will reset (FLR)
152 * functions which have filters in the hardware filter table when the
153 * workaround is enabled/disabled.
155 * We must recheck if the workaround is enabled after inserting the
156 * first hardware filter, in case it has been changed since this check.
158 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
161 encp->enc_bug26807_workaround = B_TRUE;
162 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
164 * Other functions had installed filters before the
165 * workaround was enabled, and they have been reset
168 EFSYS_PROBE(bug26807_workaround_flr_done);
169 /* FIXME: bump MC warm boot count ? */
171 } else if (rc == EACCES) {
173 * Unprivileged functions cannot enable the workaround in older
176 encp->enc_bug26807_workaround = B_FALSE;
177 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
178 encp->enc_bug26807_workaround = B_FALSE;
183 /* Get clock frequencies (in MHz). */
184 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
188 * The Huntington timer quantum is 1536 sysclk cycles, documented for
189 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
191 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
192 if (encp->enc_bug35388_workaround) {
193 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
194 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
196 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
197 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
200 encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
202 /* Alignment for receive packet DMA buffers */
203 encp->enc_rx_buf_align_start = 1;
204 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
207 * The workaround for bug35388 uses the top bit of transmit queue
208 * descriptor writes, preventing the use of 4096 descriptor TXQs.
210 encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
212 EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
213 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
214 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
215 encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
217 if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
219 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
221 /* All Huntington devices have a PCIe Gen3, 8 lane connector */
222 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
235 EFSYS_PROBE1(fail1, efx_rc_t, rc);
241 #endif /* EFSYS_OPT_HUNTINGTON */