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33 #if EFSYS_OPT_MON_MCDI
37 #if EFSYS_OPT_HUNTINGTON
39 #include "ef10_tlv_layout.h"
41 static __checkReturn efx_rc_t
42 hunt_nic_get_required_pcie_bandwidth(
44 __out uint32_t *bandwidth_mbpsp)
47 uint32_t max_port_mode;
52 * On Huntington, the firmware may not give us the current port mode, so
53 * we need to go by the set of available port modes and assume the most
54 * capable mode is in use.
57 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, NULL)) != 0) {
58 /* No port mode info available */
63 if (port_modes & (1 << TLV_PORT_MODE_40G_40G)) {
65 * This needs the full PCIe bandwidth (and could use
66 * more) - roughly 64 Gbit/s for 8 lanes of Gen3.
68 if ((rc = efx_nic_calculate_pcie_link_bandwidth(8,
69 EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)
72 if (port_modes & (1 << TLV_PORT_MODE_40G)) {
73 max_port_mode = TLV_PORT_MODE_40G;
74 } else if (port_modes & (1 << TLV_PORT_MODE_10G_10G_10G_10G)) {
75 max_port_mode = TLV_PORT_MODE_10G_10G_10G_10G;
77 /* Assume two 10G ports */
78 max_port_mode = TLV_PORT_MODE_10G_10G;
81 if ((rc = ef10_nic_get_port_mode_bandwidth(max_port_mode,
87 *bandwidth_mbpsp = bandwidth;
94 EFSYS_PROBE1(fail1, efx_rc_t, rc);
99 __checkReturn efx_rc_t
103 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
104 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
105 uint8_t mac_addr[6] = { 0 };
106 uint32_t board_type = 0;
107 ef10_link_state_t els;
108 efx_port_t *epp = &(enp->en_port);
114 uint32_t sysclk, dpcpu_clk;
119 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
123 * NOTE: The MCDI protocol numbers ports from zero.
124 * The common code MCDI interface numbers ports from one.
126 emip->emi_port = port + 1;
128 if ((rc = ef10_external_port_mapping(enp, port,
129 &encp->enc_external_port)) != 0)
133 * Get PCIe function number from firmware (used for
134 * per-function privilege and dynamic config info).
135 * - PCIe PF: pf = PF number, vf = 0xffff.
136 * - PCIe VF: pf = parent PF, vf = VF number.
138 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
144 /* MAC address for this function */
145 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
146 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
147 if ((rc == 0) && (mac_addr[0] & 0x02)) {
149 * If the static config does not include a global MAC
150 * address pool then the board may return a locally
151 * administered MAC address (this should only happen on
152 * incorrectly programmed boards).
157 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
162 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
164 /* Board configuration */
165 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
167 /* Unprivileged functions may not be able to read board cfg */
174 encp->enc_board_type = board_type;
175 encp->enc_clk_mult = 1; /* not used for Huntington */
177 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
178 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
181 /* Obtain the default PHY advertised capabilities */
182 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
184 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
185 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
188 * Enable firmware workarounds for hardware errata.
189 * Expected responses are:
191 * Success: workaround enabled or disabled as requested.
192 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
193 * Firmware does not support the MC_CMD_WORKAROUND request.
194 * (assume that the workaround is not supported).
195 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
196 * Firmware does not support the requested workaround.
197 * - MC_CMD_ERR_EPERM (reported as EACCES):
198 * Unprivileged function cannot enable/disable workarounds.
200 * See efx_mcdi_request_errcode() for MCDI error translations.
204 * If the bug35388 workaround is enabled, then use an indirect access
205 * method to avoid unsafe EVQ writes.
207 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
209 if ((rc == 0) || (rc == EACCES))
210 encp->enc_bug35388_workaround = B_TRUE;
211 else if ((rc == ENOTSUP) || (rc == ENOENT))
212 encp->enc_bug35388_workaround = B_FALSE;
217 * If the bug41750 workaround is enabled, then do not test interrupts,
218 * as the test will fail (seen with Greenport controllers).
220 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
223 encp->enc_bug41750_workaround = B_TRUE;
224 } else if (rc == EACCES) {
225 /* Assume a controller with 40G ports needs the workaround. */
226 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
227 encp->enc_bug41750_workaround = B_TRUE;
229 encp->enc_bug41750_workaround = B_FALSE;
230 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
231 encp->enc_bug41750_workaround = B_FALSE;
235 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
236 /* Interrupt testing does not work for VFs. See bug50084. */
237 encp->enc_bug41750_workaround = B_TRUE;
241 * If the bug26807 workaround is enabled, then firmware has enabled
242 * support for chained multicast filters. Firmware will reset (FLR)
243 * functions which have filters in the hardware filter table when the
244 * workaround is enabled/disabled.
246 * We must recheck if the workaround is enabled after inserting the
247 * first hardware filter, in case it has been changed since this check.
249 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
252 encp->enc_bug26807_workaround = B_TRUE;
253 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
255 * Other functions had installed filters before the
256 * workaround was enabled, and they have been reset
259 EFSYS_PROBE(bug26807_workaround_flr_done);
260 /* FIXME: bump MC warm boot count ? */
262 } else if (rc == EACCES) {
264 * Unprivileged functions cannot enable the workaround in older
267 encp->enc_bug26807_workaround = B_FALSE;
268 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
269 encp->enc_bug26807_workaround = B_FALSE;
274 /* Get clock frequencies (in MHz). */
275 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
279 * The Huntington timer quantum is 1536 sysclk cycles, documented for
280 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
282 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
283 if (encp->enc_bug35388_workaround) {
284 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
285 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
287 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
288 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
291 encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
293 /* Check capabilities of running datapath firmware */
294 if ((rc = ef10_get_datapath_caps(enp)) != 0)
297 /* Alignment for receive packet DMA buffers */
298 encp->enc_rx_buf_align_start = 1;
299 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
301 /* Alignment for WPTR updates */
302 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
305 * Maximum number of exclusive RSS contexts which can be allocated. The
306 * hardware supports 64, but 6 are reserved for shared contexts. They
307 * are a global resource so not all may be available.
309 encp->enc_rx_scale_max_exclusive_contexts = 58;
311 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
312 /* No boundary crossing limits */
313 encp->enc_tx_dma_desc_boundary = 0;
316 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
317 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
318 * resources (allocated to this PCIe function), which is zero until
319 * after we have allocated VIs.
321 encp->enc_evq_limit = 1024;
322 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
323 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
326 * The workaround for bug35388 uses the top bit of transmit queue
327 * descriptor writes, preventing the use of 4096 descriptor TXQs.
329 encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
331 encp->enc_buftbl_limit = 0xFFFFFFFF;
333 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
334 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
335 encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
338 * Get the current privilege mask. Note that this may be modified
339 * dynamically, so this value is informational only. DO NOT use
340 * the privilege mask to check for sufficient privileges, as that
341 * can result in time-of-check/time-of-use bugs.
343 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
345 encp->enc_privilege_mask = mask;
347 /* Get interrupt vector limits */
348 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
349 if (EFX_PCI_FUNCTION_IS_PF(encp))
352 /* Ignore error (cannot query vector limits from a VF). */
356 encp->enc_intr_vec_base = base;
357 encp->enc_intr_limit = nvec;
360 * Maximum number of bytes into the frame the TCP header can start for
361 * firmware assisted TSO to work.
363 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
365 if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
367 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
369 /* All Huntington devices have a PCIe Gen3, 8 lane connector */
370 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
403 EFSYS_PROBE1(fail1, efx_rc_t, rc);
409 #endif /* EFSYS_OPT_HUNTINGTON */