1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
13 #if EFSYS_OPT_HUNTINGTON
15 #include "ef10_tlv_layout.h"
17 static __checkReturn efx_rc_t
18 hunt_nic_get_required_pcie_bandwidth(
20 __out uint32_t *bandwidth_mbpsp)
23 uint32_t max_port_mode;
28 * On Huntington, the firmware may not give us the current port mode, so
29 * we need to go by the set of available port modes and assume the most
30 * capable mode is in use.
33 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, NULL)) != 0) {
34 /* No port mode info available */
39 if (port_modes & (1 << TLV_PORT_MODE_40G_40G)) {
41 * This needs the full PCIe bandwidth (and could use
42 * more) - roughly 64 Gbit/s for 8 lanes of Gen3.
44 if ((rc = efx_nic_calculate_pcie_link_bandwidth(8,
45 EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)
48 if (port_modes & (1 << TLV_PORT_MODE_40G)) {
49 max_port_mode = TLV_PORT_MODE_40G;
50 } else if (port_modes & (1 << TLV_PORT_MODE_10G_10G_10G_10G)) {
51 max_port_mode = TLV_PORT_MODE_10G_10G_10G_10G;
53 /* Assume two 10G ports */
54 max_port_mode = TLV_PORT_MODE_10G_10G;
57 if ((rc = ef10_nic_get_port_mode_bandwidth(max_port_mode,
63 *bandwidth_mbpsp = bandwidth;
70 EFSYS_PROBE1(fail1, efx_rc_t, rc);
75 __checkReturn efx_rc_t
79 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
80 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
81 uint8_t mac_addr[6] = { 0 };
82 uint32_t board_type = 0;
83 ef10_link_state_t els;
84 efx_port_t *epp = &(enp->en_port);
90 uint32_t sysclk, dpcpu_clk;
95 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
99 * NOTE: The MCDI protocol numbers ports from zero.
100 * The common code MCDI interface numbers ports from one.
102 emip->emi_port = port + 1;
104 if ((rc = ef10_external_port_mapping(enp, port,
105 &encp->enc_external_port)) != 0)
109 * Get PCIe function number from firmware (used for
110 * per-function privilege and dynamic config info).
111 * - PCIe PF: pf = PF number, vf = 0xffff.
112 * - PCIe VF: pf = parent PF, vf = VF number.
114 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
120 /* MAC address for this function */
121 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
122 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
123 if ((rc == 0) && (mac_addr[0] & 0x02)) {
125 * If the static config does not include a global MAC
126 * address pool then the board may return a locally
127 * administered MAC address (this should only happen on
128 * incorrectly programmed boards).
133 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
138 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
140 /* Board configuration */
141 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
143 /* Unprivileged functions may not be able to read board cfg */
150 encp->enc_board_type = board_type;
151 encp->enc_clk_mult = 1; /* not used for Huntington */
153 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
154 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
157 /* Obtain the default PHY advertised capabilities */
158 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
160 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
161 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
164 * Enable firmware workarounds for hardware errata.
165 * Expected responses are:
167 * Success: workaround enabled or disabled as requested.
168 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
169 * Firmware does not support the MC_CMD_WORKAROUND request.
170 * (assume that the workaround is not supported).
171 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
172 * Firmware does not support the requested workaround.
173 * - MC_CMD_ERR_EPERM (reported as EACCES):
174 * Unprivileged function cannot enable/disable workarounds.
176 * See efx_mcdi_request_errcode() for MCDI error translations.
180 * If the bug35388 workaround is enabled, then use an indirect access
181 * method to avoid unsafe EVQ writes.
183 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
185 if ((rc == 0) || (rc == EACCES))
186 encp->enc_bug35388_workaround = B_TRUE;
187 else if ((rc == ENOTSUP) || (rc == ENOENT))
188 encp->enc_bug35388_workaround = B_FALSE;
193 * If the bug41750 workaround is enabled, then do not test interrupts,
194 * as the test will fail (seen with Greenport controllers).
196 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
199 encp->enc_bug41750_workaround = B_TRUE;
200 } else if (rc == EACCES) {
201 /* Assume a controller with 40G ports needs the workaround. */
202 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
203 encp->enc_bug41750_workaround = B_TRUE;
205 encp->enc_bug41750_workaround = B_FALSE;
206 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
207 encp->enc_bug41750_workaround = B_FALSE;
211 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
212 /* Interrupt testing does not work for VFs. See bug50084. */
213 encp->enc_bug41750_workaround = B_TRUE;
217 * If the bug26807 workaround is enabled, then firmware has enabled
218 * support for chained multicast filters. Firmware will reset (FLR)
219 * functions which have filters in the hardware filter table when the
220 * workaround is enabled/disabled.
222 * We must recheck if the workaround is enabled after inserting the
223 * first hardware filter, in case it has been changed since this check.
225 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
228 encp->enc_bug26807_workaround = B_TRUE;
229 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
231 * Other functions had installed filters before the
232 * workaround was enabled, and they have been reset
235 EFSYS_PROBE(bug26807_workaround_flr_done);
236 /* FIXME: bump MC warm boot count ? */
238 } else if (rc == EACCES) {
240 * Unprivileged functions cannot enable the workaround in older
243 encp->enc_bug26807_workaround = B_FALSE;
244 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
245 encp->enc_bug26807_workaround = B_FALSE;
250 /* Get clock frequencies (in MHz). */
251 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
255 * The Huntington timer quantum is 1536 sysclk cycles, documented for
256 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
258 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
259 if (encp->enc_bug35388_workaround) {
260 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
261 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
263 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
264 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
267 encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
269 /* Check capabilities of running datapath firmware */
270 if ((rc = ef10_get_datapath_caps(enp)) != 0)
273 /* Alignment for receive packet DMA buffers */
274 encp->enc_rx_buf_align_start = 1;
275 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
277 /* Alignment for WPTR updates */
278 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
281 * Maximum number of exclusive RSS contexts which can be allocated. The
282 * hardware supports 64, but 6 are reserved for shared contexts. They
283 * are a global resource so not all may be available.
285 encp->enc_rx_scale_max_exclusive_contexts = 58;
287 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
288 /* No boundary crossing limits */
289 encp->enc_tx_dma_desc_boundary = 0;
292 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
293 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
294 * resources (allocated to this PCIe function), which is zero until
295 * after we have allocated VIs.
297 encp->enc_evq_limit = 1024;
298 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
299 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
302 * The workaround for bug35388 uses the top bit of transmit queue
303 * descriptor writes, preventing the use of 4096 descriptor TXQs.
305 encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
307 encp->enc_buftbl_limit = 0xFFFFFFFF;
309 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
310 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
311 encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
314 * Get the current privilege mask. Note that this may be modified
315 * dynamically, so this value is informational only. DO NOT use
316 * the privilege mask to check for sufficient privileges, as that
317 * can result in time-of-check/time-of-use bugs.
319 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
321 encp->enc_privilege_mask = mask;
323 /* Get interrupt vector limits */
324 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
325 if (EFX_PCI_FUNCTION_IS_PF(encp))
328 /* Ignore error (cannot query vector limits from a VF). */
332 encp->enc_intr_vec_base = base;
333 encp->enc_intr_limit = nvec;
336 * Maximum number of bytes into the frame the TCP header can start for
337 * firmware assisted TSO to work.
339 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
341 if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
343 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
345 /* All Huntington devices have a PCIe Gen3, 8 lane connector */
346 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
379 EFSYS_PROBE1(fail1, efx_rc_t, rc);
385 #endif /* EFSYS_OPT_HUNTINGTON */