1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
13 #if EFSYS_OPT_HUNTINGTON
15 #include "ef10_tlv_layout.h"
17 static __checkReturn efx_rc_t
18 hunt_nic_get_required_pcie_bandwidth(
20 __out uint32_t *bandwidth_mbpsp)
23 uint32_t max_port_mode;
28 * On Huntington, the firmware may not give us the current port mode, so
29 * we need to go by the set of available port modes and assume the most
30 * capable mode is in use.
33 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, NULL)) != 0) {
34 /* No port mode info available */
39 if (port_modes & (1 << TLV_PORT_MODE_40G_40G)) {
41 * This needs the full PCIe bandwidth (and could use
42 * more) - roughly 64 Gbit/s for 8 lanes of Gen3.
44 if ((rc = efx_nic_calculate_pcie_link_bandwidth(8,
45 EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)
48 if (port_modes & (1 << TLV_PORT_MODE_40G)) {
49 max_port_mode = TLV_PORT_MODE_40G;
50 } else if (port_modes & (1 << TLV_PORT_MODE_10G_10G_10G_10G)) {
51 max_port_mode = TLV_PORT_MODE_10G_10G_10G_10G;
53 /* Assume two 10G ports */
54 max_port_mode = TLV_PORT_MODE_10G_10G;
57 if ((rc = ef10_nic_get_port_mode_bandwidth(max_port_mode,
63 *bandwidth_mbpsp = bandwidth;
70 EFSYS_PROBE1(fail1, efx_rc_t, rc);
75 __checkReturn efx_rc_t
79 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
80 uint8_t mac_addr[6] = { 0 };
81 uint32_t board_type = 0;
82 ef10_link_state_t els;
83 efx_port_t *epp = &(enp->en_port);
88 uint32_t sysclk, dpcpu_clk;
93 /* Huntington has a fixed 8Kbyte VI window size */
94 EFX_STATIC_ASSERT(ER_DZ_EVQ_RPTR_REG_STEP == 8192);
95 EFX_STATIC_ASSERT(ER_DZ_EVQ_TMR_REG_STEP == 8192);
96 EFX_STATIC_ASSERT(ER_DZ_RX_DESC_UPD_REG_STEP == 8192);
97 EFX_STATIC_ASSERT(ER_DZ_TX_DESC_UPD_REG_STEP == 8192);
98 EFX_STATIC_ASSERT(ER_DZ_TX_PIOBUF_STEP == 8192);
100 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
101 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
104 * Get PCIe function number from firmware (used for
105 * per-function privilege and dynamic config info).
106 * - PCIe PF: pf = PF number, vf = 0xffff.
107 * - PCIe VF: pf = parent PF, vf = VF number.
109 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
115 /* MAC address for this function */
116 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
117 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
118 if ((rc == 0) && (mac_addr[0] & 0x02)) {
120 * If the static config does not include a global MAC
121 * address pool then the board may return a locally
122 * administered MAC address (this should only happen on
123 * incorrectly programmed boards).
128 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
133 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
135 /* Board configuration */
136 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
138 /* Unprivileged functions may not be able to read board cfg */
145 encp->enc_board_type = board_type;
146 encp->enc_clk_mult = 1; /* not used for Huntington */
148 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
149 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
152 /* Obtain the default PHY advertised capabilities */
153 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
155 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
156 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
159 * Enable firmware workarounds for hardware errata.
160 * Expected responses are:
162 * Success: workaround enabled or disabled as requested.
163 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
164 * Firmware does not support the MC_CMD_WORKAROUND request.
165 * (assume that the workaround is not supported).
166 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
167 * Firmware does not support the requested workaround.
168 * - MC_CMD_ERR_EPERM (reported as EACCES):
169 * Unprivileged function cannot enable/disable workarounds.
171 * See efx_mcdi_request_errcode() for MCDI error translations.
175 * If the bug35388 workaround is enabled, then use an indirect access
176 * method to avoid unsafe EVQ writes.
178 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
180 if ((rc == 0) || (rc == EACCES))
181 encp->enc_bug35388_workaround = B_TRUE;
182 else if ((rc == ENOTSUP) || (rc == ENOENT))
183 encp->enc_bug35388_workaround = B_FALSE;
188 * If the bug41750 workaround is enabled, then do not test interrupts,
189 * as the test will fail (seen with Greenport controllers).
191 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
194 encp->enc_bug41750_workaround = B_TRUE;
195 } else if (rc == EACCES) {
196 /* Assume a controller with 40G ports needs the workaround. */
197 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
198 encp->enc_bug41750_workaround = B_TRUE;
200 encp->enc_bug41750_workaround = B_FALSE;
201 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
202 encp->enc_bug41750_workaround = B_FALSE;
206 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
207 /* Interrupt testing does not work for VFs. See bug50084. */
208 encp->enc_bug41750_workaround = B_TRUE;
212 * If the bug26807 workaround is enabled, then firmware has enabled
213 * support for chained multicast filters. Firmware will reset (FLR)
214 * functions which have filters in the hardware filter table when the
215 * workaround is enabled/disabled.
217 * We must recheck if the workaround is enabled after inserting the
218 * first hardware filter, in case it has been changed since this check.
220 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
223 encp->enc_bug26807_workaround = B_TRUE;
224 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
226 * Other functions had installed filters before the
227 * workaround was enabled, and they have been reset
230 EFSYS_PROBE(bug26807_workaround_flr_done);
231 /* FIXME: bump MC warm boot count ? */
233 } else if (rc == EACCES) {
235 * Unprivileged functions cannot enable the workaround in older
238 encp->enc_bug26807_workaround = B_FALSE;
239 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
240 encp->enc_bug26807_workaround = B_FALSE;
245 /* Get clock frequencies (in MHz). */
246 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
250 * The Huntington timer quantum is 1536 sysclk cycles, documented for
251 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
253 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
254 if (encp->enc_bug35388_workaround) {
255 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
256 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
258 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
259 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
262 encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
264 /* Check capabilities of running datapath firmware */
265 if ((rc = ef10_get_datapath_caps(enp)) != 0)
268 /* Alignment for receive packet DMA buffers */
269 encp->enc_rx_buf_align_start = 1;
270 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
272 /* Alignment for WPTR updates */
273 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
276 * Maximum number of exclusive RSS contexts which can be allocated. The
277 * hardware supports 64, but 6 are reserved for shared contexts. They
278 * are a global resource so not all may be available.
280 encp->enc_rx_scale_max_exclusive_contexts = 58;
282 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
283 /* No boundary crossing limits */
284 encp->enc_tx_dma_desc_boundary = 0;
287 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
288 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
289 * resources (allocated to this PCIe function), which is zero until
290 * after we have allocated VIs.
292 encp->enc_evq_limit = 1024;
293 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
294 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
297 * The workaround for bug35388 uses the top bit of transmit queue
298 * descriptor writes, preventing the use of 4096 descriptor TXQs.
300 encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
302 encp->enc_buftbl_limit = 0xFFFFFFFF;
304 EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
305 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
306 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
307 encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
310 * Get the current privilege mask. Note that this may be modified
311 * dynamically, so this value is informational only. DO NOT use
312 * the privilege mask to check for sufficient privileges, as that
313 * can result in time-of-check/time-of-use bugs.
315 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
317 encp->enc_privilege_mask = mask;
319 /* Get interrupt vector limits */
320 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
321 if (EFX_PCI_FUNCTION_IS_PF(encp))
324 /* Ignore error (cannot query vector limits from a VF). */
328 encp->enc_intr_vec_base = base;
329 encp->enc_intr_limit = nvec;
332 * Maximum number of bytes into the frame the TCP header can start for
333 * firmware assisted TSO to work.
335 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
337 if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
339 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
341 /* All Huntington devices have a PCIe Gen3, 8 lane connector */
342 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
371 EFSYS_PROBE1(fail1, efx_rc_t, rc);
377 #endif /* EFSYS_OPT_HUNTINGTON */