1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
13 #if EFSYS_OPT_HUNTINGTON
15 #include "ef10_tlv_layout.h"
17 static __checkReturn efx_rc_t
18 hunt_nic_get_required_pcie_bandwidth(
20 __out uint32_t *bandwidth_mbpsp)
23 uint32_t max_port_mode;
28 * On Huntington, the firmware may not give us the current port mode, so
29 * we need to go by the set of available port modes and assume the most
30 * capable mode is in use.
33 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, NULL)) != 0) {
34 /* No port mode info available */
39 if (port_modes & (1 << TLV_PORT_MODE_40G_40G)) {
41 * This needs the full PCIe bandwidth (and could use
42 * more) - roughly 64 Gbit/s for 8 lanes of Gen3.
44 if ((rc = efx_nic_calculate_pcie_link_bandwidth(8,
45 EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)
48 if (port_modes & (1 << TLV_PORT_MODE_40G)) {
49 max_port_mode = TLV_PORT_MODE_40G;
50 } else if (port_modes & (1 << TLV_PORT_MODE_10G_10G_10G_10G)) {
51 max_port_mode = TLV_PORT_MODE_10G_10G_10G_10G;
53 /* Assume two 10G ports */
54 max_port_mode = TLV_PORT_MODE_10G_10G;
57 if ((rc = ef10_nic_get_port_mode_bandwidth(max_port_mode,
63 *bandwidth_mbpsp = bandwidth;
70 EFSYS_PROBE1(fail1, efx_rc_t, rc);
75 __checkReturn efx_rc_t
79 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
80 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
81 uint8_t mac_addr[6] = { 0 };
82 uint32_t board_type = 0;
83 ef10_link_state_t els;
84 efx_port_t *epp = &(enp->en_port);
90 uint32_t sysclk, dpcpu_clk;
95 /* Huntington has a fixed 8Kbyte VI window size */
96 EFX_STATIC_ASSERT(ER_DZ_EVQ_RPTR_REG_STEP == 8192);
97 EFX_STATIC_ASSERT(ER_DZ_EVQ_TMR_REG_STEP == 8192);
98 EFX_STATIC_ASSERT(ER_DZ_RX_DESC_UPD_REG_STEP == 8192);
99 EFX_STATIC_ASSERT(ER_DZ_TX_DESC_UPD_REG_STEP == 8192);
100 EFX_STATIC_ASSERT(ER_DZ_TX_PIOBUF_STEP == 8192);
102 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
103 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
106 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
110 * NOTE: The MCDI protocol numbers ports from zero.
111 * The common code MCDI interface numbers ports from one.
113 emip->emi_port = port + 1;
115 if ((rc = ef10_external_port_mapping(enp, port,
116 &encp->enc_external_port)) != 0)
120 * Get PCIe function number from firmware (used for
121 * per-function privilege and dynamic config info).
122 * - PCIe PF: pf = PF number, vf = 0xffff.
123 * - PCIe VF: pf = parent PF, vf = VF number.
125 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
131 /* MAC address for this function */
132 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
133 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
134 if ((rc == 0) && (mac_addr[0] & 0x02)) {
136 * If the static config does not include a global MAC
137 * address pool then the board may return a locally
138 * administered MAC address (this should only happen on
139 * incorrectly programmed boards).
144 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
149 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
151 /* Board configuration */
152 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
154 /* Unprivileged functions may not be able to read board cfg */
161 encp->enc_board_type = board_type;
162 encp->enc_clk_mult = 1; /* not used for Huntington */
164 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
165 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
168 /* Obtain the default PHY advertised capabilities */
169 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
171 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
172 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
175 * Enable firmware workarounds for hardware errata.
176 * Expected responses are:
178 * Success: workaround enabled or disabled as requested.
179 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
180 * Firmware does not support the MC_CMD_WORKAROUND request.
181 * (assume that the workaround is not supported).
182 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
183 * Firmware does not support the requested workaround.
184 * - MC_CMD_ERR_EPERM (reported as EACCES):
185 * Unprivileged function cannot enable/disable workarounds.
187 * See efx_mcdi_request_errcode() for MCDI error translations.
191 * If the bug35388 workaround is enabled, then use an indirect access
192 * method to avoid unsafe EVQ writes.
194 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
196 if ((rc == 0) || (rc == EACCES))
197 encp->enc_bug35388_workaround = B_TRUE;
198 else if ((rc == ENOTSUP) || (rc == ENOENT))
199 encp->enc_bug35388_workaround = B_FALSE;
204 * If the bug41750 workaround is enabled, then do not test interrupts,
205 * as the test will fail (seen with Greenport controllers).
207 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
210 encp->enc_bug41750_workaround = B_TRUE;
211 } else if (rc == EACCES) {
212 /* Assume a controller with 40G ports needs the workaround. */
213 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
214 encp->enc_bug41750_workaround = B_TRUE;
216 encp->enc_bug41750_workaround = B_FALSE;
217 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
218 encp->enc_bug41750_workaround = B_FALSE;
222 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
223 /* Interrupt testing does not work for VFs. See bug50084. */
224 encp->enc_bug41750_workaround = B_TRUE;
228 * If the bug26807 workaround is enabled, then firmware has enabled
229 * support for chained multicast filters. Firmware will reset (FLR)
230 * functions which have filters in the hardware filter table when the
231 * workaround is enabled/disabled.
233 * We must recheck if the workaround is enabled after inserting the
234 * first hardware filter, in case it has been changed since this check.
236 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
239 encp->enc_bug26807_workaround = B_TRUE;
240 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
242 * Other functions had installed filters before the
243 * workaround was enabled, and they have been reset
246 EFSYS_PROBE(bug26807_workaround_flr_done);
247 /* FIXME: bump MC warm boot count ? */
249 } else if (rc == EACCES) {
251 * Unprivileged functions cannot enable the workaround in older
254 encp->enc_bug26807_workaround = B_FALSE;
255 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
256 encp->enc_bug26807_workaround = B_FALSE;
261 /* Get clock frequencies (in MHz). */
262 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
266 * The Huntington timer quantum is 1536 sysclk cycles, documented for
267 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
269 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
270 if (encp->enc_bug35388_workaround) {
271 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
272 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
274 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
275 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
278 encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
280 /* Check capabilities of running datapath firmware */
281 if ((rc = ef10_get_datapath_caps(enp)) != 0)
284 /* Alignment for receive packet DMA buffers */
285 encp->enc_rx_buf_align_start = 1;
286 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
288 /* Alignment for WPTR updates */
289 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
292 * Maximum number of exclusive RSS contexts which can be allocated. The
293 * hardware supports 64, but 6 are reserved for shared contexts. They
294 * are a global resource so not all may be available.
296 encp->enc_rx_scale_max_exclusive_contexts = 58;
298 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
299 /* No boundary crossing limits */
300 encp->enc_tx_dma_desc_boundary = 0;
303 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
304 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
305 * resources (allocated to this PCIe function), which is zero until
306 * after we have allocated VIs.
308 encp->enc_evq_limit = 1024;
309 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
310 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
313 * The workaround for bug35388 uses the top bit of transmit queue
314 * descriptor writes, preventing the use of 4096 descriptor TXQs.
316 encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
318 encp->enc_buftbl_limit = 0xFFFFFFFF;
320 EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
321 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
322 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
323 encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
326 * Get the current privilege mask. Note that this may be modified
327 * dynamically, so this value is informational only. DO NOT use
328 * the privilege mask to check for sufficient privileges, as that
329 * can result in time-of-check/time-of-use bugs.
331 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
333 encp->enc_privilege_mask = mask;
335 /* Get interrupt vector limits */
336 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
337 if (EFX_PCI_FUNCTION_IS_PF(encp))
340 /* Ignore error (cannot query vector limits from a VF). */
344 encp->enc_intr_vec_base = base;
345 encp->enc_intr_limit = nvec;
348 * Maximum number of bytes into the frame the TCP header can start for
349 * firmware assisted TSO to work.
351 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
353 if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
355 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
357 /* All Huntington devices have a PCIe Gen3, 8 lane connector */
358 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
391 EFSYS_PROBE1(fail1, efx_rc_t, rc);
397 #endif /* EFSYS_OPT_HUNTINGTON */