2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
34 #if EFSYS_OPT_HUNTINGTON
36 #include "ef10_tlv_layout.h"
38 static __checkReturn efx_rc_t
39 hunt_nic_get_required_pcie_bandwidth(
41 __out uint32_t *bandwidth_mbpsp)
44 uint32_t max_port_mode;
49 * On Huntington, the firmware may not give us the current port mode, so
50 * we need to go by the set of available port modes and assume the most
51 * capable mode is in use.
54 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, NULL)) != 0) {
55 /* No port mode info available */
60 if (port_modes & (1 << TLV_PORT_MODE_40G_40G)) {
62 * This needs the full PCIe bandwidth (and could use
63 * more) - roughly 64 Gbit/s for 8 lanes of Gen3.
65 if ((rc = efx_nic_calculate_pcie_link_bandwidth(8,
66 EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)
69 if (port_modes & (1 << TLV_PORT_MODE_40G)) {
70 max_port_mode = TLV_PORT_MODE_40G;
71 } else if (port_modes & (1 << TLV_PORT_MODE_10G_10G_10G_10G)) {
72 max_port_mode = TLV_PORT_MODE_10G_10G_10G_10G;
74 /* Assume two 10G ports */
75 max_port_mode = TLV_PORT_MODE_10G_10G;
78 if ((rc = ef10_nic_get_port_mode_bandwidth(max_port_mode,
84 *bandwidth_mbpsp = bandwidth;
91 EFSYS_PROBE1(fail1, efx_rc_t, rc);
96 __checkReturn efx_rc_t
100 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
101 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
102 uint8_t mac_addr[6] = { 0 };
103 uint32_t board_type = 0;
104 ef10_link_state_t els;
105 efx_port_t *epp = &(enp->en_port);
111 uint32_t sysclk, dpcpu_clk;
116 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
120 * NOTE: The MCDI protocol numbers ports from zero.
121 * The common code MCDI interface numbers ports from one.
123 emip->emi_port = port + 1;
125 if ((rc = ef10_external_port_mapping(enp, port,
126 &encp->enc_external_port)) != 0)
130 * Get PCIe function number from firmware (used for
131 * per-function privilege and dynamic config info).
132 * - PCIe PF: pf = PF number, vf = 0xffff.
133 * - PCIe VF: pf = parent PF, vf = VF number.
135 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
141 /* MAC address for this function */
142 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
143 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
144 if ((rc == 0) && (mac_addr[0] & 0x02)) {
146 * If the static config does not include a global MAC
147 * address pool then the board may return a locally
148 * administered MAC address (this should only happen on
149 * incorrectly programmed boards).
154 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
159 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
161 /* Board configuration */
162 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
164 /* Unprivileged functions may not be able to read board cfg */
171 encp->enc_board_type = board_type;
172 encp->enc_clk_mult = 1; /* not used for Huntington */
174 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
175 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
178 /* Obtain the default PHY advertised capabilities */
179 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
181 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
182 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
185 * Enable firmware workarounds for hardware errata.
186 * Expected responses are:
188 * Success: workaround enabled or disabled as requested.
189 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
190 * Firmware does not support the MC_CMD_WORKAROUND request.
191 * (assume that the workaround is not supported).
192 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
193 * Firmware does not support the requested workaround.
194 * - MC_CMD_ERR_EPERM (reported as EACCES):
195 * Unprivileged function cannot enable/disable workarounds.
197 * See efx_mcdi_request_errcode() for MCDI error translations.
201 * If the bug35388 workaround is enabled, then use an indirect access
202 * method to avoid unsafe EVQ writes.
204 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
206 if ((rc == 0) || (rc == EACCES))
207 encp->enc_bug35388_workaround = B_TRUE;
208 else if ((rc == ENOTSUP) || (rc == ENOENT))
209 encp->enc_bug35388_workaround = B_FALSE;
214 * If the bug41750 workaround is enabled, then do not test interrupts,
215 * as the test will fail (seen with Greenport controllers).
217 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
220 encp->enc_bug41750_workaround = B_TRUE;
221 } else if (rc == EACCES) {
222 /* Assume a controller with 40G ports needs the workaround. */
223 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
224 encp->enc_bug41750_workaround = B_TRUE;
226 encp->enc_bug41750_workaround = B_FALSE;
227 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
228 encp->enc_bug41750_workaround = B_FALSE;
232 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
233 /* Interrupt testing does not work for VFs. See bug50084. */
234 encp->enc_bug41750_workaround = B_TRUE;
238 * If the bug26807 workaround is enabled, then firmware has enabled
239 * support for chained multicast filters. Firmware will reset (FLR)
240 * functions which have filters in the hardware filter table when the
241 * workaround is enabled/disabled.
243 * We must recheck if the workaround is enabled after inserting the
244 * first hardware filter, in case it has been changed since this check.
246 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
249 encp->enc_bug26807_workaround = B_TRUE;
250 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
252 * Other functions had installed filters before the
253 * workaround was enabled, and they have been reset
256 EFSYS_PROBE(bug26807_workaround_flr_done);
257 /* FIXME: bump MC warm boot count ? */
259 } else if (rc == EACCES) {
261 * Unprivileged functions cannot enable the workaround in older
264 encp->enc_bug26807_workaround = B_FALSE;
265 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
266 encp->enc_bug26807_workaround = B_FALSE;
271 /* Get clock frequencies (in MHz). */
272 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
276 * The Huntington timer quantum is 1536 sysclk cycles, documented for
277 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
279 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
280 if (encp->enc_bug35388_workaround) {
281 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
282 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
284 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
285 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
288 encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
290 /* Check capabilities of running datapath firmware */
291 if ((rc = ef10_get_datapath_caps(enp)) != 0)
294 /* Alignment for receive packet DMA buffers */
295 encp->enc_rx_buf_align_start = 1;
296 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
298 /* Alignment for WPTR updates */
299 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
302 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
303 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
304 * resources (allocated to this PCIe function), which is zero until
305 * after we have allocated VIs.
307 encp->enc_evq_limit = 1024;
308 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
309 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
312 * The workaround for bug35388 uses the top bit of transmit queue
313 * descriptor writes, preventing the use of 4096 descriptor TXQs.
315 encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
317 encp->enc_buftbl_limit = 0xFFFFFFFF;
319 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
320 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
321 encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
324 * Get the current privilege mask. Note that this may be modified
325 * dynamically, so this value is informational only. DO NOT use
326 * the privilege mask to check for sufficient privileges, as that
327 * can result in time-of-check/time-of-use bugs.
329 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
331 encp->enc_privilege_mask = mask;
333 /* Get interrupt vector limits */
334 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
335 if (EFX_PCI_FUNCTION_IS_PF(encp))
338 /* Ignore error (cannot query vector limits from a VF). */
342 encp->enc_intr_vec_base = base;
343 encp->enc_intr_limit = nvec;
346 * Maximum number of bytes into the frame the TCP header can start for
347 * firmware assisted TSO to work.
349 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
351 if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
353 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
355 /* All Huntington devices have a PCIe Gen3, 8 lane connector */
356 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
389 EFSYS_PROBE1(fail1, efx_rc_t, rc);
395 #endif /* EFSYS_OPT_HUNTINGTON */