1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
11 #if EFSYS_OPT_MEDFORD2
13 static __checkReturn efx_rc_t
14 medford2_nic_get_required_pcie_bandwidth(
16 __out uint32_t *bandwidth_mbpsp)
19 uint32_t current_mode;
23 /* FIXME: support new Medford2 dynamic port modes */
25 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
26 ¤t_mode)) != 0) {
27 /* No port mode info available. */
32 if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
37 *bandwidth_mbpsp = bandwidth;
42 EFSYS_PROBE1(fail1, efx_rc_t, rc);
47 __checkReturn efx_rc_t
51 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
52 uint8_t mac_addr[6] = { 0 };
53 uint32_t board_type = 0;
54 ef10_link_state_t els;
55 efx_port_t *epp = &(enp->en_port);
57 uint32_t sysclk, dpcpu_clk;
61 uint32_t vi_window_shift;
65 * FIXME: Likely to be incomplete and incorrect.
66 * Parts of this should be shared with Huntington.
69 /* Medford2 has a variable VI window size (8K, 16K or 64K) */
70 if ((rc = ef10_get_vi_window_shift(enp, &vi_window_shift)) != 0)
73 EFSYS_ASSERT3U(vi_window_shift, <=, EFX_VI_WINDOW_SHIFT_64K);
74 encp->enc_vi_window_shift = vi_window_shift;
77 /* MAC address for this function */
78 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
79 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
80 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
82 * Disable static config checking for Medford NICs, ONLY
83 * for manufacturing test and setup at the factory, to
84 * allow the static config to be installed.
86 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
87 if ((rc == 0) && (mac_addr[0] & 0x02)) {
89 * If the static config does not include a global MAC
90 * address pool then the board may return a locally
91 * administered MAC address (this should only happen on
92 * incorrectly programmed boards).
96 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
98 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
103 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
105 /* Board configuration */
106 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
108 /* Unprivileged functions may not be able to read board cfg */
115 encp->enc_board_type = board_type;
116 encp->enc_clk_mult = 1; /* not used for Medford2 */
118 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
119 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
122 /* Obtain the default PHY advertised capabilities */
123 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
125 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
126 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
129 * Enable firmware workarounds for hardware errata.
130 * Expected responses are:
132 * Success: workaround enabled or disabled as requested.
133 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
134 * Firmware does not support the MC_CMD_WORKAROUND request.
135 * (assume that the workaround is not supported).
136 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
137 * Firmware does not support the requested workaround.
138 * - MC_CMD_ERR_EPERM (reported as EACCES):
139 * Unprivileged function cannot enable/disable workarounds.
141 * See efx_mcdi_request_errcode() for MCDI error translations.
145 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
147 * Interrupt testing does not work for VFs on Medford2.
148 * See bug50084 and bug71432 comment 21.
150 encp->enc_bug41750_workaround = B_TRUE;
153 /* Chained multicast is always enabled on Medford2 */
154 encp->enc_bug26807_workaround = B_TRUE;
157 * If the bug61265 workaround is enabled, then interrupt holdoff timers
158 * cannot be controlled by timer table writes, so MCDI must be used
159 * (timer table writes can still be used for wakeup timers).
161 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
163 if ((rc == 0) || (rc == EACCES))
164 encp->enc_bug61265_workaround = B_TRUE;
165 else if ((rc == ENOTSUP) || (rc == ENOENT))
166 encp->enc_bug61265_workaround = B_FALSE;
170 /* Get clock frequencies (in MHz). */
171 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
175 * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
176 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
178 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
179 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
180 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
182 /* Check capabilities of running datapath firmware */
183 if ((rc = ef10_get_datapath_caps(enp)) != 0)
186 /* Alignment for receive packet DMA buffers */
187 encp->enc_rx_buf_align_start = 1;
189 /* Get the RX DMA end padding alignment configuration */
190 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
194 /* Assume largest tail padding size supported by hardware */
197 encp->enc_rx_buf_align_end = end_padding;
199 /* Alignment for WPTR updates */
200 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
203 * Maximum number of exclusive RSS contexts which can be allocated. The
204 * hardware supports 64, but 6 are reserved for shared contexts. They
205 * are a global resource so not all may be available.
207 encp->enc_rx_scale_max_exclusive_contexts = 58;
209 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
210 /* No boundary crossing limits */
211 encp->enc_tx_dma_desc_boundary = 0;
214 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
215 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
216 * resources (allocated to this PCIe function), which is zero until
217 * after we have allocated VIs.
219 encp->enc_evq_limit = 1024;
220 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
221 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
224 * The maximum supported transmit queue size is 2048. TXQs with 4096
225 * descriptors are not supported as the top bit is used for vfifo
228 encp->enc_txq_max_ndescs = 2048;
230 encp->enc_buftbl_limit = 0xFFFFFFFF;
232 EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
233 encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;
234 encp->enc_piobuf_size = MEDFORD2_PIOBUF_SIZE;
235 encp->enc_piobuf_min_alloc_size = MEDFORD2_MIN_PIO_ALLOC_SIZE;
238 * Get the current privilege mask. Note that this may be modified
239 * dynamically, so this value is informational only. DO NOT use
240 * the privilege mask to check for sufficient privileges, as that
241 * can result in time-of-check/time-of-use bugs.
243 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
245 encp->enc_privilege_mask = mask;
247 /* Get interrupt vector limits */
248 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
249 if (EFX_PCI_FUNCTION_IS_PF(encp))
252 /* Ignore error (cannot query vector limits from a VF). */
256 encp->enc_intr_vec_base = base;
257 encp->enc_intr_limit = nvec;
260 * Maximum number of bytes into the frame the TCP header can start for
261 * firmware assisted TSO to work.
263 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
266 * Medford2 stores a single global copy of VPD, not per-PF as on
269 encp->enc_vpd_is_global = B_TRUE;
271 rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
274 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
275 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
302 EFSYS_PROBE1(fail1, efx_rc_t, rc);
307 #endif /* EFSYS_OPT_MEDFORD2 */