1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
11 #if EFSYS_OPT_MEDFORD2
13 static __checkReturn efx_rc_t
14 medford2_nic_get_required_pcie_bandwidth(
16 __out uint32_t *bandwidth_mbpsp)
21 /* FIXME: support new Medford2 dynamic port modes */
23 if ((rc = ef10_nic_get_port_mode_bandwidth(enp,
27 *bandwidth_mbpsp = bandwidth;
32 EFSYS_PROBE1(fail1, efx_rc_t, rc);
37 __checkReturn efx_rc_t
41 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
42 uint32_t sysclk, dpcpu_clk;
48 * Enable firmware workarounds for hardware errata.
49 * Expected responses are:
51 * Success: workaround enabled or disabled as requested.
52 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
53 * Firmware does not support the MC_CMD_WORKAROUND request.
54 * (assume that the workaround is not supported).
55 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
56 * Firmware does not support the requested workaround.
57 * - MC_CMD_ERR_EPERM (reported as EACCES):
58 * Unprivileged function cannot enable/disable workarounds.
60 * See efx_mcdi_request_errcode() for MCDI error translations.
64 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
66 * Interrupt testing does not work for VFs on Medford2.
67 * See bug50084 and bug71432 comment 21.
69 encp->enc_bug41750_workaround = B_TRUE;
72 /* Chained multicast is always enabled on Medford2 */
73 encp->enc_bug26807_workaround = B_TRUE;
76 * If the bug61265 workaround is enabled, then interrupt holdoff timers
77 * cannot be controlled by timer table writes, so MCDI must be used
78 * (timer table writes can still be used for wakeup timers).
80 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
82 if ((rc == 0) || (rc == EACCES))
83 encp->enc_bug61265_workaround = B_TRUE;
84 else if ((rc == ENOTSUP) || (rc == ENOENT))
85 encp->enc_bug61265_workaround = B_FALSE;
89 /* Checksums for TSO sends should always be correct on Medford2. */
90 encp->enc_bug61297_workaround = B_FALSE;
92 /* Get clock frequencies (in MHz). */
93 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
97 * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
98 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
100 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
101 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
102 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
104 /* Alignment for receive packet DMA buffers */
105 encp->enc_rx_buf_align_start = 1;
107 /* Get the RX DMA end padding alignment configuration */
108 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
112 /* Assume largest tail padding size supported by hardware */
115 encp->enc_rx_buf_align_end = end_padding;
117 encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS;
118 encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS;
120 encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
121 encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
124 * The maximum supported transmit queue size is 2048. TXQs with 4096
125 * descriptors are not supported as the top bit is used for vfifo
128 encp->enc_txq_max_ndescs = MEDFORD2_TXQ_MAXNDESCS;
129 encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;
131 EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
132 encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;
133 encp->enc_piobuf_size = MEDFORD2_PIOBUF_SIZE;
134 encp->enc_piobuf_min_alloc_size = MEDFORD2_MIN_PIO_ALLOC_SIZE;
137 * Medford2 stores a single global copy of VPD, not per-PF as on
140 encp->enc_vpd_is_global = B_TRUE;
142 rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
145 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
146 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
157 EFSYS_PROBE1(fail1, efx_rc_t, rc);
162 #endif /* EFSYS_OPT_MEDFORD2 */