1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
11 #if EFSYS_OPT_MEDFORD2
13 static __checkReturn efx_rc_t
14 medford2_nic_get_required_pcie_bandwidth(
16 __out uint32_t *bandwidth_mbpsp)
19 uint32_t current_mode;
23 /* FIXME: support new Medford2 dynamic port modes */
25 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
26 ¤t_mode)) != 0) {
27 /* No port mode info available. */
32 if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
37 *bandwidth_mbpsp = bandwidth;
42 EFSYS_PROBE1(fail1, efx_rc_t, rc);
47 __checkReturn efx_rc_t
51 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
52 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
53 uint8_t mac_addr[6] = { 0 };
54 uint32_t board_type = 0;
55 ef10_link_state_t els;
56 efx_port_t *epp = &(enp->en_port);
61 uint32_t sysclk, dpcpu_clk;
68 * FIXME: Likely to be incomplete and incorrect.
69 * Parts of this should be shared with Huntington.
72 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
76 * NOTE: The MCDI protocol numbers ports from zero.
77 * The common code MCDI interface numbers ports from one.
79 emip->emi_port = port + 1;
81 if ((rc = ef10_external_port_mapping(enp, port,
82 &encp->enc_external_port)) != 0)
86 * Get PCIe function number from firmware (used for
87 * per-function privilege and dynamic config info).
88 * - PCIe PF: pf = PF number, vf = 0xffff.
89 * - PCIe VF: pf = parent PF, vf = VF number.
91 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
97 /* MAC address for this function */
98 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
99 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
100 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
102 * Disable static config checking for Medford NICs, ONLY
103 * for manufacturing test and setup at the factory, to
104 * allow the static config to be installed.
106 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
107 if ((rc == 0) && (mac_addr[0] & 0x02)) {
109 * If the static config does not include a global MAC
110 * address pool then the board may return a locally
111 * administered MAC address (this should only happen on
112 * incorrectly programmed boards).
116 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
118 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
123 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
125 /* Board configuration */
126 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
128 /* Unprivileged functions may not be able to read board cfg */
135 encp->enc_board_type = board_type;
136 encp->enc_clk_mult = 1; /* not used for Medford2 */
138 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
139 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
142 /* Obtain the default PHY advertised capabilities */
143 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
145 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
146 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
149 * Enable firmware workarounds for hardware errata.
150 * Expected responses are:
152 * Success: workaround enabled or disabled as requested.
153 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
154 * Firmware does not support the MC_CMD_WORKAROUND request.
155 * (assume that the workaround is not supported).
156 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
157 * Firmware does not support the requested workaround.
158 * - MC_CMD_ERR_EPERM (reported as EACCES):
159 * Unprivileged function cannot enable/disable workarounds.
161 * See efx_mcdi_request_errcode() for MCDI error translations.
165 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
167 * Interrupt testing does not work for VFs. See bug50084.
168 * FIXME: Does this still apply to Medford2?
170 encp->enc_bug41750_workaround = B_TRUE;
173 /* Chained multicast is always enabled on Medford2 */
174 encp->enc_bug26807_workaround = B_TRUE;
177 * If the bug61265 workaround is enabled, then interrupt holdoff timers
178 * cannot be controlled by timer table writes, so MCDI must be used
179 * (timer table writes can still be used for wakeup timers).
181 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
183 if ((rc == 0) || (rc == EACCES))
184 encp->enc_bug61265_workaround = B_TRUE;
185 else if ((rc == ENOTSUP) || (rc == ENOENT))
186 encp->enc_bug61265_workaround = B_FALSE;
190 /* Get clock frequencies (in MHz). */
191 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
195 * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
196 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
198 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
199 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
200 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
202 /* Check capabilities of running datapath firmware */
203 if ((rc = ef10_get_datapath_caps(enp)) != 0)
206 /* Alignment for receive packet DMA buffers */
207 encp->enc_rx_buf_align_start = 1;
209 /* Get the RX DMA end padding alignment configuration */
210 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
214 /* Assume largest tail padding size supported by hardware */
217 encp->enc_rx_buf_align_end = end_padding;
219 /* Alignment for WPTR updates */
220 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
223 * Maximum number of exclusive RSS contexts which can be allocated. The
224 * hardware supports 64, but 6 are reserved for shared contexts. They
225 * are a global resource so not all may be available.
227 encp->enc_rx_scale_max_exclusive_contexts = 58;
229 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
230 /* No boundary crossing limits */
231 encp->enc_tx_dma_desc_boundary = 0;
234 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
235 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
236 * resources (allocated to this PCIe function), which is zero until
237 * after we have allocated VIs.
239 encp->enc_evq_limit = 1024;
240 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
241 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
244 * The maximum supported transmit queue size is 2048. TXQs with 4096
245 * descriptors are not supported as the top bit is used for vfifo
248 encp->enc_txq_max_ndescs = 2048;
250 encp->enc_buftbl_limit = 0xFFFFFFFF;
252 EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
253 encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;
254 encp->enc_piobuf_size = MEDFORD2_PIOBUF_SIZE;
255 encp->enc_piobuf_min_alloc_size = MEDFORD2_MIN_PIO_ALLOC_SIZE;
258 * Get the current privilege mask. Note that this may be modified
259 * dynamically, so this value is informational only. DO NOT use
260 * the privilege mask to check for sufficient privileges, as that
261 * can result in time-of-check/time-of-use bugs.
263 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
265 encp->enc_privilege_mask = mask;
267 /* Get interrupt vector limits */
268 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
269 if (EFX_PCI_FUNCTION_IS_PF(encp))
272 /* Ignore error (cannot query vector limits from a VF). */
276 encp->enc_intr_vec_base = base;
277 encp->enc_intr_limit = nvec;
280 * Maximum number of bytes into the frame the TCP header can start for
281 * firmware assisted TSO to work.
283 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
286 * Medford2 stores a single global copy of VPD, not per-PF as on
289 encp->enc_vpd_is_global = B_TRUE;
291 rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
294 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
295 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
326 EFSYS_PROBE1(fail1, efx_rc_t, rc);
331 #endif /* EFSYS_OPT_MEDFORD2 */