1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
11 #if EFSYS_OPT_MEDFORD2
13 static __checkReturn efx_rc_t
14 efx_mcdi_get_rxdp_config(
16 __out uint32_t *end_paddingp)
19 uint8_t payload[MAX(MC_CMD_GET_RXDP_CONFIG_IN_LEN,
20 MC_CMD_GET_RXDP_CONFIG_OUT_LEN)];
24 memset(payload, 0, sizeof (payload));
25 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
26 req.emr_in_buf = payload;
27 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
28 req.emr_out_buf = payload;
29 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
31 efx_mcdi_execute(enp, &req);
32 if (req.emr_rc != 0) {
37 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
38 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
39 /* RX DMA end padding is disabled */
42 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
43 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
44 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
47 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
50 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
59 *end_paddingp = end_padding;
66 EFSYS_PROBE1(fail1, efx_rc_t, rc);
71 static __checkReturn efx_rc_t
72 medford2_nic_get_required_pcie_bandwidth(
74 __out uint32_t *bandwidth_mbpsp)
77 uint32_t current_mode;
81 /* FIXME: support new Medford2 dynamic port modes */
83 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
84 ¤t_mode)) != 0) {
85 /* No port mode info available. */
90 if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
95 *bandwidth_mbpsp = bandwidth;
100 EFSYS_PROBE1(fail1, efx_rc_t, rc);
105 __checkReturn efx_rc_t
109 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
110 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
111 uint8_t mac_addr[6] = { 0 };
112 uint32_t board_type = 0;
113 ef10_link_state_t els;
114 efx_port_t *epp = &(enp->en_port);
119 uint32_t sysclk, dpcpu_clk;
121 uint32_t end_padding;
126 * FIXME: Likely to be incomplete and incorrect.
127 * Parts of this should be shared with Huntington.
130 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
134 * NOTE: The MCDI protocol numbers ports from zero.
135 * The common code MCDI interface numbers ports from one.
137 emip->emi_port = port + 1;
139 if ((rc = ef10_external_port_mapping(enp, port,
140 &encp->enc_external_port)) != 0)
144 * Get PCIe function number from firmware (used for
145 * per-function privilege and dynamic config info).
146 * - PCIe PF: pf = PF number, vf = 0xffff.
147 * - PCIe VF: pf = parent PF, vf = VF number.
149 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
155 /* MAC address for this function */
156 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
157 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
158 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
160 * Disable static config checking for Medford NICs, ONLY
161 * for manufacturing test and setup at the factory, to
162 * allow the static config to be installed.
164 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
165 if ((rc == 0) && (mac_addr[0] & 0x02)) {
167 * If the static config does not include a global MAC
168 * address pool then the board may return a locally
169 * administered MAC address (this should only happen on
170 * incorrectly programmed boards).
174 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
176 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
181 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
183 /* Board configuration */
184 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
186 /* Unprivileged functions may not be able to read board cfg */
193 encp->enc_board_type = board_type;
194 encp->enc_clk_mult = 1; /* not used for Medford2 */
196 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
197 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
200 /* Obtain the default PHY advertised capabilities */
201 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
203 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
204 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
207 * Enable firmware workarounds for hardware errata.
208 * Expected responses are:
210 * Success: workaround enabled or disabled as requested.
211 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
212 * Firmware does not support the MC_CMD_WORKAROUND request.
213 * (assume that the workaround is not supported).
214 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
215 * Firmware does not support the requested workaround.
216 * - MC_CMD_ERR_EPERM (reported as EACCES):
217 * Unprivileged function cannot enable/disable workarounds.
219 * See efx_mcdi_request_errcode() for MCDI error translations.
223 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
225 * Interrupt testing does not work for VFs. See bug50084.
226 * FIXME: Does this still apply to Medford2?
228 encp->enc_bug41750_workaround = B_TRUE;
231 /* Chained multicast is always enabled on Medford2 */
232 encp->enc_bug26807_workaround = B_TRUE;
235 * If the bug61265 workaround is enabled, then interrupt holdoff timers
236 * cannot be controlled by timer table writes, so MCDI must be used
237 * (timer table writes can still be used for wakeup timers).
239 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
241 if ((rc == 0) || (rc == EACCES))
242 encp->enc_bug61265_workaround = B_TRUE;
243 else if ((rc == ENOTSUP) || (rc == ENOENT))
244 encp->enc_bug61265_workaround = B_FALSE;
248 /* Get clock frequencies (in MHz). */
249 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
253 * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
254 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
256 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
257 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
258 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
260 /* Check capabilities of running datapath firmware */
261 if ((rc = ef10_get_datapath_caps(enp)) != 0)
264 /* Alignment for receive packet DMA buffers */
265 encp->enc_rx_buf_align_start = 1;
267 /* Get the RX DMA end padding alignment configuration */
268 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
272 /* Assume largest tail padding size supported by hardware */
275 encp->enc_rx_buf_align_end = end_padding;
277 /* Alignment for WPTR updates */
278 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
281 * Maximum number of exclusive RSS contexts which can be allocated. The
282 * hardware supports 64, but 6 are reserved for shared contexts. They
283 * are a global resource so not all may be available.
285 encp->enc_rx_scale_max_exclusive_contexts = 58;
287 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
288 /* No boundary crossing limits */
289 encp->enc_tx_dma_desc_boundary = 0;
292 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
293 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
294 * resources (allocated to this PCIe function), which is zero until
295 * after we have allocated VIs.
297 encp->enc_evq_limit = 1024;
298 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
299 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
302 * The maximum supported transmit queue size is 2048. TXQs with 4096
303 * descriptors are not supported as the top bit is used for vfifo
306 encp->enc_txq_max_ndescs = 2048;
308 encp->enc_buftbl_limit = 0xFFFFFFFF;
310 encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;
311 encp->enc_piobuf_size = MEDFORD2_PIOBUF_SIZE;
312 encp->enc_piobuf_min_alloc_size = MEDFORD2_MIN_PIO_ALLOC_SIZE;
315 * Get the current privilege mask. Note that this may be modified
316 * dynamically, so this value is informational only. DO NOT use
317 * the privilege mask to check for sufficient privileges, as that
318 * can result in time-of-check/time-of-use bugs.
320 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
322 encp->enc_privilege_mask = mask;
324 /* Get interrupt vector limits */
325 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
326 if (EFX_PCI_FUNCTION_IS_PF(encp))
329 /* Ignore error (cannot query vector limits from a VF). */
333 encp->enc_intr_vec_base = base;
334 encp->enc_intr_limit = nvec;
337 * Maximum number of bytes into the frame the TCP header can start for
338 * firmware assisted TSO to work.
340 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
343 * Medford2 stores a single global copy of VPD, not per-PF as on
346 encp->enc_vpd_is_global = B_TRUE;
348 rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
351 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
352 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
383 EFSYS_PROBE1(fail1, efx_rc_t, rc);
388 #endif /* EFSYS_OPT_MEDFORD2 */