1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
11 #if EFSYS_OPT_MEDFORD2
13 static __checkReturn efx_rc_t
14 medford2_nic_get_required_pcie_bandwidth(
16 __out uint32_t *bandwidth_mbpsp)
19 uint32_t current_mode;
23 /* FIXME: support new Medford2 dynamic port modes */
25 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
26 ¤t_mode)) != 0) {
27 /* No port mode info available. */
32 if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
37 *bandwidth_mbpsp = bandwidth;
42 EFSYS_PROBE1(fail1, efx_rc_t, rc);
47 __checkReturn efx_rc_t
51 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
52 uint32_t sysclk, dpcpu_clk;
55 uint32_t vi_window_shift;
59 * FIXME: Likely to be incomplete and incorrect.
60 * Parts of this should be shared with Huntington.
63 /* Medford2 has a variable VI window size (8K, 16K or 64K) */
64 if ((rc = ef10_get_vi_window_shift(enp, &vi_window_shift)) != 0)
67 EFSYS_ASSERT3U(vi_window_shift, <=, EFX_VI_WINDOW_SHIFT_64K);
68 encp->enc_vi_window_shift = vi_window_shift;
72 * Enable firmware workarounds for hardware errata.
73 * Expected responses are:
75 * Success: workaround enabled or disabled as requested.
76 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
77 * Firmware does not support the MC_CMD_WORKAROUND request.
78 * (assume that the workaround is not supported).
79 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
80 * Firmware does not support the requested workaround.
81 * - MC_CMD_ERR_EPERM (reported as EACCES):
82 * Unprivileged function cannot enable/disable workarounds.
84 * See efx_mcdi_request_errcode() for MCDI error translations.
88 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
90 * Interrupt testing does not work for VFs on Medford2.
91 * See bug50084 and bug71432 comment 21.
93 encp->enc_bug41750_workaround = B_TRUE;
96 /* Chained multicast is always enabled on Medford2 */
97 encp->enc_bug26807_workaround = B_TRUE;
100 * If the bug61265 workaround is enabled, then interrupt holdoff timers
101 * cannot be controlled by timer table writes, so MCDI must be used
102 * (timer table writes can still be used for wakeup timers).
104 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
106 if ((rc == 0) || (rc == EACCES))
107 encp->enc_bug61265_workaround = B_TRUE;
108 else if ((rc == ENOTSUP) || (rc == ENOENT))
109 encp->enc_bug61265_workaround = B_FALSE;
113 /* Get clock frequencies (in MHz). */
114 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
118 * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
119 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
121 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
122 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
123 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
125 /* Alignment for receive packet DMA buffers */
126 encp->enc_rx_buf_align_start = 1;
128 /* Get the RX DMA end padding alignment configuration */
129 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
133 /* Assume largest tail padding size supported by hardware */
136 encp->enc_rx_buf_align_end = end_padding;
139 * The maximum supported transmit queue size is 2048. TXQs with 4096
140 * descriptors are not supported as the top bit is used for vfifo
143 encp->enc_txq_max_ndescs = 2048;
145 EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
146 encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;
147 encp->enc_piobuf_size = MEDFORD2_PIOBUF_SIZE;
148 encp->enc_piobuf_min_alloc_size = MEDFORD2_MIN_PIO_ALLOC_SIZE;
151 * Medford2 stores a single global copy of VPD, not per-PF as on
154 encp->enc_vpd_is_global = B_TRUE;
156 rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
159 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
160 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
173 EFSYS_PROBE1(fail1, efx_rc_t, rc);
178 #endif /* EFSYS_OPT_MEDFORD2 */