1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
11 #if EFSYS_OPT_MEDFORD2
13 static __checkReturn efx_rc_t
14 medford2_nic_get_required_pcie_bandwidth(
16 __out uint32_t *bandwidth_mbpsp)
19 uint32_t current_mode;
23 /* FIXME: support new Medford2 dynamic port modes */
25 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
26 ¤t_mode)) != 0) {
27 /* No port mode info available. */
32 if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
37 *bandwidth_mbpsp = bandwidth;
42 EFSYS_PROBE1(fail1, efx_rc_t, rc);
47 __checkReturn efx_rc_t
51 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
53 uint32_t sysclk, dpcpu_clk;
57 uint32_t vi_window_shift;
61 * FIXME: Likely to be incomplete and incorrect.
62 * Parts of this should be shared with Huntington.
65 /* Medford2 has a variable VI window size (8K, 16K or 64K) */
66 if ((rc = ef10_get_vi_window_shift(enp, &vi_window_shift)) != 0)
69 EFSYS_ASSERT3U(vi_window_shift, <=, EFX_VI_WINDOW_SHIFT_64K);
70 encp->enc_vi_window_shift = vi_window_shift;
74 * Enable firmware workarounds for hardware errata.
75 * Expected responses are:
77 * Success: workaround enabled or disabled as requested.
78 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
79 * Firmware does not support the MC_CMD_WORKAROUND request.
80 * (assume that the workaround is not supported).
81 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
82 * Firmware does not support the requested workaround.
83 * - MC_CMD_ERR_EPERM (reported as EACCES):
84 * Unprivileged function cannot enable/disable workarounds.
86 * See efx_mcdi_request_errcode() for MCDI error translations.
90 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
92 * Interrupt testing does not work for VFs on Medford2.
93 * See bug50084 and bug71432 comment 21.
95 encp->enc_bug41750_workaround = B_TRUE;
98 /* Chained multicast is always enabled on Medford2 */
99 encp->enc_bug26807_workaround = B_TRUE;
102 * If the bug61265 workaround is enabled, then interrupt holdoff timers
103 * cannot be controlled by timer table writes, so MCDI must be used
104 * (timer table writes can still be used for wakeup timers).
106 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
108 if ((rc == 0) || (rc == EACCES))
109 encp->enc_bug61265_workaround = B_TRUE;
110 else if ((rc == ENOTSUP) || (rc == ENOENT))
111 encp->enc_bug61265_workaround = B_FALSE;
115 /* Get clock frequencies (in MHz). */
116 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
120 * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
121 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
123 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
124 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
125 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
127 /* Alignment for receive packet DMA buffers */
128 encp->enc_rx_buf_align_start = 1;
130 /* Get the RX DMA end padding alignment configuration */
131 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
135 /* Assume largest tail padding size supported by hardware */
138 encp->enc_rx_buf_align_end = end_padding;
140 /* Alignment for WPTR updates */
141 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
144 * Maximum number of exclusive RSS contexts which can be allocated. The
145 * hardware supports 64, but 6 are reserved for shared contexts. They
146 * are a global resource so not all may be available.
148 encp->enc_rx_scale_max_exclusive_contexts = 58;
150 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
151 /* No boundary crossing limits */
152 encp->enc_tx_dma_desc_boundary = 0;
155 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
156 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
157 * resources (allocated to this PCIe function), which is zero until
158 * after we have allocated VIs.
160 encp->enc_evq_limit = 1024;
161 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
162 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
165 * The maximum supported transmit queue size is 2048. TXQs with 4096
166 * descriptors are not supported as the top bit is used for vfifo
169 encp->enc_txq_max_ndescs = 2048;
171 encp->enc_buftbl_limit = 0xFFFFFFFF;
173 EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
174 encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;
175 encp->enc_piobuf_size = MEDFORD2_PIOBUF_SIZE;
176 encp->enc_piobuf_min_alloc_size = MEDFORD2_MIN_PIO_ALLOC_SIZE;
179 * Get the current privilege mask. Note that this may be modified
180 * dynamically, so this value is informational only. DO NOT use
181 * the privilege mask to check for sufficient privileges, as that
182 * can result in time-of-check/time-of-use bugs.
184 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
186 encp->enc_privilege_mask = mask;
188 /* Get interrupt vector limits */
189 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
190 if (EFX_PCI_FUNCTION_IS_PF(encp))
193 /* Ignore error (cannot query vector limits from a VF). */
197 encp->enc_intr_vec_base = base;
198 encp->enc_intr_limit = nvec;
201 * Maximum number of bytes into the frame the TCP header can start for
202 * firmware assisted TSO to work.
204 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
207 * Medford2 stores a single global copy of VPD, not per-PF as on
210 encp->enc_vpd_is_global = B_TRUE;
212 rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
215 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
216 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
233 EFSYS_PROBE1(fail1, efx_rc_t, rc);
238 #endif /* EFSYS_OPT_MEDFORD2 */