1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
13 static __checkReturn efx_rc_t
14 medford_nic_get_required_pcie_bandwidth(
16 __out uint32_t *bandwidth_mbpsp)
19 uint32_t current_mode;
23 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
24 ¤t_mode)) != 0) {
25 /* No port mode info available. */
30 if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
35 *bandwidth_mbpsp = bandwidth;
40 EFSYS_PROBE1(fail1, efx_rc_t, rc);
45 __checkReturn efx_rc_t
49 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
50 uint8_t mac_addr[6] = { 0 };
51 uint32_t board_type = 0;
52 ef10_link_state_t els;
53 efx_port_t *epp = &(enp->en_port);
55 uint32_t sysclk, dpcpu_clk;
62 * FIXME: Likely to be incomplete and incorrect.
63 * Parts of this should be shared with Huntington.
66 /* Medford has a fixed 8Kbyte VI window size */
67 EFX_STATIC_ASSERT(ER_DZ_EVQ_RPTR_REG_STEP == 8192);
68 EFX_STATIC_ASSERT(ER_DZ_EVQ_TMR_REG_STEP == 8192);
69 EFX_STATIC_ASSERT(ER_DZ_RX_DESC_UPD_REG_STEP == 8192);
70 EFX_STATIC_ASSERT(ER_DZ_TX_DESC_UPD_REG_STEP == 8192);
71 EFX_STATIC_ASSERT(ER_DZ_TX_PIOBUF_STEP == 8192);
73 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
74 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
76 /* MAC address for this function */
77 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
78 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
79 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
81 * Disable static config checking for Medford NICs, ONLY
82 * for manufacturing test and setup at the factory, to
83 * allow the static config to be installed.
85 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
86 if ((rc == 0) && (mac_addr[0] & 0x02)) {
88 * If the static config does not include a global MAC
89 * address pool then the board may return a locally
90 * administered MAC address (this should only happen on
91 * incorrectly programmed boards).
95 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
97 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
102 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
104 /* Board configuration */
105 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
107 /* Unprivileged functions may not be able to read board cfg */
114 encp->enc_board_type = board_type;
115 encp->enc_clk_mult = 1; /* not used for Medford */
117 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
118 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
121 /* Obtain the default PHY advertised capabilities */
122 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
124 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
125 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
128 * Enable firmware workarounds for hardware errata.
129 * Expected responses are:
131 * Success: workaround enabled or disabled as requested.
132 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
133 * Firmware does not support the MC_CMD_WORKAROUND request.
134 * (assume that the workaround is not supported).
135 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
136 * Firmware does not support the requested workaround.
137 * - MC_CMD_ERR_EPERM (reported as EACCES):
138 * Unprivileged function cannot enable/disable workarounds.
140 * See efx_mcdi_request_errcode() for MCDI error translations.
144 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
146 * Interrupt testing does not work for VFs. See bug50084 and
147 * bug71432 comment 21.
149 encp->enc_bug41750_workaround = B_TRUE;
152 /* Chained multicast is always enabled on Medford */
153 encp->enc_bug26807_workaround = B_TRUE;
156 * If the bug61265 workaround is enabled, then interrupt holdoff timers
157 * cannot be controlled by timer table writes, so MCDI must be used
158 * (timer table writes can still be used for wakeup timers).
160 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
162 if ((rc == 0) || (rc == EACCES))
163 encp->enc_bug61265_workaround = B_TRUE;
164 else if ((rc == ENOTSUP) || (rc == ENOENT))
165 encp->enc_bug61265_workaround = B_FALSE;
169 /* Get clock frequencies (in MHz). */
170 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
174 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
175 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
177 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
178 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
179 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
181 /* Check capabilities of running datapath firmware */
182 if ((rc = ef10_get_datapath_caps(enp)) != 0)
185 /* Alignment for receive packet DMA buffers */
186 encp->enc_rx_buf_align_start = 1;
188 /* Get the RX DMA end padding alignment configuration */
189 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
193 /* Assume largest tail padding size supported by hardware */
196 encp->enc_rx_buf_align_end = end_padding;
198 /* Alignment for WPTR updates */
199 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
202 * Maximum number of exclusive RSS contexts which can be allocated. The
203 * hardware supports 64, but 6 are reserved for shared contexts. They
204 * are a global resource so not all may be available.
206 encp->enc_rx_scale_max_exclusive_contexts = 58;
208 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
209 /* No boundary crossing limits */
210 encp->enc_tx_dma_desc_boundary = 0;
213 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
214 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
215 * resources (allocated to this PCIe function), which is zero until
216 * after we have allocated VIs.
218 encp->enc_evq_limit = 1024;
219 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
220 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
223 * The maximum supported transmit queue size is 2048. TXQs with 4096
224 * descriptors are not supported as the top bit is used for vfifo
227 encp->enc_txq_max_ndescs = 2048;
229 encp->enc_buftbl_limit = 0xFFFFFFFF;
231 EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
232 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
233 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
234 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
237 * Get the current privilege mask. Note that this may be modified
238 * dynamically, so this value is informational only. DO NOT use
239 * the privilege mask to check for sufficient privileges, as that
240 * can result in time-of-check/time-of-use bugs.
242 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
244 encp->enc_privilege_mask = mask;
246 /* Get interrupt vector limits */
247 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
248 if (EFX_PCI_FUNCTION_IS_PF(encp))
251 /* Ignore error (cannot query vector limits from a VF). */
255 encp->enc_intr_vec_base = base;
256 encp->enc_intr_limit = nvec;
259 * Maximum number of bytes into the frame the TCP header can start for
260 * firmware assisted TSO to work.
262 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
265 * Medford stores a single global copy of VPD, not per-PF as on
268 encp->enc_vpd_is_global = B_TRUE;
270 rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
273 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
274 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
299 EFSYS_PROBE1(fail1, efx_rc_t, rc);
304 #endif /* EFSYS_OPT_MEDFORD */