1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
13 static __checkReturn efx_rc_t
14 efx_mcdi_get_rxdp_config(
16 __out uint32_t *end_paddingp)
19 uint8_t payload[MAX(MC_CMD_GET_RXDP_CONFIG_IN_LEN,
20 MC_CMD_GET_RXDP_CONFIG_OUT_LEN)];
24 memset(payload, 0, sizeof (payload));
25 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
26 req.emr_in_buf = payload;
27 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
28 req.emr_out_buf = payload;
29 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
31 efx_mcdi_execute(enp, &req);
32 if (req.emr_rc != 0) {
37 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
38 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
39 /* RX DMA end padding is disabled */
42 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
43 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
44 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
47 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
50 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
59 *end_paddingp = end_padding;
66 EFSYS_PROBE1(fail1, efx_rc_t, rc);
71 static __checkReturn efx_rc_t
72 medford_nic_get_required_pcie_bandwidth(
74 __out uint32_t *bandwidth_mbpsp)
77 uint32_t current_mode;
81 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
82 ¤t_mode)) != 0) {
83 /* No port mode info available. */
88 if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
93 *bandwidth_mbpsp = bandwidth;
98 EFSYS_PROBE1(fail1, efx_rc_t, rc);
103 __checkReturn efx_rc_t
107 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
108 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
109 uint8_t mac_addr[6] = { 0 };
110 uint32_t board_type = 0;
111 ef10_link_state_t els;
112 efx_port_t *epp = &(enp->en_port);
117 uint32_t sysclk, dpcpu_clk;
119 uint32_t end_padding;
124 * FIXME: Likely to be incomplete and incorrect.
125 * Parts of this should be shared with Huntington.
128 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
132 * NOTE: The MCDI protocol numbers ports from zero.
133 * The common code MCDI interface numbers ports from one.
135 emip->emi_port = port + 1;
137 if ((rc = ef10_external_port_mapping(enp, port,
138 &encp->enc_external_port)) != 0)
142 * Get PCIe function number from firmware (used for
143 * per-function privilege and dynamic config info).
144 * - PCIe PF: pf = PF number, vf = 0xffff.
145 * - PCIe VF: pf = parent PF, vf = VF number.
147 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
153 /* MAC address for this function */
154 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
155 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
156 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
158 * Disable static config checking for Medford NICs, ONLY
159 * for manufacturing test and setup at the factory, to
160 * allow the static config to be installed.
162 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
163 if ((rc == 0) && (mac_addr[0] & 0x02)) {
165 * If the static config does not include a global MAC
166 * address pool then the board may return a locally
167 * administered MAC address (this should only happen on
168 * incorrectly programmed boards).
172 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
174 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
179 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
181 /* Board configuration */
182 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
184 /* Unprivileged functions may not be able to read board cfg */
191 encp->enc_board_type = board_type;
192 encp->enc_clk_mult = 1; /* not used for Medford */
194 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
195 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
198 /* Obtain the default PHY advertised capabilities */
199 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
201 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
202 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
205 * Enable firmware workarounds for hardware errata.
206 * Expected responses are:
208 * Success: workaround enabled or disabled as requested.
209 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
210 * Firmware does not support the MC_CMD_WORKAROUND request.
211 * (assume that the workaround is not supported).
212 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
213 * Firmware does not support the requested workaround.
214 * - MC_CMD_ERR_EPERM (reported as EACCES):
215 * Unprivileged function cannot enable/disable workarounds.
217 * See efx_mcdi_request_errcode() for MCDI error translations.
221 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
223 * Interrupt testing does not work for VFs. See bug50084.
224 * FIXME: Does this still apply to Medford?
226 encp->enc_bug41750_workaround = B_TRUE;
229 /* Chained multicast is always enabled on Medford */
230 encp->enc_bug26807_workaround = B_TRUE;
233 * If the bug61265 workaround is enabled, then interrupt holdoff timers
234 * cannot be controlled by timer table writes, so MCDI must be used
235 * (timer table writes can still be used for wakeup timers).
237 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
239 if ((rc == 0) || (rc == EACCES))
240 encp->enc_bug61265_workaround = B_TRUE;
241 else if ((rc == ENOTSUP) || (rc == ENOENT))
242 encp->enc_bug61265_workaround = B_FALSE;
246 /* Get clock frequencies (in MHz). */
247 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
251 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
252 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
254 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
255 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
256 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
258 /* Check capabilities of running datapath firmware */
259 if ((rc = ef10_get_datapath_caps(enp)) != 0)
262 /* Alignment for receive packet DMA buffers */
263 encp->enc_rx_buf_align_start = 1;
265 /* Get the RX DMA end padding alignment configuration */
266 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
270 /* Assume largest tail padding size supported by hardware */
273 encp->enc_rx_buf_align_end = end_padding;
275 /* Alignment for WPTR updates */
276 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
279 * Maximum number of exclusive RSS contexts which can be allocated. The
280 * hardware supports 64, but 6 are reserved for shared contexts. They
281 * are a global resource so not all may be available.
283 encp->enc_rx_scale_max_exclusive_contexts = 58;
285 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
286 /* No boundary crossing limits */
287 encp->enc_tx_dma_desc_boundary = 0;
290 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
291 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
292 * resources (allocated to this PCIe function), which is zero until
293 * after we have allocated VIs.
295 encp->enc_evq_limit = 1024;
296 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
297 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
300 * The maximum supported transmit queue size is 2048. TXQs with 4096
301 * descriptors are not supported as the top bit is used for vfifo
304 encp->enc_txq_max_ndescs = 2048;
306 encp->enc_buftbl_limit = 0xFFFFFFFF;
308 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
309 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
310 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
313 * Get the current privilege mask. Note that this may be modified
314 * dynamically, so this value is informational only. DO NOT use
315 * the privilege mask to check for sufficient privileges, as that
316 * can result in time-of-check/time-of-use bugs.
318 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
320 encp->enc_privilege_mask = mask;
322 /* Get interrupt vector limits */
323 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
324 if (EFX_PCI_FUNCTION_IS_PF(encp))
327 /* Ignore error (cannot query vector limits from a VF). */
331 encp->enc_intr_vec_base = base;
332 encp->enc_intr_limit = nvec;
335 * Maximum number of bytes into the frame the TCP header can start for
336 * firmware assisted TSO to work.
338 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
341 * Medford stores a single global copy of VPD, not per-PF as on
344 encp->enc_vpd_is_global = B_TRUE;
346 rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
349 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
350 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
381 EFSYS_PROBE1(fail1, efx_rc_t, rc);
386 #endif /* EFSYS_OPT_MEDFORD */