1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
13 static __checkReturn efx_rc_t
14 medford_nic_get_required_pcie_bandwidth(
16 __out uint32_t *bandwidth_mbpsp)
19 uint32_t current_mode;
23 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
24 ¤t_mode)) != 0) {
25 /* No port mode info available. */
30 if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
35 *bandwidth_mbpsp = bandwidth;
40 EFSYS_PROBE1(fail1, efx_rc_t, rc);
45 __checkReturn efx_rc_t
49 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
50 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
51 uint8_t mac_addr[6] = { 0 };
52 uint32_t board_type = 0;
53 ef10_link_state_t els;
54 efx_port_t *epp = &(enp->en_port);
59 uint32_t sysclk, dpcpu_clk;
66 * FIXME: Likely to be incomplete and incorrect.
67 * Parts of this should be shared with Huntington.
70 /* Medford has a fixed 8Kbyte VI window size */
71 EFX_STATIC_ASSERT(ER_DZ_EVQ_RPTR_REG_STEP == 8192);
72 EFX_STATIC_ASSERT(ER_DZ_EVQ_TMR_REG_STEP == 8192);
73 EFX_STATIC_ASSERT(ER_DZ_RX_DESC_UPD_REG_STEP == 8192);
74 EFX_STATIC_ASSERT(ER_DZ_TX_DESC_UPD_REG_STEP == 8192);
75 EFX_STATIC_ASSERT(ER_DZ_TX_PIOBUF_STEP == 8192);
77 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
78 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
81 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
85 * NOTE: The MCDI protocol numbers ports from zero.
86 * The common code MCDI interface numbers ports from one.
88 emip->emi_port = port + 1;
90 if ((rc = ef10_external_port_mapping(enp, port,
91 &encp->enc_external_port)) != 0)
95 * Get PCIe function number from firmware (used for
96 * per-function privilege and dynamic config info).
97 * - PCIe PF: pf = PF number, vf = 0xffff.
98 * - PCIe VF: pf = parent PF, vf = VF number.
100 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
106 /* MAC address for this function */
107 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
108 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
109 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
111 * Disable static config checking for Medford NICs, ONLY
112 * for manufacturing test and setup at the factory, to
113 * allow the static config to be installed.
115 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
116 if ((rc == 0) && (mac_addr[0] & 0x02)) {
118 * If the static config does not include a global MAC
119 * address pool then the board may return a locally
120 * administered MAC address (this should only happen on
121 * incorrectly programmed boards).
125 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
127 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
132 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
134 /* Board configuration */
135 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
137 /* Unprivileged functions may not be able to read board cfg */
144 encp->enc_board_type = board_type;
145 encp->enc_clk_mult = 1; /* not used for Medford */
147 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
148 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
151 /* Obtain the default PHY advertised capabilities */
152 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
154 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
155 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
158 * Enable firmware workarounds for hardware errata.
159 * Expected responses are:
161 * Success: workaround enabled or disabled as requested.
162 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
163 * Firmware does not support the MC_CMD_WORKAROUND request.
164 * (assume that the workaround is not supported).
165 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
166 * Firmware does not support the requested workaround.
167 * - MC_CMD_ERR_EPERM (reported as EACCES):
168 * Unprivileged function cannot enable/disable workarounds.
170 * See efx_mcdi_request_errcode() for MCDI error translations.
174 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
176 * Interrupt testing does not work for VFs. See bug50084 and
177 * bug71432 comment 21.
179 encp->enc_bug41750_workaround = B_TRUE;
182 /* Chained multicast is always enabled on Medford */
183 encp->enc_bug26807_workaround = B_TRUE;
186 * If the bug61265 workaround is enabled, then interrupt holdoff timers
187 * cannot be controlled by timer table writes, so MCDI must be used
188 * (timer table writes can still be used for wakeup timers).
190 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
192 if ((rc == 0) || (rc == EACCES))
193 encp->enc_bug61265_workaround = B_TRUE;
194 else if ((rc == ENOTSUP) || (rc == ENOENT))
195 encp->enc_bug61265_workaround = B_FALSE;
199 /* Get clock frequencies (in MHz). */
200 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
204 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
205 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
207 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
208 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
209 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
211 /* Check capabilities of running datapath firmware */
212 if ((rc = ef10_get_datapath_caps(enp)) != 0)
215 /* Alignment for receive packet DMA buffers */
216 encp->enc_rx_buf_align_start = 1;
218 /* Get the RX DMA end padding alignment configuration */
219 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
223 /* Assume largest tail padding size supported by hardware */
226 encp->enc_rx_buf_align_end = end_padding;
228 /* Alignment for WPTR updates */
229 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
232 * Maximum number of exclusive RSS contexts which can be allocated. The
233 * hardware supports 64, but 6 are reserved for shared contexts. They
234 * are a global resource so not all may be available.
236 encp->enc_rx_scale_max_exclusive_contexts = 58;
238 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
239 /* No boundary crossing limits */
240 encp->enc_tx_dma_desc_boundary = 0;
243 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
244 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
245 * resources (allocated to this PCIe function), which is zero until
246 * after we have allocated VIs.
248 encp->enc_evq_limit = 1024;
249 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
250 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
253 * The maximum supported transmit queue size is 2048. TXQs with 4096
254 * descriptors are not supported as the top bit is used for vfifo
257 encp->enc_txq_max_ndescs = 2048;
259 encp->enc_buftbl_limit = 0xFFFFFFFF;
261 EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
262 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
263 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
264 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
267 * Get the current privilege mask. Note that this may be modified
268 * dynamically, so this value is informational only. DO NOT use
269 * the privilege mask to check for sufficient privileges, as that
270 * can result in time-of-check/time-of-use bugs.
272 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
274 encp->enc_privilege_mask = mask;
276 /* Get interrupt vector limits */
277 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
278 if (EFX_PCI_FUNCTION_IS_PF(encp))
281 /* Ignore error (cannot query vector limits from a VF). */
285 encp->enc_intr_vec_base = base;
286 encp->enc_intr_limit = nvec;
289 * Maximum number of bytes into the frame the TCP header can start for
290 * firmware assisted TSO to work.
292 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
295 * Medford stores a single global copy of VPD, not per-PF as on
298 encp->enc_vpd_is_global = B_TRUE;
300 rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
303 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
304 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
335 EFSYS_PROBE1(fail1, efx_rc_t, rc);
340 #endif /* EFSYS_OPT_MEDFORD */