1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2015-2019 Solarflare Communications Inc.
13 static __checkReturn efx_rc_t
14 medford_nic_get_required_pcie_bandwidth(
16 __out uint32_t *bandwidth_mbpsp)
21 if ((rc = ef10_nic_get_port_mode_bandwidth(enp,
25 *bandwidth_mbpsp = bandwidth;
30 EFSYS_PROBE1(fail1, efx_rc_t, rc);
35 __checkReturn efx_rc_t
39 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
40 uint32_t sysclk, dpcpu_clk;
46 * Enable firmware workarounds for hardware errata.
47 * Expected responses are:
49 * Success: workaround enabled or disabled as requested.
50 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
51 * Firmware does not support the MC_CMD_WORKAROUND request.
52 * (assume that the workaround is not supported).
53 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
54 * Firmware does not support the requested workaround.
55 * - MC_CMD_ERR_EPERM (reported as EACCES):
56 * Unprivileged function cannot enable/disable workarounds.
58 * See efx_mcdi_request_errcode() for MCDI error translations.
62 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
64 * Interrupt testing does not work for VFs. See bug50084 and
65 * bug71432 comment 21.
67 encp->enc_bug41750_workaround = B_TRUE;
71 * If the bug61265 workaround is enabled, then interrupt holdoff timers
72 * cannot be controlled by timer table writes, so MCDI must be used
73 * (timer table writes can still be used for wakeup timers).
75 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
77 if ((rc == 0) || (rc == EACCES))
78 encp->enc_bug61265_workaround = B_TRUE;
79 else if ((rc == ENOTSUP) || (rc == ENOENT))
80 encp->enc_bug61265_workaround = B_FALSE;
84 /* Checksums for TSO sends can be incorrect on Medford. */
85 encp->enc_bug61297_workaround = B_TRUE;
87 /* Get clock frequencies (in MHz). */
88 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
92 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
93 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
95 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
96 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
97 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
99 encp->enc_ev_desc_size = EF10_EVQ_DESC_SIZE;
100 encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE;
101 encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;
103 /* Alignment for receive packet DMA buffers */
104 encp->enc_rx_buf_align_start = 1;
106 /* Get the RX DMA end padding alignment configuration */
107 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
111 /* Assume largest tail padding size supported by hardware */
114 encp->enc_rx_buf_align_end = end_padding;
116 encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS;
117 encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS;
119 encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
120 encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
123 * The maximum supported transmit queue size is 2048. TXQs with 4096
124 * descriptors are not supported as the top bit is used for vfifo
127 encp->enc_txq_max_ndescs = MEDFORD_TXQ_MAXNDESCS;
128 encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;
130 EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
131 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
132 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
133 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
136 * Medford stores a single global copy of VPD, not per-PF as on
139 encp->enc_vpd_is_global = B_TRUE;
141 rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
144 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
145 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
156 EFSYS_PROBE1(fail1, efx_rc_t, rc);
161 #endif /* EFSYS_OPT_MEDFORD */