1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
13 static __checkReturn efx_rc_t
14 medford_nic_get_required_pcie_bandwidth(
16 __out uint32_t *bandwidth_mbpsp)
19 uint32_t current_mode;
23 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
24 ¤t_mode)) != 0) {
25 /* No port mode info available. */
30 if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
35 *bandwidth_mbpsp = bandwidth;
40 EFSYS_PROBE1(fail1, efx_rc_t, rc);
45 __checkReturn efx_rc_t
49 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
51 uint32_t sysclk, dpcpu_clk;
58 * FIXME: Likely to be incomplete and incorrect.
59 * Parts of this should be shared with Huntington.
62 /* Medford has a fixed 8Kbyte VI window size */
63 EFX_STATIC_ASSERT(ER_DZ_EVQ_RPTR_REG_STEP == 8192);
64 EFX_STATIC_ASSERT(ER_DZ_EVQ_TMR_REG_STEP == 8192);
65 EFX_STATIC_ASSERT(ER_DZ_RX_DESC_UPD_REG_STEP == 8192);
66 EFX_STATIC_ASSERT(ER_DZ_TX_DESC_UPD_REG_STEP == 8192);
67 EFX_STATIC_ASSERT(ER_DZ_TX_PIOBUF_STEP == 8192);
69 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
70 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
73 * Enable firmware workarounds for hardware errata.
74 * Expected responses are:
76 * Success: workaround enabled or disabled as requested.
77 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
78 * Firmware does not support the MC_CMD_WORKAROUND request.
79 * (assume that the workaround is not supported).
80 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
81 * Firmware does not support the requested workaround.
82 * - MC_CMD_ERR_EPERM (reported as EACCES):
83 * Unprivileged function cannot enable/disable workarounds.
85 * See efx_mcdi_request_errcode() for MCDI error translations.
89 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
91 * Interrupt testing does not work for VFs. See bug50084 and
92 * bug71432 comment 21.
94 encp->enc_bug41750_workaround = B_TRUE;
97 /* Chained multicast is always enabled on Medford */
98 encp->enc_bug26807_workaround = B_TRUE;
101 * If the bug61265 workaround is enabled, then interrupt holdoff timers
102 * cannot be controlled by timer table writes, so MCDI must be used
103 * (timer table writes can still be used for wakeup timers).
105 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
107 if ((rc == 0) || (rc == EACCES))
108 encp->enc_bug61265_workaround = B_TRUE;
109 else if ((rc == ENOTSUP) || (rc == ENOENT))
110 encp->enc_bug61265_workaround = B_FALSE;
114 /* Get clock frequencies (in MHz). */
115 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
119 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
120 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
122 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
123 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
124 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
126 /* Check capabilities of running datapath firmware */
127 if ((rc = ef10_get_datapath_caps(enp)) != 0)
130 /* Alignment for receive packet DMA buffers */
131 encp->enc_rx_buf_align_start = 1;
133 /* Get the RX DMA end padding alignment configuration */
134 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
138 /* Assume largest tail padding size supported by hardware */
141 encp->enc_rx_buf_align_end = end_padding;
143 /* Alignment for WPTR updates */
144 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
147 * Maximum number of exclusive RSS contexts which can be allocated. The
148 * hardware supports 64, but 6 are reserved for shared contexts. They
149 * are a global resource so not all may be available.
151 encp->enc_rx_scale_max_exclusive_contexts = 58;
153 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
154 /* No boundary crossing limits */
155 encp->enc_tx_dma_desc_boundary = 0;
158 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
159 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
160 * resources (allocated to this PCIe function), which is zero until
161 * after we have allocated VIs.
163 encp->enc_evq_limit = 1024;
164 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
165 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
168 * The maximum supported transmit queue size is 2048. TXQs with 4096
169 * descriptors are not supported as the top bit is used for vfifo
172 encp->enc_txq_max_ndescs = 2048;
174 encp->enc_buftbl_limit = 0xFFFFFFFF;
176 EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
177 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
178 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
179 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
182 * Get the current privilege mask. Note that this may be modified
183 * dynamically, so this value is informational only. DO NOT use
184 * the privilege mask to check for sufficient privileges, as that
185 * can result in time-of-check/time-of-use bugs.
187 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
189 encp->enc_privilege_mask = mask;
191 /* Get interrupt vector limits */
192 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
193 if (EFX_PCI_FUNCTION_IS_PF(encp))
196 /* Ignore error (cannot query vector limits from a VF). */
200 encp->enc_intr_vec_base = base;
201 encp->enc_intr_limit = nvec;
204 * Maximum number of bytes into the frame the TCP header can start for
205 * firmware assisted TSO to work.
207 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
210 * Medford stores a single global copy of VPD, not per-PF as on
213 encp->enc_vpd_is_global = B_TRUE;
215 rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
218 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
219 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
236 EFSYS_PROBE1(fail1, efx_rc_t, rc);
241 #endif /* EFSYS_OPT_MEDFORD */