2 * Copyright (c) 2015-2016 Solarflare Communications Inc.
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6 * modification, are permitted provided that the following conditions are met:
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11 * this list of conditions and the following disclaimer in the documentation
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37 static __checkReturn efx_rc_t
38 efx_mcdi_get_rxdp_config(
40 __out uint32_t *end_paddingp)
43 uint8_t payload[MAX(MC_CMD_GET_RXDP_CONFIG_IN_LEN,
44 MC_CMD_GET_RXDP_CONFIG_OUT_LEN)];
48 memset(payload, 0, sizeof (payload));
49 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
50 req.emr_in_buf = payload;
51 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
52 req.emr_out_buf = payload;
53 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
55 efx_mcdi_execute(enp, &req);
56 if (req.emr_rc != 0) {
61 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
62 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
63 /* RX DMA end padding is disabled */
66 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
67 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
68 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
71 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
74 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
83 *end_paddingp = end_padding;
90 EFSYS_PROBE1(fail1, efx_rc_t, rc);
95 static __checkReturn efx_rc_t
96 medford_nic_get_required_pcie_bandwidth(
98 __out uint32_t *bandwidth_mbpsp)
101 uint32_t current_mode;
105 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
106 ¤t_mode)) != 0) {
107 /* No port mode info available. */
112 if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
117 *bandwidth_mbpsp = bandwidth;
122 EFSYS_PROBE1(fail1, efx_rc_t, rc);
127 __checkReturn efx_rc_t
131 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
132 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
133 uint8_t mac_addr[6] = { 0 };
134 uint32_t board_type = 0;
135 ef10_link_state_t els;
136 efx_port_t *epp = &(enp->en_port);
141 uint32_t sysclk, dpcpu_clk;
143 uint32_t end_padding;
148 * FIXME: Likely to be incomplete and incorrect.
149 * Parts of this should be shared with Huntington.
152 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
156 * NOTE: The MCDI protocol numbers ports from zero.
157 * The common code MCDI interface numbers ports from one.
159 emip->emi_port = port + 1;
161 if ((rc = ef10_external_port_mapping(enp, port,
162 &encp->enc_external_port)) != 0)
166 * Get PCIe function number from firmware (used for
167 * per-function privilege and dynamic config info).
168 * - PCIe PF: pf = PF number, vf = 0xffff.
169 * - PCIe VF: pf = parent PF, vf = VF number.
171 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
177 /* MAC address for this function */
178 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
179 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
180 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
181 /* Disable static config checking for Medford NICs, ONLY
182 * for manufacturing test and setup at the factory, to
183 * allow the static config to be installed.
185 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
186 if ((rc == 0) && (mac_addr[0] & 0x02)) {
188 * If the static config does not include a global MAC
189 * address pool then the board may return a locally
190 * administered MAC address (this should only happen on
191 * incorrectly programmed boards).
195 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
197 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
202 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
204 /* Board configuration */
205 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
207 /* Unprivileged functions may not be able to read board cfg */
214 encp->enc_board_type = board_type;
215 encp->enc_clk_mult = 1; /* not used for Medford */
217 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
218 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
221 /* Obtain the default PHY advertised capabilities */
222 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
224 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
225 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
228 * Enable firmware workarounds for hardware errata.
229 * Expected responses are:
231 * Success: workaround enabled or disabled as requested.
232 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
233 * Firmware does not support the MC_CMD_WORKAROUND request.
234 * (assume that the workaround is not supported).
235 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
236 * Firmware does not support the requested workaround.
237 * - MC_CMD_ERR_EPERM (reported as EACCES):
238 * Unprivileged function cannot enable/disable workarounds.
240 * See efx_mcdi_request_errcode() for MCDI error translations.
244 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
246 * Interrupt testing does not work for VFs. See bug50084.
247 * FIXME: Does this still apply to Medford?
249 encp->enc_bug41750_workaround = B_TRUE;
252 /* Chained multicast is always enabled on Medford */
253 encp->enc_bug26807_workaround = B_TRUE;
256 * If the bug61265 workaround is enabled, then interrupt holdoff timers
257 * cannot be controlled by timer table writes, so MCDI must be used
258 * (timer table writes can still be used for wakeup timers).
260 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
262 if ((rc == 0) || (rc == EACCES))
263 encp->enc_bug61265_workaround = B_TRUE;
264 else if ((rc == ENOTSUP) || (rc == ENOENT))
265 encp->enc_bug61265_workaround = B_FALSE;
269 /* Get clock frequencies (in MHz). */
270 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
274 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
275 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
277 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
278 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
279 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
281 /* Check capabilities of running datapath firmware */
282 if ((rc = ef10_get_datapath_caps(enp)) != 0)
285 /* Alignment for receive packet DMA buffers */
286 encp->enc_rx_buf_align_start = 1;
288 /* Get the RX DMA end padding alignment configuration */
289 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
293 /* Assume largest tail padding size supported by hardware */
296 encp->enc_rx_buf_align_end = end_padding;
298 /* Alignment for WPTR updates */
299 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
302 * Maximum number of exclusive RSS contexts which can be allocated. The
303 * hardware supports 64, but 6 are reserved for shared contexts. They
304 * are a global resource so not all may be available.
306 encp->enc_rx_scale_max_exclusive_contexts = 58;
308 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
309 /* No boundary crossing limits */
310 encp->enc_tx_dma_desc_boundary = 0;
313 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
314 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
315 * resources (allocated to this PCIe function), which is zero until
316 * after we have allocated VIs.
318 encp->enc_evq_limit = 1024;
319 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
320 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
323 * The maximum supported transmit queue size is 2048. TXQs with 4096
324 * descriptors are not supported as the top bit is used for vfifo
327 encp->enc_txq_max_ndescs = 2048;
329 encp->enc_buftbl_limit = 0xFFFFFFFF;
331 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
332 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
333 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
336 * Get the current privilege mask. Note that this may be modified
337 * dynamically, so this value is informational only. DO NOT use
338 * the privilege mask to check for sufficient privileges, as that
339 * can result in time-of-check/time-of-use bugs.
341 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
343 encp->enc_privilege_mask = mask;
345 /* Get interrupt vector limits */
346 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
347 if (EFX_PCI_FUNCTION_IS_PF(encp))
350 /* Ignore error (cannot query vector limits from a VF). */
354 encp->enc_intr_vec_base = base;
355 encp->enc_intr_limit = nvec;
358 * Maximum number of bytes into the frame the TCP header can start for
359 * firmware assisted TSO to work.
361 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
364 * Medford stores a single global copy of VPD, not per-PF as on
367 encp->enc_vpd_is_global = B_TRUE;
369 rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
372 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
373 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
404 EFSYS_PROBE1(fail1, efx_rc_t, rc);
409 #endif /* EFSYS_OPT_MEDFORD */