1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
13 static __checkReturn efx_rc_t
14 medford_nic_get_required_pcie_bandwidth(
16 __out uint32_t *bandwidth_mbpsp)
19 uint32_t current_mode;
23 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
24 ¤t_mode)) != 0) {
25 /* No port mode info available. */
30 if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
35 *bandwidth_mbpsp = bandwidth;
40 EFSYS_PROBE1(fail1, efx_rc_t, rc);
45 __checkReturn efx_rc_t
49 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
50 uint32_t board_type = 0;
51 ef10_link_state_t els;
52 efx_port_t *epp = &(enp->en_port);
54 uint32_t sysclk, dpcpu_clk;
61 * FIXME: Likely to be incomplete and incorrect.
62 * Parts of this should be shared with Huntington.
65 /* Medford has a fixed 8Kbyte VI window size */
66 EFX_STATIC_ASSERT(ER_DZ_EVQ_RPTR_REG_STEP == 8192);
67 EFX_STATIC_ASSERT(ER_DZ_EVQ_TMR_REG_STEP == 8192);
68 EFX_STATIC_ASSERT(ER_DZ_RX_DESC_UPD_REG_STEP == 8192);
69 EFX_STATIC_ASSERT(ER_DZ_TX_DESC_UPD_REG_STEP == 8192);
70 EFX_STATIC_ASSERT(ER_DZ_TX_PIOBUF_STEP == 8192);
72 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
73 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
75 /* Board configuration */
76 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
78 /* Unprivileged functions may not be able to read board cfg */
85 encp->enc_board_type = board_type;
86 encp->enc_clk_mult = 1; /* not used for Medford */
88 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
89 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
92 /* Obtain the default PHY advertised capabilities */
93 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
95 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
96 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
99 * Enable firmware workarounds for hardware errata.
100 * Expected responses are:
102 * Success: workaround enabled or disabled as requested.
103 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
104 * Firmware does not support the MC_CMD_WORKAROUND request.
105 * (assume that the workaround is not supported).
106 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
107 * Firmware does not support the requested workaround.
108 * - MC_CMD_ERR_EPERM (reported as EACCES):
109 * Unprivileged function cannot enable/disable workarounds.
111 * See efx_mcdi_request_errcode() for MCDI error translations.
115 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
117 * Interrupt testing does not work for VFs. See bug50084 and
118 * bug71432 comment 21.
120 encp->enc_bug41750_workaround = B_TRUE;
123 /* Chained multicast is always enabled on Medford */
124 encp->enc_bug26807_workaround = B_TRUE;
127 * If the bug61265 workaround is enabled, then interrupt holdoff timers
128 * cannot be controlled by timer table writes, so MCDI must be used
129 * (timer table writes can still be used for wakeup timers).
131 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
133 if ((rc == 0) || (rc == EACCES))
134 encp->enc_bug61265_workaround = B_TRUE;
135 else if ((rc == ENOTSUP) || (rc == ENOENT))
136 encp->enc_bug61265_workaround = B_FALSE;
140 /* Get clock frequencies (in MHz). */
141 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
145 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
146 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
148 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
149 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
150 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
152 /* Check capabilities of running datapath firmware */
153 if ((rc = ef10_get_datapath_caps(enp)) != 0)
156 /* Alignment for receive packet DMA buffers */
157 encp->enc_rx_buf_align_start = 1;
159 /* Get the RX DMA end padding alignment configuration */
160 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
164 /* Assume largest tail padding size supported by hardware */
167 encp->enc_rx_buf_align_end = end_padding;
169 /* Alignment for WPTR updates */
170 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
173 * Maximum number of exclusive RSS contexts which can be allocated. The
174 * hardware supports 64, but 6 are reserved for shared contexts. They
175 * are a global resource so not all may be available.
177 encp->enc_rx_scale_max_exclusive_contexts = 58;
179 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
180 /* No boundary crossing limits */
181 encp->enc_tx_dma_desc_boundary = 0;
184 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
185 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
186 * resources (allocated to this PCIe function), which is zero until
187 * after we have allocated VIs.
189 encp->enc_evq_limit = 1024;
190 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
191 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
194 * The maximum supported transmit queue size is 2048. TXQs with 4096
195 * descriptors are not supported as the top bit is used for vfifo
198 encp->enc_txq_max_ndescs = 2048;
200 encp->enc_buftbl_limit = 0xFFFFFFFF;
202 EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
203 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
204 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
205 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
208 * Get the current privilege mask. Note that this may be modified
209 * dynamically, so this value is informational only. DO NOT use
210 * the privilege mask to check for sufficient privileges, as that
211 * can result in time-of-check/time-of-use bugs.
213 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
215 encp->enc_privilege_mask = mask;
217 /* Get interrupt vector limits */
218 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
219 if (EFX_PCI_FUNCTION_IS_PF(encp))
222 /* Ignore error (cannot query vector limits from a VF). */
226 encp->enc_intr_vec_base = base;
227 encp->enc_intr_limit = nvec;
230 * Maximum number of bytes into the frame the TCP header can start for
231 * firmware assisted TSO to work.
233 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
236 * Medford stores a single global copy of VPD, not per-PF as on
239 encp->enc_vpd_is_global = B_TRUE;
241 rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
244 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
245 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
268 EFSYS_PROBE1(fail1, efx_rc_t, rc);
273 #endif /* EFSYS_OPT_MEDFORD */