1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
13 static __checkReturn efx_rc_t
14 medford_nic_get_required_pcie_bandwidth(
16 __out uint32_t *bandwidth_mbpsp)
19 uint32_t current_mode;
23 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
24 ¤t_mode)) != 0) {
25 /* No port mode info available. */
30 if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
35 *bandwidth_mbpsp = bandwidth;
40 EFSYS_PROBE1(fail1, efx_rc_t, rc);
45 __checkReturn efx_rc_t
49 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
50 uint32_t sysclk, dpcpu_clk;
56 * FIXME: Likely to be incomplete and incorrect.
57 * Parts of this should be shared with Huntington.
61 * Enable firmware workarounds for hardware errata.
62 * Expected responses are:
64 * Success: workaround enabled or disabled as requested.
65 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
66 * Firmware does not support the MC_CMD_WORKAROUND request.
67 * (assume that the workaround is not supported).
68 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
69 * Firmware does not support the requested workaround.
70 * - MC_CMD_ERR_EPERM (reported as EACCES):
71 * Unprivileged function cannot enable/disable workarounds.
73 * See efx_mcdi_request_errcode() for MCDI error translations.
77 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
79 * Interrupt testing does not work for VFs. See bug50084 and
80 * bug71432 comment 21.
82 encp->enc_bug41750_workaround = B_TRUE;
85 /* Chained multicast is always enabled on Medford */
86 encp->enc_bug26807_workaround = B_TRUE;
89 * If the bug61265 workaround is enabled, then interrupt holdoff timers
90 * cannot be controlled by timer table writes, so MCDI must be used
91 * (timer table writes can still be used for wakeup timers).
93 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
95 if ((rc == 0) || (rc == EACCES))
96 encp->enc_bug61265_workaround = B_TRUE;
97 else if ((rc == ENOTSUP) || (rc == ENOENT))
98 encp->enc_bug61265_workaround = B_FALSE;
102 /* Get clock frequencies (in MHz). */
103 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
107 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
108 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
110 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
111 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
112 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
114 /* Alignment for receive packet DMA buffers */
115 encp->enc_rx_buf_align_start = 1;
117 /* Get the RX DMA end padding alignment configuration */
118 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
122 /* Assume largest tail padding size supported by hardware */
125 encp->enc_rx_buf_align_end = end_padding;
128 * The maximum supported transmit queue size is 2048. TXQs with 4096
129 * descriptors are not supported as the top bit is used for vfifo
132 encp->enc_txq_max_ndescs = 2048;
134 EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
135 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
136 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
137 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
140 * Medford stores a single global copy of VPD, not per-PF as on
143 encp->enc_vpd_is_global = B_TRUE;
145 rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
148 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
149 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
160 EFSYS_PROBE1(fail1, efx_rc_t, rc);
165 #endif /* EFSYS_OPT_MEDFORD */