1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
13 static __checkReturn efx_rc_t
14 medford_nic_get_required_pcie_bandwidth(
16 __out uint32_t *bandwidth_mbpsp)
19 uint32_t current_mode;
23 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
24 ¤t_mode)) != 0) {
25 /* No port mode info available. */
30 if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
35 *bandwidth_mbpsp = bandwidth;
40 EFSYS_PROBE1(fail1, efx_rc_t, rc);
45 __checkReturn efx_rc_t
49 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
50 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
51 uint8_t mac_addr[6] = { 0 };
52 uint32_t board_type = 0;
53 ef10_link_state_t els;
54 efx_port_t *epp = &(enp->en_port);
59 uint32_t sysclk, dpcpu_clk;
66 * FIXME: Likely to be incomplete and incorrect.
67 * Parts of this should be shared with Huntington.
70 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
74 * NOTE: The MCDI protocol numbers ports from zero.
75 * The common code MCDI interface numbers ports from one.
77 emip->emi_port = port + 1;
79 if ((rc = ef10_external_port_mapping(enp, port,
80 &encp->enc_external_port)) != 0)
84 * Get PCIe function number from firmware (used for
85 * per-function privilege and dynamic config info).
86 * - PCIe PF: pf = PF number, vf = 0xffff.
87 * - PCIe VF: pf = parent PF, vf = VF number.
89 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
95 /* MAC address for this function */
96 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
97 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
98 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
100 * Disable static config checking for Medford NICs, ONLY
101 * for manufacturing test and setup at the factory, to
102 * allow the static config to be installed.
104 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
105 if ((rc == 0) && (mac_addr[0] & 0x02)) {
107 * If the static config does not include a global MAC
108 * address pool then the board may return a locally
109 * administered MAC address (this should only happen on
110 * incorrectly programmed boards).
114 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
116 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
121 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
123 /* Board configuration */
124 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
126 /* Unprivileged functions may not be able to read board cfg */
133 encp->enc_board_type = board_type;
134 encp->enc_clk_mult = 1; /* not used for Medford */
136 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
137 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
140 /* Obtain the default PHY advertised capabilities */
141 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
143 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
144 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
147 * Enable firmware workarounds for hardware errata.
148 * Expected responses are:
150 * Success: workaround enabled or disabled as requested.
151 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
152 * Firmware does not support the MC_CMD_WORKAROUND request.
153 * (assume that the workaround is not supported).
154 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
155 * Firmware does not support the requested workaround.
156 * - MC_CMD_ERR_EPERM (reported as EACCES):
157 * Unprivileged function cannot enable/disable workarounds.
159 * See efx_mcdi_request_errcode() for MCDI error translations.
163 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
165 * Interrupt testing does not work for VFs. See bug50084.
166 * FIXME: Does this still apply to Medford?
168 encp->enc_bug41750_workaround = B_TRUE;
171 /* Chained multicast is always enabled on Medford */
172 encp->enc_bug26807_workaround = B_TRUE;
175 * If the bug61265 workaround is enabled, then interrupt holdoff timers
176 * cannot be controlled by timer table writes, so MCDI must be used
177 * (timer table writes can still be used for wakeup timers).
179 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
181 if ((rc == 0) || (rc == EACCES))
182 encp->enc_bug61265_workaround = B_TRUE;
183 else if ((rc == ENOTSUP) || (rc == ENOENT))
184 encp->enc_bug61265_workaround = B_FALSE;
188 /* Get clock frequencies (in MHz). */
189 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
193 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
194 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
196 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
197 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
198 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
200 /* Check capabilities of running datapath firmware */
201 if ((rc = ef10_get_datapath_caps(enp)) != 0)
204 /* Alignment for receive packet DMA buffers */
205 encp->enc_rx_buf_align_start = 1;
207 /* Get the RX DMA end padding alignment configuration */
208 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
212 /* Assume largest tail padding size supported by hardware */
215 encp->enc_rx_buf_align_end = end_padding;
217 /* Alignment for WPTR updates */
218 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
221 * Maximum number of exclusive RSS contexts which can be allocated. The
222 * hardware supports 64, but 6 are reserved for shared contexts. They
223 * are a global resource so not all may be available.
225 encp->enc_rx_scale_max_exclusive_contexts = 58;
227 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
228 /* No boundary crossing limits */
229 encp->enc_tx_dma_desc_boundary = 0;
232 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
233 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
234 * resources (allocated to this PCIe function), which is zero until
235 * after we have allocated VIs.
237 encp->enc_evq_limit = 1024;
238 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
239 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
242 * The maximum supported transmit queue size is 2048. TXQs with 4096
243 * descriptors are not supported as the top bit is used for vfifo
246 encp->enc_txq_max_ndescs = 2048;
248 encp->enc_buftbl_limit = 0xFFFFFFFF;
250 EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
251 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
252 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
253 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
256 * Get the current privilege mask. Note that this may be modified
257 * dynamically, so this value is informational only. DO NOT use
258 * the privilege mask to check for sufficient privileges, as that
259 * can result in time-of-check/time-of-use bugs.
261 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
263 encp->enc_privilege_mask = mask;
265 /* Get interrupt vector limits */
266 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
267 if (EFX_PCI_FUNCTION_IS_PF(encp))
270 /* Ignore error (cannot query vector limits from a VF). */
274 encp->enc_intr_vec_base = base;
275 encp->enc_intr_limit = nvec;
278 * Maximum number of bytes into the frame the TCP header can start for
279 * firmware assisted TSO to work.
281 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
284 * Medford stores a single global copy of VPD, not per-PF as on
287 encp->enc_vpd_is_global = B_TRUE;
289 rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
292 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
293 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
324 EFSYS_PROBE1(fail1, efx_rc_t, rc);
329 #endif /* EFSYS_OPT_MEDFORD */