2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
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6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
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11 * this list of conditions and the following disclaimer in the documentation
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31 #ifndef _SYS_SIENA_FLASH_H
32 #define _SYS_SIENA_FLASH_H
36 /* Fixed locations near the start of flash (which may be in the internal PHY
37 * firmware header) point to the boot header.
39 * - parsed by MC boot ROM and firmware
40 * - reserved (but not parsed) by PHY firmware
44 #define SIENA_MC_BOOT_PHY_FW_HDR_LEN (0x20)
46 #define SIENA_MC_BOOT_PTR_LOCATION (0x18) /* First thing we try to boot */
47 #define SIENA_MC_BOOT_ALT_PTR_LOCATION (0x1c) /* Alternative if that fails */
49 #define SIENA_MC_BOOT_HDR_LEN (0x200)
51 #define SIENA_MC_BOOT_MAGIC (0x51E4A001)
52 #define SIENA_MC_BOOT_VERSION (1)
55 /*Structures supporting an arbitrary number of binary blobs in the flash image
56 intended to house code and tables for the satellite cpus*/
57 /*thanks to random.org for:*/
58 #define BLOBS_HEADER_MAGIC (0xBDA3BBD4)
59 #define BLOB_HEADER_MAGIC (0xA1478A91)
61 typedef struct blobs_hdr_s { /* GENERATED BY scripts/genfwdef */
63 efx_dword_t no_of_blobs;
66 typedef struct blob_hdr_s { /* GENERATED BY scripts/genfwdef */
69 efx_dword_t build_variant;
75 #define BLOB_CPU_TYPE_TXDI_TEXT (0)
76 #define BLOB_CPU_TYPE_RXDI_TEXT (1)
77 #define BLOB_CPU_TYPE_TXDP_TEXT (2)
78 #define BLOB_CPU_TYPE_RXDP_TEXT (3)
79 #define BLOB_CPU_TYPE_RXHRSL_HR_LUT (4)
80 #define BLOB_CPU_TYPE_RXHRSL_HR_LUT_CFG (5)
81 #define BLOB_CPU_TYPE_TXHRSL_HR_LUT (6)
82 #define BLOB_CPU_TYPE_TXHRSL_HR_LUT_CFG (7)
83 #define BLOB_CPU_TYPE_RXHRSL_HR_PGM (8)
84 #define BLOB_CPU_TYPE_RXHRSL_SL_PGM (9)
85 #define BLOB_CPU_TYPE_TXHRSL_HR_PGM (10)
86 #define BLOB_CPU_TYPE_TXHRSL_SL_PGM (11)
87 #define BLOB_CPU_TYPE_RXDI_VTBL0 (12)
88 #define BLOB_CPU_TYPE_TXDI_VTBL0 (13)
89 #define BLOB_CPU_TYPE_RXDI_VTBL1 (14)
90 #define BLOB_CPU_TYPE_TXDI_VTBL1 (15)
91 #define BLOB_CPU_TYPE_DUMPSPEC (32)
92 #define BLOB_CPU_TYPE_MC_XIP (33)
94 #define BLOB_CPU_TYPE_INVALID (31)
97 * The upper four bits of the CPU type field specify the compression
98 * algorithm used for this blob.
100 #define BLOB_COMPRESSION_MASK (0xf0000000)
101 #define BLOB_CPU_TYPE_MASK (0x0fffffff)
103 #define BLOB_COMPRESSION_NONE (0x00000000) /* Stored as is */
104 #define BLOB_COMPRESSION_LZ (0x10000000) /* see lib/lzdecoder.c */
106 typedef struct siena_mc_boot_hdr_s { /* GENERATED BY scripts/genfwdef */
107 efx_dword_t magic; /* = SIENA_MC_BOOT_MAGIC */
108 efx_word_t hdr_version; /* this structure definition is version 1 */
109 efx_byte_t board_type;
110 efx_byte_t firmware_version_a;
111 efx_byte_t firmware_version_b;
112 efx_byte_t firmware_version_c;
113 efx_word_t checksum; /* of whole header area + firmware image */
114 efx_word_t firmware_version_d;
115 efx_byte_t mcfw_subtype;
116 efx_byte_t generation; /* MC (Medford and later): MC partition generation when */
117 /* written to NVRAM. */
118 /* MUM & SUC images: subtype. */
119 /* (Otherwise set to 0) */
120 efx_dword_t firmware_text_offset; /* offset to firmware .text */
121 efx_dword_t firmware_text_size; /* length of firmware .text, in bytes */
122 efx_dword_t firmware_data_offset; /* offset to firmware .data */
123 efx_dword_t firmware_data_size; /* length of firmware .data, in bytes */
124 efx_byte_t spi_rate; /* SPI rate for reading image, 0 is BootROM default */
125 efx_byte_t spi_phase_adj; /* SPI SDO/SCL phase adjustment, 0 is default (no adj) */
126 efx_word_t xpm_sector; /* XPM (MEDFORD and later): The sector that contains */
127 /* the key, or 0xffff if unsigned. (Otherwise set to 0) */
128 efx_byte_t mumfw_subtype; /* MUM & SUC images: subtype. (Otherwise set to 0) */
129 efx_byte_t reserved_b[3]; /* (set to 0) */
130 efx_dword_t reserved_c[6]; /* (set to 0) */
131 } siena_mc_boot_hdr_t;
133 #define SIENA_MC_BOOT_HDR_PADDING \
134 (SIENA_MC_BOOT_HDR_LEN - sizeof(siena_mc_boot_hdr_t))
136 #define SIENA_MC_STATIC_CONFIG_MAGIC (0xBDCF5555)
137 #define SIENA_MC_STATIC_CONFIG_VERSION (0)
139 typedef struct siena_mc_static_config_hdr_s { /* GENERATED BY scripts/genfwdef */
140 efx_dword_t magic; /* = SIENA_MC_STATIC_CONFIG_MAGIC */
141 efx_word_t length; /* of header area (i.e. not including VPD) */
143 efx_byte_t csum; /* over header area (i.e. not including VPD) */
144 efx_dword_t static_vpd_offset;
145 efx_dword_t static_vpd_length;
146 efx_dword_t capabilities;
147 efx_byte_t mac_addr_base[6];
148 efx_byte_t green_mode_cal; /* Green mode calibration result */
149 efx_byte_t green_mode_valid; /* Whether cal holds a valid value */
150 efx_word_t mac_addr_count;
151 efx_word_t mac_addr_stride;
152 efx_word_t calibrated_vref; /* Vref as measured during production */
153 efx_word_t adc_vref; /* Vref as read by ADC */
154 efx_dword_t reserved2[1]; /* (write as zero) */
155 efx_dword_t num_dbi_items;
158 efx_word_t byte_enables;
161 } siena_mc_static_config_hdr_t;
163 /* This prefixes a valid XIP partition */
164 #define XIP_PARTITION_MAGIC (0x51DEC0DE)
166 #define SIENA_MC_DYNAMIC_CONFIG_MAGIC (0xBDCFDDDD)
167 #define SIENA_MC_DYNAMIC_CONFIG_VERSION (0)
169 typedef struct siena_mc_fw_version_s { /* GENERATED BY scripts/genfwdef */
170 efx_dword_t fw_subtype;
171 efx_word_t version_w;
172 efx_word_t version_x;
173 efx_word_t version_y;
174 efx_word_t version_z;
175 } siena_mc_fw_version_t;
177 typedef struct siena_mc_dynamic_config_hdr_s { /* GENERATED BY scripts/genfwdef */
178 efx_dword_t magic; /* = SIENA_MC_DYNAMIC_CONFIG_MAGIC */
179 efx_word_t length; /* of header area (i.e. not including VPD) */
181 efx_byte_t csum; /* over header area (i.e. not including VPD) */
182 efx_dword_t dynamic_vpd_offset;
183 efx_dword_t dynamic_vpd_length;
184 efx_dword_t num_fw_version_items;
185 siena_mc_fw_version_t fw_version[];
186 } siena_mc_dynamic_config_hdr_t;
188 #define SIENA_MC_EXPROM_SINGLE_MAGIC (0xAA55) /* little-endian uint16_t */
190 #define SIENA_MC_EXPROM_COMBO_MAGIC (0xB0070102) /* little-endian uint32_t */
191 #define SIENA_MC_EXPROM_COMBO_V2_MAGIC (0xB0070103) /* little-endian uint32_t */
193 typedef struct siena_mc_combo_rom_hdr_s { /* GENERATED BY scripts/genfwdef */
194 efx_dword_t magic; /* = SIENA_MC_EXPROM_COMBO_MAGIC or SIENA_MC_EXPROM_COMBO_V2_MAGIC */
197 efx_dword_t len1; /* length of first image */
198 efx_dword_t len2; /* length of second image */
199 efx_dword_t off1; /* offset of first byte to edit to combine images */
200 efx_dword_t off2; /* offset of second byte to edit to combine images */
201 efx_word_t infoblk0_off;/* infoblk offset */
202 efx_word_t infoblk1_off;/* infoblk offset */
203 efx_byte_t infoblk_len;/* length of space reserved for one infoblk structure */
204 efx_byte_t reserved[7];/* (set to 0) */
207 efx_dword_t len1; /* length of first image */
208 efx_dword_t len2; /* length of second image */
209 efx_dword_t off1; /* offset of first byte to edit to combine images */
210 efx_dword_t off2; /* offset of second byte to edit to combine images */
211 efx_word_t infoblk_off;/* infoblk start offset */
212 efx_word_t infoblk_count;/* infoblk count */
213 efx_byte_t infoblk_len;/* length of space reserved for one infoblk structure */
214 efx_byte_t reserved[7];/* (set to 0) */
217 } siena_mc_combo_rom_hdr_t;
221 #endif /* _SYS_SIENA_FLASH_H */