1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2009-2019 Solarflare Communications Inc.
12 __checkReturn efx_rc_t
15 __out efx_link_mode_t *link_modep)
17 efx_port_t *epp = &(enp->en_port);
18 siena_link_state_t sls;
21 if ((rc = siena_phy_get_link(enp, &sls)) != 0)
24 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask;
25 epp->ep_fcntl = sls.sls_fcntl;
27 *link_modep = sls.sls_link_mode;
32 EFSYS_PROBE1(fail1, efx_rc_t, rc);
34 *link_modep = EFX_LINK_UNKNOWN;
39 __checkReturn efx_rc_t
42 __out boolean_t *mac_upp)
44 siena_link_state_t sls;
48 * Because Siena doesn't *require* polling, we can't rely on
49 * siena_mac_poll() being executed to populate epp->ep_mac_up.
51 if ((rc = siena_phy_get_link(enp, &sls)) != 0)
54 *mac_upp = sls.sls_mac_up;
59 EFSYS_PROBE1(fail1, efx_rc_t, rc);
64 __checkReturn efx_rc_t
65 siena_mac_reconfigure(
68 efx_port_t *epp = &(enp->en_port);
69 efx_oword_t multicast_hash[2];
71 EFX_MCDI_DECLARE_BUF(payload,
72 MAX(MC_CMD_SET_MAC_IN_LEN, MC_CMD_SET_MCAST_HASH_IN_LEN),
73 MAX(MC_CMD_SET_MAC_OUT_LEN, MC_CMD_SET_MCAST_HASH_OUT_LEN));
78 req.emr_cmd = MC_CMD_SET_MAC;
79 req.emr_in_buf = payload;
80 req.emr_in_length = MC_CMD_SET_MAC_IN_LEN;
81 req.emr_out_buf = payload;
82 req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN;
84 MCDI_IN_SET_DWORD(req, SET_MAC_IN_MTU, epp->ep_mac_pdu);
85 MCDI_IN_SET_DWORD(req, SET_MAC_IN_DRAIN, epp->ep_mac_drain ? 1 : 0);
86 EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, SET_MAC_IN_ADDR),
88 MCDI_IN_POPULATE_DWORD_2(req, SET_MAC_IN_REJECT,
89 SET_MAC_IN_REJECT_UNCST, !epp->ep_all_unicst,
90 SET_MAC_IN_REJECT_BRDCST, !epp->ep_brdcst);
92 if (epp->ep_fcntl_autoneg)
93 /* efx_fcntl_set() has already set the phy capabilities */
94 fcntl = MC_CMD_FCNTL_AUTO;
95 else if (epp->ep_fcntl & EFX_FCNTL_RESPOND)
96 fcntl = (epp->ep_fcntl & EFX_FCNTL_GENERATE)
98 : MC_CMD_FCNTL_RESPOND;
100 fcntl = MC_CMD_FCNTL_OFF;
102 MCDI_IN_SET_DWORD(req, SET_MAC_IN_FCNTL, fcntl);
104 efx_mcdi_execute(enp, &req);
106 if (req.emr_rc != 0) {
110 epp->ep_all_unicst_inserted = epp->ep_all_unicst;
112 /* Push multicast hash */
114 if (epp->ep_all_mulcst) {
115 /* A hash matching all multicast is all 1s */
116 EFX_SET_OWORD(multicast_hash[0]);
117 EFX_SET_OWORD(multicast_hash[1]);
118 } else if (epp->ep_mulcst) {
119 /* Use the hash set by the multicast list */
120 multicast_hash[0] = epp->ep_multicst_hash[0];
121 multicast_hash[1] = epp->ep_multicst_hash[1];
123 /* A hash matching no traffic is simply 0 */
124 EFX_ZERO_OWORD(multicast_hash[0]);
125 EFX_ZERO_OWORD(multicast_hash[1]);
129 * Broadcast packets go through the multicast hash filter.
130 * The IEEE 802.3 CRC32 of the broadcast address is 0xbe2612ff
131 * so we always add bit 0xff to the mask (bit 0x7f in the
134 if (epp->ep_brdcst) {
136 * NOTE: due to constant folding, some of this evaluates
137 * to null expressions, giving E_EXPR_NULL_EFFECT during
138 * lint on Illumos. No good way to fix this without
139 * explicit coding the individual word/bit setting.
140 * So just suppress lint for this one line.
143 EFX_SET_OWORD_BIT(multicast_hash[1], 0x7f);
146 (void) memset(payload, 0, sizeof (payload));
147 req.emr_cmd = MC_CMD_SET_MCAST_HASH;
148 req.emr_in_buf = payload;
149 req.emr_in_length = MC_CMD_SET_MCAST_HASH_IN_LEN;
150 req.emr_out_buf = payload;
151 req.emr_out_length = MC_CMD_SET_MCAST_HASH_OUT_LEN;
153 memcpy(MCDI_IN2(req, uint8_t, SET_MCAST_HASH_IN_HASH0),
154 multicast_hash, sizeof (multicast_hash));
156 efx_mcdi_execute(enp, &req);
158 if (req.emr_rc != 0) {
162 epp->ep_all_mulcst_inserted = epp->ep_all_mulcst;
169 EFSYS_PROBE1(fail1, efx_rc_t, rc);
174 #if EFSYS_OPT_LOOPBACK
176 __checkReturn efx_rc_t
177 siena_mac_loopback_set(
179 __in efx_link_mode_t link_mode,
180 __in efx_loopback_type_t loopback_type)
182 efx_port_t *epp = &(enp->en_port);
183 const efx_phy_ops_t *epop = epp->ep_epop;
184 efx_loopback_type_t old_loopback_type;
185 efx_link_mode_t old_loopback_link_mode;
188 /* The PHY object handles this on Siena */
189 old_loopback_type = epp->ep_loopback_type;
190 old_loopback_link_mode = epp->ep_loopback_link_mode;
191 epp->ep_loopback_type = loopback_type;
192 epp->ep_loopback_link_mode = link_mode;
194 if ((rc = epop->epo_reconfigure(enp)) != 0)
200 EFSYS_PROBE1(fail1, efx_rc_t, rc);
202 epp->ep_loopback_type = old_loopback_type;
203 epp->ep_loopback_link_mode = old_loopback_link_mode;
208 #endif /* EFSYS_OPT_LOOPBACK */
210 #if EFSYS_OPT_MAC_STATS
212 __checkReturn efx_rc_t
213 siena_mac_stats_get_mask(
215 __inout_bcount(mask_size) uint32_t *maskp,
216 __in size_t mask_size)
218 const struct efx_mac_stats_range siena_stats[] = {
219 { EFX_MAC_RX_OCTETS, EFX_MAC_RX_GE_15XX_PKTS },
220 /* EFX_MAC_RX_ERRORS is not supported */
221 { EFX_MAC_RX_FCS_ERRORS, EFX_MAC_TX_EX_DEF_PKTS },
225 _NOTE(ARGUNUSED(enp))
227 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
228 siena_stats, EFX_ARRAY_SIZE(siena_stats))) != 0)
234 EFSYS_PROBE1(fail1, efx_rc_t, rc);
239 #define SIENA_MAC_STAT_READ(_esmp, _field, _eqp) \
240 EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp)
242 __checkReturn efx_rc_t
243 siena_mac_stats_update(
245 __in efsys_mem_t *esmp,
246 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
247 __inout_opt uint32_t *generationp)
249 const efx_nic_cfg_t *encp = &enp->en_nic_cfg;
250 efx_qword_t generation_start;
251 efx_qword_t generation_end;
255 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS) {
256 /* MAC stats count too small */
260 if (EFSYS_MEM_SIZE(esmp) <
261 (encp->enc_mac_stats_nstats * sizeof (efx_qword_t))) {
262 /* DMA buffer too small */
267 /* Read END first so we don't race with the MC */
268 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
269 SIENA_MAC_STAT_READ(esmp, (encp->enc_mac_stats_nstats - 1),
271 EFSYS_MEM_READ_BARRIER();
274 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PKTS, &value);
275 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);
276 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_CONTROL_PKTS, &value);
277 EFSYS_STAT_SUBR_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);
279 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PAUSE_PKTS, &value);
280 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PAUSE_PKTS]), &value);
282 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_UNICAST_PKTS, &value);
283 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_UNICST_PKTS]), &value);
285 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTICAST_PKTS, &value);
286 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULTICST_PKTS]), &value);
288 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BROADCAST_PKTS, &value);
289 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_BRDCST_PKTS]), &value);
291 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BYTES, &value);
292 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_OCTETS]), &value);
294 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LT64_PKTS, &value);
295 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);
296 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_64_PKTS, &value);
297 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);
299 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_65_TO_127_PKTS, &value);
300 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_65_TO_127_PKTS]), &value);
302 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_128_TO_255_PKTS, &value);
303 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_128_TO_255_PKTS]), &value);
305 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_256_TO_511_PKTS, &value);
306 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_256_TO_511_PKTS]), &value);
308 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_512_TO_1023_PKTS, &value);
309 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_512_TO_1023_PKTS]), &value);
311 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_1024_TO_15XX_PKTS, &value);
312 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_1024_TO_15XX_PKTS]), &value);
314 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS, &value);
315 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);
316 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_GTJUMBO_PKTS, &value);
317 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);
319 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BAD_FCS_PKTS, &value);
320 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_ERRORS]), &value);
322 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS, &value);
323 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_SGL_COL_PKTS]), &value);
325 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS,
327 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULT_COL_PKTS]), &value);
329 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS,
331 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_COL_PKTS]), &value);
333 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LATE_COLLISION_PKTS, &value);
334 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LATE_COL_PKTS]), &value);
336 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_DEFERRED_PKTS, &value);
337 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_DEF_PKTS]), &value);
339 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS,
341 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_DEF_PKTS]), &value);
344 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BYTES, &value);
345 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_OCTETS]), &value);
347 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PKTS, &value);
348 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PKTS]), &value);
350 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNICAST_PKTS, &value);
351 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_UNICST_PKTS]), &value);
353 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MULTICAST_PKTS, &value);
354 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MULTICST_PKTS]), &value);
356 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BROADCAST_PKTS, &value);
357 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_BRDCST_PKTS]), &value);
359 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PAUSE_PKTS, &value);
360 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PAUSE_PKTS]), &value);
362 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNDERSIZE_PKTS, &value);
363 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);
364 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_64_PKTS, &value);
365 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);
367 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_65_TO_127_PKTS, &value);
368 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_65_TO_127_PKTS]), &value);
370 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_128_TO_255_PKTS, &value);
371 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_128_TO_255_PKTS]), &value);
373 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_256_TO_511_PKTS, &value);
374 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_256_TO_511_PKTS]), &value);
376 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_512_TO_1023_PKTS, &value);
377 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_512_TO_1023_PKTS]), &value);
379 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_1024_TO_15XX_PKTS, &value);
380 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_1024_TO_15XX_PKTS]), &value);
382 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS, &value);
383 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);
384 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_GTJUMBO_PKTS, &value);
385 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);
387 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BAD_FCS_PKTS, &value);
388 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FCS_ERRORS]), &value);
390 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_OVERFLOW_PKTS, &value);
391 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_DROP_EVENTS]), &value);
393 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_FALSE_CARRIER_PKTS, &value);
394 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FALSE_CARRIER_ERRORS]), &value);
396 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS, &value);
397 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_SYMBOL_ERRORS]), &value);
399 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_ALIGN_ERROR_PKTS, &value);
400 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_ALIGN_ERRORS]), &value);
402 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS, &value);
403 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_INTERNAL_ERRORS]), &value);
405 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_JABBER_PKTS, &value);
406 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_JABBER_PKTS]), &value);
408 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_CHAR_ERR, &value);
409 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_CHAR_ERR]),
410 &(value.eq_dword[0]));
411 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_CHAR_ERR]),
412 &(value.eq_dword[1]));
414 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_CHAR_ERR, &value);
415 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_CHAR_ERR]),
416 &(value.eq_dword[0]));
417 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_CHAR_ERR]),
418 &(value.eq_dword[1]));
420 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_DISP_ERR, &value);
421 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_DISP_ERR]),
422 &(value.eq_dword[0]));
423 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_DISP_ERR]),
424 &(value.eq_dword[1]));
426 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_DISP_ERR, &value);
427 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_DISP_ERR]),
428 &(value.eq_dword[0]));
429 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_DISP_ERR]),
430 &(value.eq_dword[1]));
432 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MATCH_FAULT, &value);
433 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MATCH_FAULT]), &value);
435 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_NODESC_DROPS, &value);
436 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_NODESC_DROP_CNT]), &value);
438 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
439 EFSYS_MEM_READ_BARRIER();
440 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_START,
443 /* Check that we didn't read the stats in the middle of a DMA */
444 /* Not a good enough check ? */
445 if (memcmp(&generation_start, &generation_end,
446 sizeof (generation_start)))
450 *generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0);
457 EFSYS_PROBE1(fail1, efx_rc_t, rc);
462 #endif /* EFSYS_OPT_MAC_STATS */
464 __checkReturn efx_rc_t
472 #endif /* EFSYS_OPT_SIENA */