1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2009-2018 Solarflare Communications Inc.
12 __checkReturn efx_rc_t
15 __out efx_link_mode_t *link_modep)
17 efx_port_t *epp = &(enp->en_port);
18 siena_link_state_t sls;
21 if ((rc = siena_phy_get_link(enp, &sls)) != 0)
24 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask;
25 epp->ep_fcntl = sls.sls_fcntl;
27 *link_modep = sls.sls_link_mode;
32 EFSYS_PROBE1(fail1, efx_rc_t, rc);
34 *link_modep = EFX_LINK_UNKNOWN;
39 __checkReturn efx_rc_t
42 __out boolean_t *mac_upp)
44 siena_link_state_t sls;
48 * Because Siena doesn't *require* polling, we can't rely on
49 * siena_mac_poll() being executed to populate epp->ep_mac_up.
51 if ((rc = siena_phy_get_link(enp, &sls)) != 0)
54 *mac_upp = sls.sls_mac_up;
59 EFSYS_PROBE1(fail1, efx_rc_t, rc);
64 __checkReturn efx_rc_t
65 siena_mac_reconfigure(
68 efx_port_t *epp = &(enp->en_port);
69 efx_oword_t multicast_hash[2];
71 uint8_t payload[MAX(MAX(MC_CMD_SET_MAC_IN_LEN,
72 MC_CMD_SET_MAC_OUT_LEN),
73 MAX(MC_CMD_SET_MCAST_HASH_IN_LEN,
74 MC_CMD_SET_MCAST_HASH_OUT_LEN))];
78 (void) memset(payload, 0, sizeof (payload));
79 req.emr_cmd = MC_CMD_SET_MAC;
80 req.emr_in_buf = payload;
81 req.emr_in_length = MC_CMD_SET_MAC_IN_LEN;
82 req.emr_out_buf = payload;
83 req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN;
85 MCDI_IN_SET_DWORD(req, SET_MAC_IN_MTU, epp->ep_mac_pdu);
86 MCDI_IN_SET_DWORD(req, SET_MAC_IN_DRAIN, epp->ep_mac_drain ? 1 : 0);
87 EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, SET_MAC_IN_ADDR),
89 MCDI_IN_POPULATE_DWORD_2(req, SET_MAC_IN_REJECT,
90 SET_MAC_IN_REJECT_UNCST, !epp->ep_all_unicst,
91 SET_MAC_IN_REJECT_BRDCST, !epp->ep_brdcst);
93 if (epp->ep_fcntl_autoneg)
94 /* efx_fcntl_set() has already set the phy capabilities */
95 fcntl = MC_CMD_FCNTL_AUTO;
96 else if (epp->ep_fcntl & EFX_FCNTL_RESPOND)
97 fcntl = (epp->ep_fcntl & EFX_FCNTL_GENERATE)
99 : MC_CMD_FCNTL_RESPOND;
101 fcntl = MC_CMD_FCNTL_OFF;
103 MCDI_IN_SET_DWORD(req, SET_MAC_IN_FCNTL, fcntl);
105 efx_mcdi_execute(enp, &req);
107 if (req.emr_rc != 0) {
112 /* Push multicast hash */
114 if (epp->ep_all_mulcst) {
115 /* A hash matching all multicast is all 1s */
116 EFX_SET_OWORD(multicast_hash[0]);
117 EFX_SET_OWORD(multicast_hash[1]);
118 } else if (epp->ep_mulcst) {
119 /* Use the hash set by the multicast list */
120 multicast_hash[0] = epp->ep_multicst_hash[0];
121 multicast_hash[1] = epp->ep_multicst_hash[1];
123 /* A hash matching no traffic is simply 0 */
124 EFX_ZERO_OWORD(multicast_hash[0]);
125 EFX_ZERO_OWORD(multicast_hash[1]);
129 * Broadcast packets go through the multicast hash filter.
130 * The IEEE 802.3 CRC32 of the broadcast address is 0xbe2612ff
131 * so we always add bit 0xff to the mask (bit 0x7f in the
134 if (epp->ep_brdcst) {
136 * NOTE: due to constant folding, some of this evaluates
137 * to null expressions, giving E_EXPR_NULL_EFFECT during
138 * lint on Illumos. No good way to fix this without
139 * explicit coding the individual word/bit setting.
140 * So just suppress lint for this one line.
143 EFX_SET_OWORD_BIT(multicast_hash[1], 0x7f);
146 (void) memset(payload, 0, sizeof (payload));
147 req.emr_cmd = MC_CMD_SET_MCAST_HASH;
148 req.emr_in_buf = payload;
149 req.emr_in_length = MC_CMD_SET_MCAST_HASH_IN_LEN;
150 req.emr_out_buf = payload;
151 req.emr_out_length = MC_CMD_SET_MCAST_HASH_OUT_LEN;
153 memcpy(MCDI_IN2(req, uint8_t, SET_MCAST_HASH_IN_HASH0),
154 multicast_hash, sizeof (multicast_hash));
156 efx_mcdi_execute(enp, &req);
158 if (req.emr_rc != 0) {
168 EFSYS_PROBE1(fail1, efx_rc_t, rc);
173 #if EFSYS_OPT_LOOPBACK
175 __checkReturn efx_rc_t
176 siena_mac_loopback_set(
178 __in efx_link_mode_t link_mode,
179 __in efx_loopback_type_t loopback_type)
181 efx_port_t *epp = &(enp->en_port);
182 const efx_phy_ops_t *epop = epp->ep_epop;
183 efx_loopback_type_t old_loopback_type;
184 efx_link_mode_t old_loopback_link_mode;
187 /* The PHY object handles this on Siena */
188 old_loopback_type = epp->ep_loopback_type;
189 old_loopback_link_mode = epp->ep_loopback_link_mode;
190 epp->ep_loopback_type = loopback_type;
191 epp->ep_loopback_link_mode = link_mode;
193 if ((rc = epop->epo_reconfigure(enp)) != 0)
199 EFSYS_PROBE1(fail1, efx_rc_t, rc);
201 epp->ep_loopback_type = old_loopback_type;
202 epp->ep_loopback_link_mode = old_loopback_link_mode;
207 #endif /* EFSYS_OPT_LOOPBACK */
209 #if EFSYS_OPT_MAC_STATS
211 __checkReturn efx_rc_t
212 siena_mac_stats_get_mask(
214 __inout_bcount(mask_size) uint32_t *maskp,
215 __in size_t mask_size)
217 const struct efx_mac_stats_range siena_stats[] = {
218 { EFX_MAC_RX_OCTETS, EFX_MAC_RX_GE_15XX_PKTS },
219 /* EFX_MAC_RX_ERRORS is not supported */
220 { EFX_MAC_RX_FCS_ERRORS, EFX_MAC_TX_EX_DEF_PKTS },
224 _NOTE(ARGUNUSED(enp))
226 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
227 siena_stats, EFX_ARRAY_SIZE(siena_stats))) != 0)
233 EFSYS_PROBE1(fail1, efx_rc_t, rc);
238 #define SIENA_MAC_STAT_READ(_esmp, _field, _eqp) \
239 EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp)
241 __checkReturn efx_rc_t
242 siena_mac_stats_update(
244 __in efsys_mem_t *esmp,
245 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
246 __inout_opt uint32_t *generationp)
248 const efx_nic_cfg_t *encp = &enp->en_nic_cfg;
249 efx_qword_t generation_start;
250 efx_qword_t generation_end;
254 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS) {
255 /* MAC stats count too small */
259 if (EFSYS_MEM_SIZE(esmp) <
260 (encp->enc_mac_stats_nstats * sizeof (efx_qword_t))) {
261 /* DMA buffer too small */
266 /* Read END first so we don't race with the MC */
267 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
268 SIENA_MAC_STAT_READ(esmp, (encp->enc_mac_stats_nstats - 1),
270 EFSYS_MEM_READ_BARRIER();
273 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PKTS, &value);
274 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);
275 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_CONTROL_PKTS, &value);
276 EFSYS_STAT_SUBR_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);
278 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PAUSE_PKTS, &value);
279 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PAUSE_PKTS]), &value);
281 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_UNICAST_PKTS, &value);
282 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_UNICST_PKTS]), &value);
284 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTICAST_PKTS, &value);
285 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULTICST_PKTS]), &value);
287 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BROADCAST_PKTS, &value);
288 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_BRDCST_PKTS]), &value);
290 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BYTES, &value);
291 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_OCTETS]), &value);
293 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LT64_PKTS, &value);
294 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);
295 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_64_PKTS, &value);
296 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);
298 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_65_TO_127_PKTS, &value);
299 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_65_TO_127_PKTS]), &value);
301 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_128_TO_255_PKTS, &value);
302 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_128_TO_255_PKTS]), &value);
304 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_256_TO_511_PKTS, &value);
305 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_256_TO_511_PKTS]), &value);
307 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_512_TO_1023_PKTS, &value);
308 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_512_TO_1023_PKTS]), &value);
310 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_1024_TO_15XX_PKTS, &value);
311 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_1024_TO_15XX_PKTS]), &value);
313 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS, &value);
314 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);
315 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_GTJUMBO_PKTS, &value);
316 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);
318 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BAD_FCS_PKTS, &value);
319 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_ERRORS]), &value);
321 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS, &value);
322 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_SGL_COL_PKTS]), &value);
324 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS,
326 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULT_COL_PKTS]), &value);
328 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS,
330 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_COL_PKTS]), &value);
332 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LATE_COLLISION_PKTS, &value);
333 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LATE_COL_PKTS]), &value);
335 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_DEFERRED_PKTS, &value);
336 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_DEF_PKTS]), &value);
338 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS,
340 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_DEF_PKTS]), &value);
343 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BYTES, &value);
344 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_OCTETS]), &value);
346 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PKTS, &value);
347 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PKTS]), &value);
349 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNICAST_PKTS, &value);
350 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_UNICST_PKTS]), &value);
352 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MULTICAST_PKTS, &value);
353 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MULTICST_PKTS]), &value);
355 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BROADCAST_PKTS, &value);
356 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_BRDCST_PKTS]), &value);
358 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PAUSE_PKTS, &value);
359 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PAUSE_PKTS]), &value);
361 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNDERSIZE_PKTS, &value);
362 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);
363 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_64_PKTS, &value);
364 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);
366 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_65_TO_127_PKTS, &value);
367 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_65_TO_127_PKTS]), &value);
369 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_128_TO_255_PKTS, &value);
370 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_128_TO_255_PKTS]), &value);
372 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_256_TO_511_PKTS, &value);
373 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_256_TO_511_PKTS]), &value);
375 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_512_TO_1023_PKTS, &value);
376 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_512_TO_1023_PKTS]), &value);
378 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_1024_TO_15XX_PKTS, &value);
379 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_1024_TO_15XX_PKTS]), &value);
381 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS, &value);
382 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);
383 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_GTJUMBO_PKTS, &value);
384 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);
386 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BAD_FCS_PKTS, &value);
387 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FCS_ERRORS]), &value);
389 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_OVERFLOW_PKTS, &value);
390 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_DROP_EVENTS]), &value);
392 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_FALSE_CARRIER_PKTS, &value);
393 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FALSE_CARRIER_ERRORS]), &value);
395 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS, &value);
396 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_SYMBOL_ERRORS]), &value);
398 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_ALIGN_ERROR_PKTS, &value);
399 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_ALIGN_ERRORS]), &value);
401 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS, &value);
402 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_INTERNAL_ERRORS]), &value);
404 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_JABBER_PKTS, &value);
405 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_JABBER_PKTS]), &value);
407 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_CHAR_ERR, &value);
408 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_CHAR_ERR]),
409 &(value.eq_dword[0]));
410 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_CHAR_ERR]),
411 &(value.eq_dword[1]));
413 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_CHAR_ERR, &value);
414 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_CHAR_ERR]),
415 &(value.eq_dword[0]));
416 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_CHAR_ERR]),
417 &(value.eq_dword[1]));
419 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_DISP_ERR, &value);
420 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_DISP_ERR]),
421 &(value.eq_dword[0]));
422 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_DISP_ERR]),
423 &(value.eq_dword[1]));
425 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_DISP_ERR, &value);
426 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_DISP_ERR]),
427 &(value.eq_dword[0]));
428 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_DISP_ERR]),
429 &(value.eq_dword[1]));
431 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MATCH_FAULT, &value);
432 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MATCH_FAULT]), &value);
434 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_NODESC_DROPS, &value);
435 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_NODESC_DROP_CNT]), &value);
437 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
438 EFSYS_MEM_READ_BARRIER();
439 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_START,
442 /* Check that we didn't read the stats in the middle of a DMA */
443 /* Not a good enough check ? */
444 if (memcmp(&generation_start, &generation_end,
445 sizeof (generation_start)))
449 *generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0);
456 EFSYS_PROBE1(fail1, efx_rc_t, rc);
461 #endif /* EFSYS_OPT_MAC_STATS */
463 __checkReturn efx_rc_t
471 #endif /* EFSYS_OPT_SIENA */