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37 static __checkReturn efx_rc_t
41 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
43 efx_dword_t capabilities;
45 uint32_t nevq, nrxq, ntxq;
48 /* External port identifier using one-based port numbering */
49 encp->enc_external_port = (uint8_t)enp->en_mcdi.em_emip.emi_port;
51 /* Board configuration */
52 if ((rc = efx_mcdi_get_board_cfg(enp, &board_type,
53 &capabilities, mac_addr)) != 0)
56 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
58 encp->enc_board_type = board_type;
61 * There is no possibility to determine the number of PFs on Siena
62 * by issuing MCDI request, and it is not an easy task to find the
63 * value based on the board type, so 'enc_hw_pf_count' is set to 1
65 encp->enc_hw_pf_count = 1;
67 /* Additional capabilities */
68 encp->enc_clk_mult = 1;
69 if (EFX_DWORD_FIELD(capabilities, MC_CMD_CAPABILITIES_TURBO)) {
70 enp->en_features |= EFX_FEATURE_TURBO;
72 if (EFX_DWORD_FIELD(capabilities,
73 MC_CMD_CAPABILITIES_TURBO_ACTIVE)) {
74 encp->enc_clk_mult = 2;
78 encp->enc_evq_timer_quantum_ns =
79 EFX_EVQ_SIENA_TIMER_QUANTUM_NS / encp->enc_clk_mult;
80 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
81 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
83 /* When hash header insertion is enabled, Siena inserts 16 bytes */
84 encp->enc_rx_prefix_size = 16;
86 /* Alignment for receive packet DMA buffers */
87 encp->enc_rx_buf_align_start = 1;
88 encp->enc_rx_buf_align_end = 1;
90 /* Alignment for WPTR updates */
91 encp->enc_rx_push_align = 1;
94 rc = efx_mcdi_get_resource_limits(enp, &nevq, &nrxq, &ntxq);
100 nrxq = EFX_RXQ_LIMIT_TARGET;
101 ntxq = EFX_TXQ_LIMIT_TARGET;
103 encp->enc_evq_limit = nevq;
104 encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
105 encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
107 encp->enc_txq_max_ndescs = 4096;
109 encp->enc_buftbl_limit = SIENA_SRAM_ROWS -
110 (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) -
111 (encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
113 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
114 encp->enc_fw_assisted_tso_enabled = B_FALSE;
115 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
116 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
117 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
118 encp->enc_rx_packed_stream_supported = B_FALSE;
119 encp->enc_rx_var_packed_stream_supported = B_FALSE;
121 /* Siena supports two 10G ports, and 8 lanes of PCIe Gen2 */
122 encp->enc_required_pcie_bandwidth_mbps = 2 * 10000;
123 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN2;
125 encp->enc_fw_verified_nvram_update_required = B_FALSE;
132 EFSYS_PROBE1(fail1, efx_rc_t, rc);
137 static __checkReturn efx_rc_t
141 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
144 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
145 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
151 EFSYS_PROBE1(fail1, efx_rc_t, rc);
156 __checkReturn efx_rc_t
160 efx_port_t *epp = &(enp->en_port);
161 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
162 siena_link_state_t sls;
167 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
170 if ((rc = efx_nic_biu_test(enp)) != 0)
173 /* Clear the region register */
174 EFX_POPULATE_OWORD_4(oword,
175 FRF_AZ_ADR_REGION0, 0,
176 FRF_AZ_ADR_REGION1, (1 << 16),
177 FRF_AZ_ADR_REGION2, (2 << 16),
178 FRF_AZ_ADR_REGION3, (3 << 16));
179 EFX_BAR_WRITEO(enp, FR_AZ_ADR_REGION_REG, &oword);
181 /* Read clear any assertion state */
182 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
185 /* Exit the assertion handler */
186 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
189 /* Wrestle control from the BMC */
190 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
193 if ((rc = siena_board_cfg(enp)) != 0)
196 if ((rc = siena_phy_cfg(enp)) != 0)
199 /* Obtain the default PHY advertised capabilities */
200 if ((rc = siena_nic_reset(enp)) != 0)
202 if ((rc = siena_phy_get_link(enp, &sls)) != 0)
204 epp->ep_default_adv_cap_mask = sls.sls_adv_cap_mask;
205 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask;
207 encp->enc_features = enp->en_features;
226 EFSYS_PROBE1(fail1, efx_rc_t, rc);
231 __checkReturn efx_rc_t
238 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
240 /* siena_nic_reset() is called to recover from BADASSERT failures. */
241 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
243 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
247 * Bug24908: ENTITY_RESET_IN_LEN is non zero but zero may be supplied
248 * for backwards compatibility with PORT_RESET_IN_LEN.
250 EFX_STATIC_ASSERT(MC_CMD_ENTITY_RESET_OUT_LEN == 0);
252 req.emr_cmd = MC_CMD_ENTITY_RESET;
253 req.emr_in_buf = NULL;
254 req.emr_in_length = 0;
255 req.emr_out_buf = NULL;
256 req.emr_out_length = 0;
258 efx_mcdi_execute(enp, &req);
260 if (req.emr_rc != 0) {
272 EFSYS_PROBE1(fail1, efx_rc_t, rc);
284 * RX_INGR_EN is always enabled on Siena, because we rely on
285 * the RX parser to be resiliant to missing SOP/EOP.
287 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
288 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_INGR_EN, 1);
289 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
291 /* Disable parsing of additional 802.1Q in Q packets */
292 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
293 EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES, 0);
294 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
303 EFX_POPULATE_OWORD_1(oword, FRF_CZ_USREV_DIS, 1);
304 EFX_BAR_WRITEO(enp, FR_CZ_USR_EV_CFG, &oword);
307 __checkReturn efx_rc_t
313 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
315 /* Enable reporting of some events (e.g. link change) */
316 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
319 siena_sram_init(enp);
321 /* Configure Siena's RX block */
322 siena_nic_rx_cfg(enp);
324 /* Disable USR_EVents for now */
325 siena_nic_usrev_dis(enp);
327 /* bug17057: Ensure set_link is called */
328 if ((rc = siena_phy_reconfigure(enp)) != 0)
331 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V1;
338 EFSYS_PROBE1(fail1, efx_rc_t, rc);
347 _NOTE(ARGUNUSED(enp))
354 (void) efx_mcdi_drv_attach(enp, B_FALSE);
357 #endif /* EFSYS_OPT_SIENA */