2 * Copyright (c) 2009-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
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14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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37 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
39 static __checkReturn efx_rc_t
40 siena_nic_get_partn_mask(
42 __out unsigned int *maskp)
45 uint8_t payload[MAX(MC_CMD_NVRAM_TYPES_IN_LEN,
46 MC_CMD_NVRAM_TYPES_OUT_LEN)];
49 (void) memset(payload, 0, sizeof (payload));
50 req.emr_cmd = MC_CMD_NVRAM_TYPES;
51 req.emr_in_buf = payload;
52 req.emr_in_length = MC_CMD_NVRAM_TYPES_IN_LEN;
53 req.emr_out_buf = payload;
54 req.emr_out_length = MC_CMD_NVRAM_TYPES_OUT_LEN;
56 efx_mcdi_execute(enp, &req);
58 if (req.emr_rc != 0) {
63 if (req.emr_out_length_used < MC_CMD_NVRAM_TYPES_OUT_LEN) {
68 *maskp = MCDI_OUT_DWORD(req, NVRAM_TYPES_OUT_TYPES);
75 EFSYS_PROBE1(fail1, efx_rc_t, rc);
80 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
82 static __checkReturn efx_rc_t
86 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
88 efx_dword_t capabilities;
90 uint32_t nevq, nrxq, ntxq;
93 /* External port identifier using one-based port numbering */
94 encp->enc_external_port = (uint8_t)enp->en_mcdi.em_emip.emi_port;
96 /* Board configuration */
97 if ((rc = efx_mcdi_get_board_cfg(enp, &board_type,
98 &capabilities, mac_addr)) != 0)
101 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
103 encp->enc_board_type = board_type;
106 * There is no possibility to determine the number of PFs on Siena
107 * by issuing MCDI request, and it is not an easy task to find the
108 * value based on the board type, so 'enc_hw_pf_count' is set to 1
110 encp->enc_hw_pf_count = 1;
112 /* Additional capabilities */
113 encp->enc_clk_mult = 1;
114 if (EFX_DWORD_FIELD(capabilities, MC_CMD_CAPABILITIES_TURBO)) {
115 enp->en_features |= EFX_FEATURE_TURBO;
117 if (EFX_DWORD_FIELD(capabilities,
118 MC_CMD_CAPABILITIES_TURBO_ACTIVE)) {
119 encp->enc_clk_mult = 2;
123 encp->enc_evq_timer_quantum_ns =
124 EFX_EVQ_SIENA_TIMER_QUANTUM_NS / encp->enc_clk_mult;
125 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
126 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
128 /* When hash header insertion is enabled, Siena inserts 16 bytes */
129 encp->enc_rx_prefix_size = 16;
131 /* Alignment for receive packet DMA buffers */
132 encp->enc_rx_buf_align_start = 1;
133 encp->enc_rx_buf_align_end = 1;
135 /* Alignment for WPTR updates */
136 encp->enc_rx_push_align = 1;
138 /* There is one RSS context per function */
139 encp->enc_rx_scale_max_exclusive_contexts = 1;
141 encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);
142 /* Fragments must not span 4k boundaries. */
143 encp->enc_tx_dma_desc_boundary = 4096;
145 /* Resource limits */
146 rc = efx_mcdi_get_resource_limits(enp, &nevq, &nrxq, &ntxq);
152 nrxq = EFX_RXQ_LIMIT_TARGET;
153 ntxq = EFX_TXQ_LIMIT_TARGET;
155 encp->enc_evq_limit = nevq;
156 encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
157 encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
159 encp->enc_txq_max_ndescs = 4096;
161 encp->enc_buftbl_limit = SIENA_SRAM_ROWS -
162 (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) -
163 (encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
165 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
166 encp->enc_fw_assisted_tso_enabled = B_FALSE;
167 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
168 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
169 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
170 encp->enc_rx_packed_stream_supported = B_FALSE;
171 encp->enc_rx_var_packed_stream_supported = B_FALSE;
173 /* Siena supports two 10G ports, and 8 lanes of PCIe Gen2 */
174 encp->enc_required_pcie_bandwidth_mbps = 2 * 10000;
175 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN2;
177 encp->enc_nvram_update_verify_result_supported = B_FALSE;
184 EFSYS_PROBE1(fail1, efx_rc_t, rc);
189 static __checkReturn efx_rc_t
193 #if EFSYS_OPT_PHY_STATS
194 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
195 #endif /* EFSYS_OPT_PHY_STATS */
198 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
199 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
202 #if EFSYS_OPT_PHY_STATS
203 /* Convert the MCDI statistic mask into the EFX_PHY_STAT mask */
204 siena_phy_decode_stats(enp, encp->enc_mcdi_phy_stat_mask,
205 NULL, &encp->enc_phy_stat_mask, NULL);
206 #endif /* EFSYS_OPT_PHY_STATS */
211 EFSYS_PROBE1(fail1, efx_rc_t, rc);
216 #define SIENA_BIU_MAGIC0 0x01234567
217 #define SIENA_BIU_MAGIC1 0xfedcba98
219 static __checkReturn efx_rc_t
227 * Write magic values to scratch registers 0 and 1, then
228 * verify that the values were written correctly. Interleave
229 * the accesses to ensure that the BIU is not just reading
230 * back the cached value that was last written.
232 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC0);
233 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
235 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC1);
236 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
238 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
239 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC0) {
244 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
245 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC1) {
251 * Perform the same test, with the values swapped. This
252 * ensures that subsequent tests don't start with the correct
253 * values already written into the scratch registers.
255 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC1);
256 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
258 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC0);
259 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
261 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
262 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC1) {
267 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
268 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC0) {
282 EFSYS_PROBE1(fail1, efx_rc_t, rc);
287 __checkReturn efx_rc_t
291 efx_port_t *epp = &(enp->en_port);
292 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
293 siena_link_state_t sls;
298 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
301 if ((rc = siena_nic_biu_test(enp)) != 0)
304 /* Clear the region register */
305 EFX_POPULATE_OWORD_4(oword,
306 FRF_AZ_ADR_REGION0, 0,
307 FRF_AZ_ADR_REGION1, (1 << 16),
308 FRF_AZ_ADR_REGION2, (2 << 16),
309 FRF_AZ_ADR_REGION3, (3 << 16));
310 EFX_BAR_WRITEO(enp, FR_AZ_ADR_REGION_REG, &oword);
312 /* Read clear any assertion state */
313 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
316 /* Exit the assertion handler */
317 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
320 /* Wrestle control from the BMC */
321 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
324 if ((rc = siena_board_cfg(enp)) != 0)
327 if ((rc = siena_phy_cfg(enp)) != 0)
330 /* Obtain the default PHY advertised capabilities */
331 if ((rc = siena_nic_reset(enp)) != 0)
333 if ((rc = siena_phy_get_link(enp, &sls)) != 0)
335 epp->ep_default_adv_cap_mask = sls.sls_adv_cap_mask;
336 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask;
338 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
339 if ((rc = siena_nic_get_partn_mask(enp, &mask)) != 0)
341 enp->en_u.siena.enu_partn_mask = mask;
344 #if EFSYS_OPT_MAC_STATS
345 /* Wipe the MAC statistics */
346 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
350 #if EFSYS_OPT_LOOPBACK
351 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
355 #if EFSYS_OPT_MON_STATS
356 if ((rc = mcdi_mon_cfg_build(enp)) != 0)
360 encp->enc_features = enp->en_features;
364 #if EFSYS_OPT_MON_STATS
368 #if EFSYS_OPT_LOOPBACK
372 #if EFSYS_OPT_MAC_STATS
376 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
395 EFSYS_PROBE1(fail1, efx_rc_t, rc);
400 __checkReturn efx_rc_t
407 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
409 /* siena_nic_reset() is called to recover from BADASSERT failures. */
410 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
412 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
416 * Bug24908: ENTITY_RESET_IN_LEN is non zero but zero may be supplied
417 * for backwards compatibility with PORT_RESET_IN_LEN.
419 EFX_STATIC_ASSERT(MC_CMD_ENTITY_RESET_OUT_LEN == 0);
421 req.emr_cmd = MC_CMD_ENTITY_RESET;
422 req.emr_in_buf = NULL;
423 req.emr_in_length = 0;
424 req.emr_out_buf = NULL;
425 req.emr_out_length = 0;
427 efx_mcdi_execute(enp, &req);
429 if (req.emr_rc != 0) {
441 EFSYS_PROBE1(fail1, efx_rc_t, rc);
453 * RX_INGR_EN is always enabled on Siena, because we rely on
454 * the RX parser to be resiliant to missing SOP/EOP.
456 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
457 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_INGR_EN, 1);
458 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
460 /* Disable parsing of additional 802.1Q in Q packets */
461 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
462 EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES, 0);
463 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
472 EFX_POPULATE_OWORD_1(oword, FRF_CZ_USREV_DIS, 1);
473 EFX_BAR_WRITEO(enp, FR_CZ_USR_EV_CFG, &oword);
476 __checkReturn efx_rc_t
482 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
484 /* Enable reporting of some events (e.g. link change) */
485 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
488 siena_sram_init(enp);
490 /* Configure Siena's RX block */
491 siena_nic_rx_cfg(enp);
493 /* Disable USR_EVents for now */
494 siena_nic_usrev_dis(enp);
496 /* bug17057: Ensure set_link is called */
497 if ((rc = siena_phy_reconfigure(enp)) != 0)
500 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V1;
507 EFSYS_PROBE1(fail1, efx_rc_t, rc);
516 _NOTE(ARGUNUSED(enp))
523 #if EFSYS_OPT_MON_STATS
524 mcdi_mon_cfg_free(enp);
525 #endif /* EFSYS_OPT_MON_STATS */
526 (void) efx_mcdi_drv_attach(enp, B_FALSE);
531 static siena_register_set_t __siena_registers[] = {
532 { FR_AZ_ADR_REGION_REG_OFST, 0, 1 },
533 { FR_CZ_USR_EV_CFG_OFST, 0, 1 },
534 { FR_AZ_RX_CFG_REG_OFST, 0, 1 },
535 { FR_AZ_TX_CFG_REG_OFST, 0, 1 },
536 { FR_AZ_TX_RESERVED_REG_OFST, 0, 1 },
537 { FR_AZ_SRM_TX_DC_CFG_REG_OFST, 0, 1 },
538 { FR_AZ_RX_DC_CFG_REG_OFST, 0, 1 },
539 { FR_AZ_RX_DC_PF_WM_REG_OFST, 0, 1 },
540 { FR_AZ_DP_CTRL_REG_OFST, 0, 1 },
541 { FR_BZ_RX_RSS_TKEY_REG_OFST, 0, 1},
542 { FR_CZ_RX_RSS_IPV6_REG1_OFST, 0, 1},
543 { FR_CZ_RX_RSS_IPV6_REG2_OFST, 0, 1},
544 { FR_CZ_RX_RSS_IPV6_REG3_OFST, 0, 1}
547 static const uint32_t __siena_register_masks[] = {
548 0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF,
549 0x000103FF, 0x00000000, 0x00000000, 0x00000000,
550 0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000,
551 0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF,
552 0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF,
553 0x001FFFFF, 0x00000000, 0x00000000, 0x00000000,
554 0x00000003, 0x00000000, 0x00000000, 0x00000000,
555 0x000003FF, 0x00000000, 0x00000000, 0x00000000,
556 0x00000FFF, 0x00000000, 0x00000000, 0x00000000,
557 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
558 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
559 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
560 0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000
563 static siena_register_set_t __siena_tables[] = {
564 { FR_AZ_RX_FILTER_TBL0_OFST, FR_AZ_RX_FILTER_TBL0_STEP,
565 FR_AZ_RX_FILTER_TBL0_ROWS },
566 { FR_CZ_RX_MAC_FILTER_TBL0_OFST, FR_CZ_RX_MAC_FILTER_TBL0_STEP,
567 FR_CZ_RX_MAC_FILTER_TBL0_ROWS },
568 { FR_AZ_RX_DESC_PTR_TBL_OFST,
569 FR_AZ_RX_DESC_PTR_TBL_STEP, FR_CZ_RX_DESC_PTR_TBL_ROWS },
570 { FR_AZ_TX_DESC_PTR_TBL_OFST,
571 FR_AZ_TX_DESC_PTR_TBL_STEP, FR_CZ_TX_DESC_PTR_TBL_ROWS },
572 { FR_AZ_TIMER_TBL_OFST, FR_AZ_TIMER_TBL_STEP, FR_CZ_TIMER_TBL_ROWS },
573 { FR_CZ_TX_FILTER_TBL0_OFST,
574 FR_CZ_TX_FILTER_TBL0_STEP, FR_CZ_TX_FILTER_TBL0_ROWS },
575 { FR_CZ_TX_MAC_FILTER_TBL0_OFST,
576 FR_CZ_TX_MAC_FILTER_TBL0_STEP, FR_CZ_TX_MAC_FILTER_TBL0_ROWS }
579 static const uint32_t __siena_table_masks[] = {
580 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000003FF,
581 0xFFFF0FFF, 0xFFFFFFFF, 0x00000E7F, 0x00000000,
582 0xFFFFFFFE, 0x0FFFFFFF, 0x01800000, 0x00000000,
583 0xFFFFFFFE, 0x0FFFFFFF, 0x0C000000, 0x00000000,
584 0x3FFFFFFF, 0x00000000, 0x00000000, 0x00000000,
585 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000013FF,
586 0xFFFF07FF, 0xFFFFFFFF, 0x0000007F, 0x00000000,
589 __checkReturn efx_rc_t
590 siena_nic_test_registers(
592 __in siena_register_set_t *rsp,
596 efx_oword_t original;
602 /* This function is only suitable for registers */
603 EFSYS_ASSERT(rsp->rows == 1);
605 /* bit sweep on and off */
606 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &original,
608 for (bit = 0; bit < 128; bit++) {
609 /* Is this bit in the mask? */
610 if (~(rsp->mask.eo_u32[bit >> 5]) & (1 << bit))
613 /* Test this bit can be set in isolation */
615 EFX_AND_OWORD(reg, rsp->mask);
616 EFX_SET_OWORD_BIT(reg, bit);
618 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
620 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
623 EFX_AND_OWORD(buf, rsp->mask);
624 if (memcmp(®, &buf, sizeof (reg))) {
629 /* Test this bit can be cleared in isolation */
630 EFX_OR_OWORD(reg, rsp->mask);
631 EFX_CLEAR_OWORD_BIT(reg, bit);
633 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
635 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
638 EFX_AND_OWORD(buf, rsp->mask);
639 if (memcmp(®, &buf, sizeof (reg))) {
645 /* Restore the old value */
646 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original,
658 EFSYS_PROBE1(fail1, efx_rc_t, rc);
660 /* Restore the old value */
661 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, B_TRUE);
666 __checkReturn efx_rc_t
667 siena_nic_test_tables(
669 __in siena_register_set_t *rsp,
670 __in efx_pattern_type_t pattern,
673 efx_sram_pattern_fn_t func;
675 unsigned int address;
680 EFSYS_ASSERT(pattern < EFX_PATTERN_NTYPES);
681 func = __efx_sram_pattern_fns[pattern];
685 address = rsp->address;
686 for (index = 0; index < rsp->rows; ++index) {
687 func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
688 func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
689 EFX_AND_OWORD(reg, rsp->mask);
690 EFSYS_BAR_WRITEO(enp->en_esbp, address, ®, B_TRUE);
692 address += rsp->step;
696 address = rsp->address;
697 for (index = 0; index < rsp->rows; ++index) {
698 func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
699 func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
700 EFX_AND_OWORD(reg, rsp->mask);
701 EFSYS_BAR_READO(enp->en_esbp, address, &buf, B_TRUE);
702 if (memcmp(®, &buf, sizeof (reg))) {
707 address += rsp->step;
717 EFSYS_PROBE1(fail1, efx_rc_t, rc);
723 __checkReturn efx_rc_t
724 siena_nic_register_test(
727 siena_register_set_t *rsp;
728 const uint32_t *dwordp;
733 /* Fill out the register mask entries */
734 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_register_masks)
735 == EFX_ARRAY_SIZE(__siena_registers) * 4);
737 nitems = EFX_ARRAY_SIZE(__siena_registers);
738 dwordp = __siena_register_masks;
739 for (count = 0; count < nitems; ++count) {
740 rsp = __siena_registers + count;
741 rsp->mask.eo_u32[0] = *dwordp++;
742 rsp->mask.eo_u32[1] = *dwordp++;
743 rsp->mask.eo_u32[2] = *dwordp++;
744 rsp->mask.eo_u32[3] = *dwordp++;
747 /* Fill out the register table entries */
748 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_table_masks)
749 == EFX_ARRAY_SIZE(__siena_tables) * 4);
751 nitems = EFX_ARRAY_SIZE(__siena_tables);
752 dwordp = __siena_table_masks;
753 for (count = 0; count < nitems; ++count) {
754 rsp = __siena_tables + count;
755 rsp->mask.eo_u32[0] = *dwordp++;
756 rsp->mask.eo_u32[1] = *dwordp++;
757 rsp->mask.eo_u32[2] = *dwordp++;
758 rsp->mask.eo_u32[3] = *dwordp++;
761 if ((rc = siena_nic_test_registers(enp, __siena_registers,
762 EFX_ARRAY_SIZE(__siena_registers))) != 0)
765 if ((rc = siena_nic_test_tables(enp, __siena_tables,
766 EFX_PATTERN_BYTE_ALTERNATE,
767 EFX_ARRAY_SIZE(__siena_tables))) != 0)
770 if ((rc = siena_nic_test_tables(enp, __siena_tables,
771 EFX_PATTERN_BYTE_CHANGING,
772 EFX_ARRAY_SIZE(__siena_tables))) != 0)
775 if ((rc = siena_nic_test_tables(enp, __siena_tables,
776 EFX_PATTERN_BIT_SWEEP, EFX_ARRAY_SIZE(__siena_tables))) != 0)
788 EFSYS_PROBE1(fail1, efx_rc_t, rc);
793 #endif /* EFSYS_OPT_DIAG */
795 #endif /* EFSYS_OPT_SIENA */