1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2009-2018 Solarflare Communications Inc.
13 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
15 static __checkReturn efx_rc_t
16 siena_nic_get_partn_mask(
18 __out unsigned int *maskp)
21 uint8_t payload[MAX(MC_CMD_NVRAM_TYPES_IN_LEN,
22 MC_CMD_NVRAM_TYPES_OUT_LEN)];
25 (void) memset(payload, 0, sizeof (payload));
26 req.emr_cmd = MC_CMD_NVRAM_TYPES;
27 req.emr_in_buf = payload;
28 req.emr_in_length = MC_CMD_NVRAM_TYPES_IN_LEN;
29 req.emr_out_buf = payload;
30 req.emr_out_length = MC_CMD_NVRAM_TYPES_OUT_LEN;
32 efx_mcdi_execute(enp, &req);
34 if (req.emr_rc != 0) {
39 if (req.emr_out_length_used < MC_CMD_NVRAM_TYPES_OUT_LEN) {
44 *maskp = MCDI_OUT_DWORD(req, NVRAM_TYPES_OUT_TYPES);
51 EFSYS_PROBE1(fail1, efx_rc_t, rc);
56 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
58 static __checkReturn efx_rc_t
62 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
64 efx_dword_t capabilities;
66 uint32_t nevq, nrxq, ntxq;
69 /* Siena has a fixed 8Kbyte VI window size */
70 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
71 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
73 /* External port identifier using one-based port numbering */
74 encp->enc_external_port = (uint8_t)enp->en_mcdi.em_emip.emi_port;
76 /* Board configuration */
77 if ((rc = efx_mcdi_get_board_cfg(enp, &board_type,
78 &capabilities, mac_addr)) != 0)
81 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
83 encp->enc_board_type = board_type;
86 * There is no possibility to determine the number of PFs on Siena
87 * by issuing MCDI request, and it is not an easy task to find the
88 * value based on the board type, so 'enc_hw_pf_count' is set to 1
90 encp->enc_hw_pf_count = 1;
92 /* Additional capabilities */
93 encp->enc_clk_mult = 1;
94 if (EFX_DWORD_FIELD(capabilities, MC_CMD_CAPABILITIES_TURBO)) {
95 enp->en_features |= EFX_FEATURE_TURBO;
97 if (EFX_DWORD_FIELD(capabilities,
98 MC_CMD_CAPABILITIES_TURBO_ACTIVE)) {
99 encp->enc_clk_mult = 2;
103 encp->enc_evq_timer_quantum_ns =
104 EFX_EVQ_SIENA_TIMER_QUANTUM_NS / encp->enc_clk_mult;
105 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
106 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
108 /* When hash header insertion is enabled, Siena inserts 16 bytes */
109 encp->enc_rx_prefix_size = 16;
111 /* Alignment for receive packet DMA buffers */
112 encp->enc_rx_buf_align_start = 1;
113 encp->enc_rx_buf_align_end = 1;
115 /* Alignment for WPTR updates */
116 encp->enc_rx_push_align = 1;
118 /* There is one RSS context per function */
119 encp->enc_rx_scale_max_exclusive_contexts = 1;
121 encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);
122 /* Fragments must not span 4k boundaries. */
123 encp->enc_tx_dma_desc_boundary = 4096;
125 /* Resource limits */
126 rc = efx_mcdi_get_resource_limits(enp, &nevq, &nrxq, &ntxq);
132 nrxq = EFX_RXQ_LIMIT_TARGET;
133 ntxq = EFX_TXQ_LIMIT_TARGET;
135 encp->enc_evq_limit = nevq;
136 encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
137 encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
139 encp->enc_txq_max_ndescs = 4096;
141 encp->enc_buftbl_limit = SIENA_SRAM_ROWS -
142 (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) -
143 (encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
145 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
146 encp->enc_fw_assisted_tso_enabled = B_FALSE;
147 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
148 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
149 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
150 encp->enc_rx_packed_stream_supported = B_FALSE;
151 encp->enc_rx_var_packed_stream_supported = B_FALSE;
153 /* Siena supports two 10G ports, and 8 lanes of PCIe Gen2 */
154 encp->enc_required_pcie_bandwidth_mbps = 2 * 10000;
155 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN2;
157 encp->enc_nvram_update_verify_result_supported = B_FALSE;
164 EFSYS_PROBE1(fail1, efx_rc_t, rc);
169 static __checkReturn efx_rc_t
173 #if EFSYS_OPT_PHY_STATS
174 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
175 #endif /* EFSYS_OPT_PHY_STATS */
178 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
179 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
182 #if EFSYS_OPT_PHY_STATS
183 /* Convert the MCDI statistic mask into the EFX_PHY_STAT mask */
184 siena_phy_decode_stats(enp, encp->enc_mcdi_phy_stat_mask,
185 NULL, &encp->enc_phy_stat_mask, NULL);
186 #endif /* EFSYS_OPT_PHY_STATS */
191 EFSYS_PROBE1(fail1, efx_rc_t, rc);
196 #define SIENA_BIU_MAGIC0 0x01234567
197 #define SIENA_BIU_MAGIC1 0xfedcba98
199 static __checkReturn efx_rc_t
207 * Write magic values to scratch registers 0 and 1, then
208 * verify that the values were written correctly. Interleave
209 * the accesses to ensure that the BIU is not just reading
210 * back the cached value that was last written.
212 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC0);
213 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
215 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC1);
216 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
218 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
219 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC0) {
224 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
225 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC1) {
231 * Perform the same test, with the values swapped. This
232 * ensures that subsequent tests don't start with the correct
233 * values already written into the scratch registers.
235 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC1);
236 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
238 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC0);
239 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
241 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
242 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC1) {
247 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
248 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC0) {
262 EFSYS_PROBE1(fail1, efx_rc_t, rc);
267 __checkReturn efx_rc_t
271 efx_port_t *epp = &(enp->en_port);
272 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
273 siena_link_state_t sls;
278 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
281 if ((rc = siena_nic_biu_test(enp)) != 0)
284 /* Clear the region register */
285 EFX_POPULATE_OWORD_4(oword,
286 FRF_AZ_ADR_REGION0, 0,
287 FRF_AZ_ADR_REGION1, (1 << 16),
288 FRF_AZ_ADR_REGION2, (2 << 16),
289 FRF_AZ_ADR_REGION3, (3 << 16));
290 EFX_BAR_WRITEO(enp, FR_AZ_ADR_REGION_REG, &oword);
292 /* Read clear any assertion state */
293 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
296 /* Exit the assertion handler */
297 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
300 /* Wrestle control from the BMC */
301 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
304 if ((rc = siena_board_cfg(enp)) != 0)
307 if ((rc = siena_phy_cfg(enp)) != 0)
310 /* Obtain the default PHY advertised capabilities */
311 if ((rc = siena_nic_reset(enp)) != 0)
313 if ((rc = siena_phy_get_link(enp, &sls)) != 0)
315 epp->ep_default_adv_cap_mask = sls.sls_adv_cap_mask;
316 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask;
318 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
319 if ((rc = siena_nic_get_partn_mask(enp, &mask)) != 0)
321 enp->en_u.siena.enu_partn_mask = mask;
324 #if EFSYS_OPT_MAC_STATS
325 /* Wipe the MAC statistics */
326 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
330 #if EFSYS_OPT_LOOPBACK
331 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
335 #if EFSYS_OPT_MON_STATS
336 if ((rc = mcdi_mon_cfg_build(enp)) != 0)
340 encp->enc_features = enp->en_features;
344 #if EFSYS_OPT_MON_STATS
348 #if EFSYS_OPT_LOOPBACK
352 #if EFSYS_OPT_MAC_STATS
356 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
375 EFSYS_PROBE1(fail1, efx_rc_t, rc);
380 __checkReturn efx_rc_t
387 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
389 /* siena_nic_reset() is called to recover from BADASSERT failures. */
390 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
392 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
396 * Bug24908: ENTITY_RESET_IN_LEN is non zero but zero may be supplied
397 * for backwards compatibility with PORT_RESET_IN_LEN.
399 EFX_STATIC_ASSERT(MC_CMD_ENTITY_RESET_OUT_LEN == 0);
401 req.emr_cmd = MC_CMD_ENTITY_RESET;
402 req.emr_in_buf = NULL;
403 req.emr_in_length = 0;
404 req.emr_out_buf = NULL;
405 req.emr_out_length = 0;
407 efx_mcdi_execute(enp, &req);
409 if (req.emr_rc != 0) {
421 EFSYS_PROBE1(fail1, efx_rc_t, rc);
433 * RX_INGR_EN is always enabled on Siena, because we rely on
434 * the RX parser to be resiliant to missing SOP/EOP.
436 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
437 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_INGR_EN, 1);
438 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
440 /* Disable parsing of additional 802.1Q in Q packets */
441 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
442 EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES, 0);
443 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
452 EFX_POPULATE_OWORD_1(oword, FRF_CZ_USREV_DIS, 1);
453 EFX_BAR_WRITEO(enp, FR_CZ_USR_EV_CFG, &oword);
456 __checkReturn efx_rc_t
462 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
464 /* Enable reporting of some events (e.g. link change) */
465 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
468 siena_sram_init(enp);
470 /* Configure Siena's RX block */
471 siena_nic_rx_cfg(enp);
473 /* Disable USR_EVents for now */
474 siena_nic_usrev_dis(enp);
476 /* bug17057: Ensure set_link is called */
477 if ((rc = siena_phy_reconfigure(enp)) != 0)
480 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V1;
487 EFSYS_PROBE1(fail1, efx_rc_t, rc);
496 _NOTE(ARGUNUSED(enp))
503 #if EFSYS_OPT_MON_STATS
504 mcdi_mon_cfg_free(enp);
505 #endif /* EFSYS_OPT_MON_STATS */
506 (void) efx_mcdi_drv_attach(enp, B_FALSE);
511 static siena_register_set_t __siena_registers[] = {
512 { FR_AZ_ADR_REGION_REG_OFST, 0, 1 },
513 { FR_CZ_USR_EV_CFG_OFST, 0, 1 },
514 { FR_AZ_RX_CFG_REG_OFST, 0, 1 },
515 { FR_AZ_TX_CFG_REG_OFST, 0, 1 },
516 { FR_AZ_TX_RESERVED_REG_OFST, 0, 1 },
517 { FR_AZ_SRM_TX_DC_CFG_REG_OFST, 0, 1 },
518 { FR_AZ_RX_DC_CFG_REG_OFST, 0, 1 },
519 { FR_AZ_RX_DC_PF_WM_REG_OFST, 0, 1 },
520 { FR_AZ_DP_CTRL_REG_OFST, 0, 1 },
521 { FR_BZ_RX_RSS_TKEY_REG_OFST, 0, 1},
522 { FR_CZ_RX_RSS_IPV6_REG1_OFST, 0, 1},
523 { FR_CZ_RX_RSS_IPV6_REG2_OFST, 0, 1},
524 { FR_CZ_RX_RSS_IPV6_REG3_OFST, 0, 1}
527 static const uint32_t __siena_register_masks[] = {
528 0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF,
529 0x000103FF, 0x00000000, 0x00000000, 0x00000000,
530 0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000,
531 0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF,
532 0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF,
533 0x001FFFFF, 0x00000000, 0x00000000, 0x00000000,
534 0x00000003, 0x00000000, 0x00000000, 0x00000000,
535 0x000003FF, 0x00000000, 0x00000000, 0x00000000,
536 0x00000FFF, 0x00000000, 0x00000000, 0x00000000,
537 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
538 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
539 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
540 0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000
543 static siena_register_set_t __siena_tables[] = {
544 { FR_AZ_RX_FILTER_TBL0_OFST, FR_AZ_RX_FILTER_TBL0_STEP,
545 FR_AZ_RX_FILTER_TBL0_ROWS },
546 { FR_CZ_RX_MAC_FILTER_TBL0_OFST, FR_CZ_RX_MAC_FILTER_TBL0_STEP,
547 FR_CZ_RX_MAC_FILTER_TBL0_ROWS },
548 { FR_AZ_RX_DESC_PTR_TBL_OFST,
549 FR_AZ_RX_DESC_PTR_TBL_STEP, FR_CZ_RX_DESC_PTR_TBL_ROWS },
550 { FR_AZ_TX_DESC_PTR_TBL_OFST,
551 FR_AZ_TX_DESC_PTR_TBL_STEP, FR_CZ_TX_DESC_PTR_TBL_ROWS },
552 { FR_AZ_TIMER_TBL_OFST, FR_AZ_TIMER_TBL_STEP, FR_CZ_TIMER_TBL_ROWS },
553 { FR_CZ_TX_FILTER_TBL0_OFST,
554 FR_CZ_TX_FILTER_TBL0_STEP, FR_CZ_TX_FILTER_TBL0_ROWS },
555 { FR_CZ_TX_MAC_FILTER_TBL0_OFST,
556 FR_CZ_TX_MAC_FILTER_TBL0_STEP, FR_CZ_TX_MAC_FILTER_TBL0_ROWS }
559 static const uint32_t __siena_table_masks[] = {
560 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000003FF,
561 0xFFFF0FFF, 0xFFFFFFFF, 0x00000E7F, 0x00000000,
562 0xFFFFFFFE, 0x0FFFFFFF, 0x01800000, 0x00000000,
563 0xFFFFFFFE, 0x0FFFFFFF, 0x0C000000, 0x00000000,
564 0x3FFFFFFF, 0x00000000, 0x00000000, 0x00000000,
565 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000013FF,
566 0xFFFF07FF, 0xFFFFFFFF, 0x0000007F, 0x00000000,
569 __checkReturn efx_rc_t
570 siena_nic_test_registers(
572 __in siena_register_set_t *rsp,
576 efx_oword_t original;
582 /* This function is only suitable for registers */
583 EFSYS_ASSERT(rsp->rows == 1);
585 /* bit sweep on and off */
586 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &original,
588 for (bit = 0; bit < 128; bit++) {
589 /* Is this bit in the mask? */
590 if (~(rsp->mask.eo_u32[bit >> 5]) & (1 << bit))
593 /* Test this bit can be set in isolation */
595 EFX_AND_OWORD(reg, rsp->mask);
596 EFX_SET_OWORD_BIT(reg, bit);
598 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
600 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
603 EFX_AND_OWORD(buf, rsp->mask);
604 if (memcmp(®, &buf, sizeof (reg))) {
609 /* Test this bit can be cleared in isolation */
610 EFX_OR_OWORD(reg, rsp->mask);
611 EFX_CLEAR_OWORD_BIT(reg, bit);
613 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
615 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
618 EFX_AND_OWORD(buf, rsp->mask);
619 if (memcmp(®, &buf, sizeof (reg))) {
625 /* Restore the old value */
626 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original,
638 EFSYS_PROBE1(fail1, efx_rc_t, rc);
640 /* Restore the old value */
641 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, B_TRUE);
646 __checkReturn efx_rc_t
647 siena_nic_test_tables(
649 __in siena_register_set_t *rsp,
650 __in efx_pattern_type_t pattern,
653 efx_sram_pattern_fn_t func;
655 unsigned int address;
660 EFSYS_ASSERT(pattern < EFX_PATTERN_NTYPES);
661 func = __efx_sram_pattern_fns[pattern];
665 address = rsp->address;
666 for (index = 0; index < rsp->rows; ++index) {
667 func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
668 func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
669 EFX_AND_OWORD(reg, rsp->mask);
670 EFSYS_BAR_WRITEO(enp->en_esbp, address, ®, B_TRUE);
672 address += rsp->step;
676 address = rsp->address;
677 for (index = 0; index < rsp->rows; ++index) {
678 func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
679 func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
680 EFX_AND_OWORD(reg, rsp->mask);
681 EFSYS_BAR_READO(enp->en_esbp, address, &buf, B_TRUE);
682 if (memcmp(®, &buf, sizeof (reg))) {
687 address += rsp->step;
697 EFSYS_PROBE1(fail1, efx_rc_t, rc);
703 __checkReturn efx_rc_t
704 siena_nic_register_test(
707 siena_register_set_t *rsp;
708 const uint32_t *dwordp;
713 /* Fill out the register mask entries */
714 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_register_masks)
715 == EFX_ARRAY_SIZE(__siena_registers) * 4);
717 nitems = EFX_ARRAY_SIZE(__siena_registers);
718 dwordp = __siena_register_masks;
719 for (count = 0; count < nitems; ++count) {
720 rsp = __siena_registers + count;
721 rsp->mask.eo_u32[0] = *dwordp++;
722 rsp->mask.eo_u32[1] = *dwordp++;
723 rsp->mask.eo_u32[2] = *dwordp++;
724 rsp->mask.eo_u32[3] = *dwordp++;
727 /* Fill out the register table entries */
728 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_table_masks)
729 == EFX_ARRAY_SIZE(__siena_tables) * 4);
731 nitems = EFX_ARRAY_SIZE(__siena_tables);
732 dwordp = __siena_table_masks;
733 for (count = 0; count < nitems; ++count) {
734 rsp = __siena_tables + count;
735 rsp->mask.eo_u32[0] = *dwordp++;
736 rsp->mask.eo_u32[1] = *dwordp++;
737 rsp->mask.eo_u32[2] = *dwordp++;
738 rsp->mask.eo_u32[3] = *dwordp++;
741 if ((rc = siena_nic_test_registers(enp, __siena_registers,
742 EFX_ARRAY_SIZE(__siena_registers))) != 0)
745 if ((rc = siena_nic_test_tables(enp, __siena_tables,
746 EFX_PATTERN_BYTE_ALTERNATE,
747 EFX_ARRAY_SIZE(__siena_tables))) != 0)
750 if ((rc = siena_nic_test_tables(enp, __siena_tables,
751 EFX_PATTERN_BYTE_CHANGING,
752 EFX_ARRAY_SIZE(__siena_tables))) != 0)
755 if ((rc = siena_nic_test_tables(enp, __siena_tables,
756 EFX_PATTERN_BIT_SWEEP, EFX_ARRAY_SIZE(__siena_tables))) != 0)
768 EFSYS_PROBE1(fail1, efx_rc_t, rc);
773 #endif /* EFSYS_OPT_DIAG */
775 #endif /* EFSYS_OPT_SIENA */