2 * Copyright (c) 2009-2016 Solarflare Communications Inc.
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37 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
39 static __checkReturn efx_rc_t
40 siena_nic_get_partn_mask(
42 __out unsigned int *maskp)
45 uint8_t payload[MAX(MC_CMD_NVRAM_TYPES_IN_LEN,
46 MC_CMD_NVRAM_TYPES_OUT_LEN)];
49 (void) memset(payload, 0, sizeof (payload));
50 req.emr_cmd = MC_CMD_NVRAM_TYPES;
51 req.emr_in_buf = payload;
52 req.emr_in_length = MC_CMD_NVRAM_TYPES_IN_LEN;
53 req.emr_out_buf = payload;
54 req.emr_out_length = MC_CMD_NVRAM_TYPES_OUT_LEN;
56 efx_mcdi_execute(enp, &req);
58 if (req.emr_rc != 0) {
63 if (req.emr_out_length_used < MC_CMD_NVRAM_TYPES_OUT_LEN) {
68 *maskp = MCDI_OUT_DWORD(req, NVRAM_TYPES_OUT_TYPES);
75 EFSYS_PROBE1(fail1, efx_rc_t, rc);
80 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
82 static __checkReturn efx_rc_t
86 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
88 efx_dword_t capabilities;
90 uint32_t nevq, nrxq, ntxq;
93 /* External port identifier using one-based port numbering */
94 encp->enc_external_port = (uint8_t)enp->en_mcdi.em_emip.emi_port;
96 /* Board configuration */
97 if ((rc = efx_mcdi_get_board_cfg(enp, &board_type,
98 &capabilities, mac_addr)) != 0)
101 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
103 encp->enc_board_type = board_type;
106 * There is no possibility to determine the number of PFs on Siena
107 * by issuing MCDI request, and it is not an easy task to find the
108 * value based on the board type, so 'enc_hw_pf_count' is set to 1
110 encp->enc_hw_pf_count = 1;
112 /* Additional capabilities */
113 encp->enc_clk_mult = 1;
114 if (EFX_DWORD_FIELD(capabilities, MC_CMD_CAPABILITIES_TURBO)) {
115 enp->en_features |= EFX_FEATURE_TURBO;
117 if (EFX_DWORD_FIELD(capabilities,
118 MC_CMD_CAPABILITIES_TURBO_ACTIVE)) {
119 encp->enc_clk_mult = 2;
123 encp->enc_evq_timer_quantum_ns =
124 EFX_EVQ_SIENA_TIMER_QUANTUM_NS / encp->enc_clk_mult;
125 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
126 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
128 /* When hash header insertion is enabled, Siena inserts 16 bytes */
129 encp->enc_rx_prefix_size = 16;
131 /* Alignment for receive packet DMA buffers */
132 encp->enc_rx_buf_align_start = 1;
133 encp->enc_rx_buf_align_end = 1;
135 /* Alignment for WPTR updates */
136 encp->enc_rx_push_align = 1;
138 /* There is one RSS context per function */
139 encp->enc_rx_scale_max_exclusive_contexts = 1;
141 encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);
142 /* Fragments must not span 4k boundaries. */
143 encp->enc_tx_dma_desc_boundary = 4096;
145 /* Resource limits */
146 rc = efx_mcdi_get_resource_limits(enp, &nevq, &nrxq, &ntxq);
152 nrxq = EFX_RXQ_LIMIT_TARGET;
153 ntxq = EFX_TXQ_LIMIT_TARGET;
155 encp->enc_evq_limit = nevq;
156 encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
157 encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
159 encp->enc_txq_max_ndescs = 4096;
161 encp->enc_buftbl_limit = SIENA_SRAM_ROWS -
162 (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) -
163 (encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
165 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
166 encp->enc_fw_assisted_tso_enabled = B_FALSE;
167 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
168 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
169 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
170 encp->enc_rx_packed_stream_supported = B_FALSE;
171 encp->enc_rx_var_packed_stream_supported = B_FALSE;
173 /* Siena supports two 10G ports, and 8 lanes of PCIe Gen2 */
174 encp->enc_required_pcie_bandwidth_mbps = 2 * 10000;
175 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN2;
177 encp->enc_fw_verified_nvram_update_required = B_FALSE;
184 EFSYS_PROBE1(fail1, efx_rc_t, rc);
189 static __checkReturn efx_rc_t
193 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
196 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
197 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
200 #if EFSYS_OPT_PHY_STATS
201 /* Convert the MCDI statistic mask into the EFX_PHY_STAT mask */
202 siena_phy_decode_stats(enp, encp->enc_mcdi_phy_stat_mask,
203 NULL, &encp->enc_phy_stat_mask, NULL);
204 #endif /* EFSYS_OPT_PHY_STATS */
209 EFSYS_PROBE1(fail1, efx_rc_t, rc);
214 __checkReturn efx_rc_t
218 efx_port_t *epp = &(enp->en_port);
219 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
220 siena_link_state_t sls;
225 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
228 if ((rc = efx_nic_biu_test(enp)) != 0)
231 /* Clear the region register */
232 EFX_POPULATE_OWORD_4(oword,
233 FRF_AZ_ADR_REGION0, 0,
234 FRF_AZ_ADR_REGION1, (1 << 16),
235 FRF_AZ_ADR_REGION2, (2 << 16),
236 FRF_AZ_ADR_REGION3, (3 << 16));
237 EFX_BAR_WRITEO(enp, FR_AZ_ADR_REGION_REG, &oword);
239 /* Read clear any assertion state */
240 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
243 /* Exit the assertion handler */
244 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
247 /* Wrestle control from the BMC */
248 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
251 if ((rc = siena_board_cfg(enp)) != 0)
254 if ((rc = siena_phy_cfg(enp)) != 0)
257 /* Obtain the default PHY advertised capabilities */
258 if ((rc = siena_nic_reset(enp)) != 0)
260 if ((rc = siena_phy_get_link(enp, &sls)) != 0)
262 epp->ep_default_adv_cap_mask = sls.sls_adv_cap_mask;
263 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask;
265 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
266 if ((rc = siena_nic_get_partn_mask(enp, &mask)) != 0)
268 enp->en_u.siena.enu_partn_mask = mask;
271 #if EFSYS_OPT_MAC_STATS
272 /* Wipe the MAC statistics */
273 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
277 #if EFSYS_OPT_LOOPBACK
278 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
282 #if EFSYS_OPT_MON_STATS
283 if ((rc = mcdi_mon_cfg_build(enp)) != 0)
287 encp->enc_features = enp->en_features;
291 #if EFSYS_OPT_MON_STATS
295 #if EFSYS_OPT_LOOPBACK
299 #if EFSYS_OPT_MAC_STATS
303 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
322 EFSYS_PROBE1(fail1, efx_rc_t, rc);
327 __checkReturn efx_rc_t
334 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
336 /* siena_nic_reset() is called to recover from BADASSERT failures. */
337 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
339 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
343 * Bug24908: ENTITY_RESET_IN_LEN is non zero but zero may be supplied
344 * for backwards compatibility with PORT_RESET_IN_LEN.
346 EFX_STATIC_ASSERT(MC_CMD_ENTITY_RESET_OUT_LEN == 0);
348 req.emr_cmd = MC_CMD_ENTITY_RESET;
349 req.emr_in_buf = NULL;
350 req.emr_in_length = 0;
351 req.emr_out_buf = NULL;
352 req.emr_out_length = 0;
354 efx_mcdi_execute(enp, &req);
356 if (req.emr_rc != 0) {
368 EFSYS_PROBE1(fail1, efx_rc_t, rc);
380 * RX_INGR_EN is always enabled on Siena, because we rely on
381 * the RX parser to be resiliant to missing SOP/EOP.
383 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
384 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_INGR_EN, 1);
385 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
387 /* Disable parsing of additional 802.1Q in Q packets */
388 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
389 EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES, 0);
390 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
399 EFX_POPULATE_OWORD_1(oword, FRF_CZ_USREV_DIS, 1);
400 EFX_BAR_WRITEO(enp, FR_CZ_USR_EV_CFG, &oword);
403 __checkReturn efx_rc_t
409 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
411 /* Enable reporting of some events (e.g. link change) */
412 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
415 siena_sram_init(enp);
417 /* Configure Siena's RX block */
418 siena_nic_rx_cfg(enp);
420 /* Disable USR_EVents for now */
421 siena_nic_usrev_dis(enp);
423 /* bug17057: Ensure set_link is called */
424 if ((rc = siena_phy_reconfigure(enp)) != 0)
427 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V1;
434 EFSYS_PROBE1(fail1, efx_rc_t, rc);
443 _NOTE(ARGUNUSED(enp))
450 #if EFSYS_OPT_MON_STATS
451 mcdi_mon_cfg_free(enp);
452 #endif /* EFSYS_OPT_MON_STATS */
453 (void) efx_mcdi_drv_attach(enp, B_FALSE);
458 static efx_register_set_t __siena_registers[] = {
459 { FR_AZ_ADR_REGION_REG_OFST, 0, 1 },
460 { FR_CZ_USR_EV_CFG_OFST, 0, 1 },
461 { FR_AZ_RX_CFG_REG_OFST, 0, 1 },
462 { FR_AZ_TX_CFG_REG_OFST, 0, 1 },
463 { FR_AZ_TX_RESERVED_REG_OFST, 0, 1 },
464 { FR_AZ_SRM_TX_DC_CFG_REG_OFST, 0, 1 },
465 { FR_AZ_RX_DC_CFG_REG_OFST, 0, 1 },
466 { FR_AZ_RX_DC_PF_WM_REG_OFST, 0, 1 },
467 { FR_AZ_DP_CTRL_REG_OFST, 0, 1 },
468 { FR_BZ_RX_RSS_TKEY_REG_OFST, 0, 1},
469 { FR_CZ_RX_RSS_IPV6_REG1_OFST, 0, 1},
470 { FR_CZ_RX_RSS_IPV6_REG2_OFST, 0, 1},
471 { FR_CZ_RX_RSS_IPV6_REG3_OFST, 0, 1}
474 static const uint32_t __siena_register_masks[] = {
475 0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF,
476 0x000103FF, 0x00000000, 0x00000000, 0x00000000,
477 0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000,
478 0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF,
479 0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF,
480 0x001FFFFF, 0x00000000, 0x00000000, 0x00000000,
481 0x00000003, 0x00000000, 0x00000000, 0x00000000,
482 0x000003FF, 0x00000000, 0x00000000, 0x00000000,
483 0x00000FFF, 0x00000000, 0x00000000, 0x00000000,
484 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
485 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
486 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
487 0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000
490 static efx_register_set_t __siena_tables[] = {
491 { FR_AZ_RX_FILTER_TBL0_OFST, FR_AZ_RX_FILTER_TBL0_STEP,
492 FR_AZ_RX_FILTER_TBL0_ROWS },
493 { FR_CZ_RX_MAC_FILTER_TBL0_OFST, FR_CZ_RX_MAC_FILTER_TBL0_STEP,
494 FR_CZ_RX_MAC_FILTER_TBL0_ROWS },
495 { FR_AZ_RX_DESC_PTR_TBL_OFST,
496 FR_AZ_RX_DESC_PTR_TBL_STEP, FR_CZ_RX_DESC_PTR_TBL_ROWS },
497 { FR_AZ_TX_DESC_PTR_TBL_OFST,
498 FR_AZ_TX_DESC_PTR_TBL_STEP, FR_CZ_TX_DESC_PTR_TBL_ROWS },
499 { FR_AZ_TIMER_TBL_OFST, FR_AZ_TIMER_TBL_STEP, FR_CZ_TIMER_TBL_ROWS },
500 { FR_CZ_TX_FILTER_TBL0_OFST,
501 FR_CZ_TX_FILTER_TBL0_STEP, FR_CZ_TX_FILTER_TBL0_ROWS },
502 { FR_CZ_TX_MAC_FILTER_TBL0_OFST,
503 FR_CZ_TX_MAC_FILTER_TBL0_STEP, FR_CZ_TX_MAC_FILTER_TBL0_ROWS }
506 static const uint32_t __siena_table_masks[] = {
507 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000003FF,
508 0xFFFF0FFF, 0xFFFFFFFF, 0x00000E7F, 0x00000000,
509 0xFFFFFFFE, 0x0FFFFFFF, 0x01800000, 0x00000000,
510 0xFFFFFFFE, 0x0FFFFFFF, 0x0C000000, 0x00000000,
511 0x3FFFFFFF, 0x00000000, 0x00000000, 0x00000000,
512 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000013FF,
513 0xFFFF07FF, 0xFFFFFFFF, 0x0000007F, 0x00000000,
516 __checkReturn efx_rc_t
517 siena_nic_register_test(
520 efx_register_set_t *rsp;
521 const uint32_t *dwordp;
526 /* Fill out the register mask entries */
527 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_register_masks)
528 == EFX_ARRAY_SIZE(__siena_registers) * 4);
530 nitems = EFX_ARRAY_SIZE(__siena_registers);
531 dwordp = __siena_register_masks;
532 for (count = 0; count < nitems; ++count) {
533 rsp = __siena_registers + count;
534 rsp->mask.eo_u32[0] = *dwordp++;
535 rsp->mask.eo_u32[1] = *dwordp++;
536 rsp->mask.eo_u32[2] = *dwordp++;
537 rsp->mask.eo_u32[3] = *dwordp++;
540 /* Fill out the register table entries */
541 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_table_masks)
542 == EFX_ARRAY_SIZE(__siena_tables) * 4);
544 nitems = EFX_ARRAY_SIZE(__siena_tables);
545 dwordp = __siena_table_masks;
546 for (count = 0; count < nitems; ++count) {
547 rsp = __siena_tables + count;
548 rsp->mask.eo_u32[0] = *dwordp++;
549 rsp->mask.eo_u32[1] = *dwordp++;
550 rsp->mask.eo_u32[2] = *dwordp++;
551 rsp->mask.eo_u32[3] = *dwordp++;
554 if ((rc = efx_nic_test_registers(enp, __siena_registers,
555 EFX_ARRAY_SIZE(__siena_registers))) != 0)
558 if ((rc = efx_nic_test_tables(enp, __siena_tables,
559 EFX_PATTERN_BYTE_ALTERNATE,
560 EFX_ARRAY_SIZE(__siena_tables))) != 0)
563 if ((rc = efx_nic_test_tables(enp, __siena_tables,
564 EFX_PATTERN_BYTE_CHANGING,
565 EFX_ARRAY_SIZE(__siena_tables))) != 0)
568 if ((rc = efx_nic_test_tables(enp, __siena_tables,
569 EFX_PATTERN_BIT_SWEEP, EFX_ARRAY_SIZE(__siena_tables))) != 0)
581 EFSYS_PROBE1(fail1, efx_rc_t, rc);
586 #endif /* EFSYS_OPT_DIAG */
588 #endif /* EFSYS_OPT_SIENA */