2 * Copyright (c) 2009-2016 Solarflare Communications Inc.
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37 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
39 static __checkReturn efx_rc_t
40 siena_nic_get_partn_mask(
42 __out unsigned int *maskp)
45 uint8_t payload[MAX(MC_CMD_NVRAM_TYPES_IN_LEN,
46 MC_CMD_NVRAM_TYPES_OUT_LEN)];
49 (void) memset(payload, 0, sizeof (payload));
50 req.emr_cmd = MC_CMD_NVRAM_TYPES;
51 req.emr_in_buf = payload;
52 req.emr_in_length = MC_CMD_NVRAM_TYPES_IN_LEN;
53 req.emr_out_buf = payload;
54 req.emr_out_length = MC_CMD_NVRAM_TYPES_OUT_LEN;
56 efx_mcdi_execute(enp, &req);
58 if (req.emr_rc != 0) {
63 if (req.emr_out_length_used < MC_CMD_NVRAM_TYPES_OUT_LEN) {
68 *maskp = MCDI_OUT_DWORD(req, NVRAM_TYPES_OUT_TYPES);
75 EFSYS_PROBE1(fail1, efx_rc_t, rc);
80 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
82 static __checkReturn efx_rc_t
86 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
88 efx_dword_t capabilities;
90 uint32_t nevq, nrxq, ntxq;
93 /* External port identifier using one-based port numbering */
94 encp->enc_external_port = (uint8_t)enp->en_mcdi.em_emip.emi_port;
96 /* Board configuration */
97 if ((rc = efx_mcdi_get_board_cfg(enp, &board_type,
98 &capabilities, mac_addr)) != 0)
101 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
103 encp->enc_board_type = board_type;
106 * There is no possibility to determine the number of PFs on Siena
107 * by issuing MCDI request, and it is not an easy task to find the
108 * value based on the board type, so 'enc_hw_pf_count' is set to 1
110 encp->enc_hw_pf_count = 1;
112 /* Additional capabilities */
113 encp->enc_clk_mult = 1;
114 if (EFX_DWORD_FIELD(capabilities, MC_CMD_CAPABILITIES_TURBO)) {
115 enp->en_features |= EFX_FEATURE_TURBO;
117 if (EFX_DWORD_FIELD(capabilities,
118 MC_CMD_CAPABILITIES_TURBO_ACTIVE)) {
119 encp->enc_clk_mult = 2;
123 encp->enc_evq_timer_quantum_ns =
124 EFX_EVQ_SIENA_TIMER_QUANTUM_NS / encp->enc_clk_mult;
125 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
126 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
128 /* When hash header insertion is enabled, Siena inserts 16 bytes */
129 encp->enc_rx_prefix_size = 16;
131 /* Alignment for receive packet DMA buffers */
132 encp->enc_rx_buf_align_start = 1;
133 encp->enc_rx_buf_align_end = 1;
135 /* Alignment for WPTR updates */
136 encp->enc_rx_push_align = 1;
138 encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);
139 /* Fragments must not span 4k boundaries. */
140 encp->enc_tx_dma_desc_boundary = 4096;
142 /* Resource limits */
143 rc = efx_mcdi_get_resource_limits(enp, &nevq, &nrxq, &ntxq);
149 nrxq = EFX_RXQ_LIMIT_TARGET;
150 ntxq = EFX_TXQ_LIMIT_TARGET;
152 encp->enc_evq_limit = nevq;
153 encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
154 encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
156 encp->enc_txq_max_ndescs = 4096;
158 encp->enc_buftbl_limit = SIENA_SRAM_ROWS -
159 (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) -
160 (encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
162 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
163 encp->enc_fw_assisted_tso_enabled = B_FALSE;
164 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
165 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
166 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
167 encp->enc_rx_packed_stream_supported = B_FALSE;
168 encp->enc_rx_var_packed_stream_supported = B_FALSE;
170 /* Siena supports two 10G ports, and 8 lanes of PCIe Gen2 */
171 encp->enc_required_pcie_bandwidth_mbps = 2 * 10000;
172 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN2;
174 encp->enc_fw_verified_nvram_update_required = B_FALSE;
181 EFSYS_PROBE1(fail1, efx_rc_t, rc);
186 static __checkReturn efx_rc_t
190 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
193 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
194 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
197 #if EFSYS_OPT_PHY_STATS
198 /* Convert the MCDI statistic mask into the EFX_PHY_STAT mask */
199 siena_phy_decode_stats(enp, encp->enc_mcdi_phy_stat_mask,
200 NULL, &encp->enc_phy_stat_mask, NULL);
201 #endif /* EFSYS_OPT_PHY_STATS */
206 EFSYS_PROBE1(fail1, efx_rc_t, rc);
211 __checkReturn efx_rc_t
215 efx_port_t *epp = &(enp->en_port);
216 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
217 siena_link_state_t sls;
222 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
225 if ((rc = efx_nic_biu_test(enp)) != 0)
228 /* Clear the region register */
229 EFX_POPULATE_OWORD_4(oword,
230 FRF_AZ_ADR_REGION0, 0,
231 FRF_AZ_ADR_REGION1, (1 << 16),
232 FRF_AZ_ADR_REGION2, (2 << 16),
233 FRF_AZ_ADR_REGION3, (3 << 16));
234 EFX_BAR_WRITEO(enp, FR_AZ_ADR_REGION_REG, &oword);
236 /* Read clear any assertion state */
237 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
240 /* Exit the assertion handler */
241 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
244 /* Wrestle control from the BMC */
245 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
248 if ((rc = siena_board_cfg(enp)) != 0)
251 if ((rc = siena_phy_cfg(enp)) != 0)
254 /* Obtain the default PHY advertised capabilities */
255 if ((rc = siena_nic_reset(enp)) != 0)
257 if ((rc = siena_phy_get_link(enp, &sls)) != 0)
259 epp->ep_default_adv_cap_mask = sls.sls_adv_cap_mask;
260 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask;
262 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
263 if ((rc = siena_nic_get_partn_mask(enp, &mask)) != 0)
265 enp->en_u.siena.enu_partn_mask = mask;
268 #if EFSYS_OPT_MAC_STATS
269 /* Wipe the MAC statistics */
270 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
274 #if EFSYS_OPT_LOOPBACK
275 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
279 #if EFSYS_OPT_MON_STATS
280 if ((rc = mcdi_mon_cfg_build(enp)) != 0)
284 encp->enc_features = enp->en_features;
288 #if EFSYS_OPT_MON_STATS
292 #if EFSYS_OPT_LOOPBACK
296 #if EFSYS_OPT_MAC_STATS
300 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
319 EFSYS_PROBE1(fail1, efx_rc_t, rc);
324 __checkReturn efx_rc_t
331 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
333 /* siena_nic_reset() is called to recover from BADASSERT failures. */
334 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
336 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
340 * Bug24908: ENTITY_RESET_IN_LEN is non zero but zero may be supplied
341 * for backwards compatibility with PORT_RESET_IN_LEN.
343 EFX_STATIC_ASSERT(MC_CMD_ENTITY_RESET_OUT_LEN == 0);
345 req.emr_cmd = MC_CMD_ENTITY_RESET;
346 req.emr_in_buf = NULL;
347 req.emr_in_length = 0;
348 req.emr_out_buf = NULL;
349 req.emr_out_length = 0;
351 efx_mcdi_execute(enp, &req);
353 if (req.emr_rc != 0) {
365 EFSYS_PROBE1(fail1, efx_rc_t, rc);
377 * RX_INGR_EN is always enabled on Siena, because we rely on
378 * the RX parser to be resiliant to missing SOP/EOP.
380 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
381 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_INGR_EN, 1);
382 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
384 /* Disable parsing of additional 802.1Q in Q packets */
385 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
386 EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES, 0);
387 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
396 EFX_POPULATE_OWORD_1(oword, FRF_CZ_USREV_DIS, 1);
397 EFX_BAR_WRITEO(enp, FR_CZ_USR_EV_CFG, &oword);
400 __checkReturn efx_rc_t
406 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
408 /* Enable reporting of some events (e.g. link change) */
409 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
412 siena_sram_init(enp);
414 /* Configure Siena's RX block */
415 siena_nic_rx_cfg(enp);
417 /* Disable USR_EVents for now */
418 siena_nic_usrev_dis(enp);
420 /* bug17057: Ensure set_link is called */
421 if ((rc = siena_phy_reconfigure(enp)) != 0)
424 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V1;
431 EFSYS_PROBE1(fail1, efx_rc_t, rc);
440 _NOTE(ARGUNUSED(enp))
447 #if EFSYS_OPT_MON_STATS
448 mcdi_mon_cfg_free(enp);
449 #endif /* EFSYS_OPT_MON_STATS */
450 (void) efx_mcdi_drv_attach(enp, B_FALSE);
455 static efx_register_set_t __siena_registers[] = {
456 { FR_AZ_ADR_REGION_REG_OFST, 0, 1 },
457 { FR_CZ_USR_EV_CFG_OFST, 0, 1 },
458 { FR_AZ_RX_CFG_REG_OFST, 0, 1 },
459 { FR_AZ_TX_CFG_REG_OFST, 0, 1 },
460 { FR_AZ_TX_RESERVED_REG_OFST, 0, 1 },
461 { FR_AZ_SRM_TX_DC_CFG_REG_OFST, 0, 1 },
462 { FR_AZ_RX_DC_CFG_REG_OFST, 0, 1 },
463 { FR_AZ_RX_DC_PF_WM_REG_OFST, 0, 1 },
464 { FR_AZ_DP_CTRL_REG_OFST, 0, 1 },
465 { FR_BZ_RX_RSS_TKEY_REG_OFST, 0, 1},
466 { FR_CZ_RX_RSS_IPV6_REG1_OFST, 0, 1},
467 { FR_CZ_RX_RSS_IPV6_REG2_OFST, 0, 1},
468 { FR_CZ_RX_RSS_IPV6_REG3_OFST, 0, 1}
471 static const uint32_t __siena_register_masks[] = {
472 0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF,
473 0x000103FF, 0x00000000, 0x00000000, 0x00000000,
474 0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000,
475 0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF,
476 0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF,
477 0x001FFFFF, 0x00000000, 0x00000000, 0x00000000,
478 0x00000003, 0x00000000, 0x00000000, 0x00000000,
479 0x000003FF, 0x00000000, 0x00000000, 0x00000000,
480 0x00000FFF, 0x00000000, 0x00000000, 0x00000000,
481 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
482 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
483 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
484 0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000
487 static efx_register_set_t __siena_tables[] = {
488 { FR_AZ_RX_FILTER_TBL0_OFST, FR_AZ_RX_FILTER_TBL0_STEP,
489 FR_AZ_RX_FILTER_TBL0_ROWS },
490 { FR_CZ_RX_MAC_FILTER_TBL0_OFST, FR_CZ_RX_MAC_FILTER_TBL0_STEP,
491 FR_CZ_RX_MAC_FILTER_TBL0_ROWS },
492 { FR_AZ_RX_DESC_PTR_TBL_OFST,
493 FR_AZ_RX_DESC_PTR_TBL_STEP, FR_CZ_RX_DESC_PTR_TBL_ROWS },
494 { FR_AZ_TX_DESC_PTR_TBL_OFST,
495 FR_AZ_TX_DESC_PTR_TBL_STEP, FR_CZ_TX_DESC_PTR_TBL_ROWS },
496 { FR_AZ_TIMER_TBL_OFST, FR_AZ_TIMER_TBL_STEP, FR_CZ_TIMER_TBL_ROWS },
497 { FR_CZ_TX_FILTER_TBL0_OFST,
498 FR_CZ_TX_FILTER_TBL0_STEP, FR_CZ_TX_FILTER_TBL0_ROWS },
499 { FR_CZ_TX_MAC_FILTER_TBL0_OFST,
500 FR_CZ_TX_MAC_FILTER_TBL0_STEP, FR_CZ_TX_MAC_FILTER_TBL0_ROWS }
503 static const uint32_t __siena_table_masks[] = {
504 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000003FF,
505 0xFFFF0FFF, 0xFFFFFFFF, 0x00000E7F, 0x00000000,
506 0xFFFFFFFE, 0x0FFFFFFF, 0x01800000, 0x00000000,
507 0xFFFFFFFE, 0x0FFFFFFF, 0x0C000000, 0x00000000,
508 0x3FFFFFFF, 0x00000000, 0x00000000, 0x00000000,
509 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000013FF,
510 0xFFFF07FF, 0xFFFFFFFF, 0x0000007F, 0x00000000,
513 __checkReturn efx_rc_t
514 siena_nic_register_test(
517 efx_register_set_t *rsp;
518 const uint32_t *dwordp;
523 /* Fill out the register mask entries */
524 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_register_masks)
525 == EFX_ARRAY_SIZE(__siena_registers) * 4);
527 nitems = EFX_ARRAY_SIZE(__siena_registers);
528 dwordp = __siena_register_masks;
529 for (count = 0; count < nitems; ++count) {
530 rsp = __siena_registers + count;
531 rsp->mask.eo_u32[0] = *dwordp++;
532 rsp->mask.eo_u32[1] = *dwordp++;
533 rsp->mask.eo_u32[2] = *dwordp++;
534 rsp->mask.eo_u32[3] = *dwordp++;
537 /* Fill out the register table entries */
538 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_table_masks)
539 == EFX_ARRAY_SIZE(__siena_tables) * 4);
541 nitems = EFX_ARRAY_SIZE(__siena_tables);
542 dwordp = __siena_table_masks;
543 for (count = 0; count < nitems; ++count) {
544 rsp = __siena_tables + count;
545 rsp->mask.eo_u32[0] = *dwordp++;
546 rsp->mask.eo_u32[1] = *dwordp++;
547 rsp->mask.eo_u32[2] = *dwordp++;
548 rsp->mask.eo_u32[3] = *dwordp++;
551 if ((rc = efx_nic_test_registers(enp, __siena_registers,
552 EFX_ARRAY_SIZE(__siena_registers))) != 0)
555 if ((rc = efx_nic_test_tables(enp, __siena_tables,
556 EFX_PATTERN_BYTE_ALTERNATE,
557 EFX_ARRAY_SIZE(__siena_tables))) != 0)
560 if ((rc = efx_nic_test_tables(enp, __siena_tables,
561 EFX_PATTERN_BYTE_CHANGING,
562 EFX_ARRAY_SIZE(__siena_tables))) != 0)
565 if ((rc = efx_nic_test_tables(enp, __siena_tables,
566 EFX_PATTERN_BIT_SWEEP, EFX_ARRAY_SIZE(__siena_tables))) != 0)
578 EFSYS_PROBE1(fail1, efx_rc_t, rc);
583 #endif /* EFSYS_OPT_DIAG */
585 #endif /* EFSYS_OPT_SIENA */