1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2009-2018 Solarflare Communications Inc.
12 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
14 __checkReturn efx_rc_t
15 siena_nvram_partn_size(
22 if ((1 << partn) & ~enp->en_u.siena.enu_partn_mask) {
27 if ((rc = efx_mcdi_nvram_info(enp, partn, sizep,
28 NULL, NULL, NULL)) != 0) {
37 EFSYS_PROBE1(fail1, efx_rc_t, rc);
42 __checkReturn efx_rc_t
43 siena_nvram_partn_info(
46 __out efx_nvram_info_t * enip)
50 if ((rc = efx_mcdi_nvram_info_ex(enp, partn, enip)) != 0)
53 if (enip->eni_write_size == 0)
54 enip->eni_write_size = SIENA_NVRAM_CHUNK;
59 EFSYS_PROBE1(fail1, efx_rc_t, rc);
65 __checkReturn efx_rc_t
66 siena_nvram_partn_lock(
72 if ((rc = efx_mcdi_nvram_update_start(enp, partn)) != 0) {
79 EFSYS_PROBE1(fail1, efx_rc_t, rc);
84 __checkReturn efx_rc_t
85 siena_nvram_partn_read(
88 __in unsigned int offset,
89 __out_bcount(size) caddr_t data,
96 chunk = MIN(size, SIENA_NVRAM_CHUNK);
98 if ((rc = efx_mcdi_nvram_read(enp, partn, offset, data, chunk,
99 MC_CMD_NVRAM_READ_IN_V2_DEFAULT)) != 0) {
111 EFSYS_PROBE1(fail1, efx_rc_t, rc);
116 __checkReturn efx_rc_t
117 siena_nvram_partn_erase(
120 __in unsigned int offset,
125 if ((rc = efx_mcdi_nvram_erase(enp, partn, offset, size)) != 0) {
132 EFSYS_PROBE1(fail1, efx_rc_t, rc);
137 __checkReturn efx_rc_t
138 siena_nvram_partn_write(
141 __in unsigned int offset,
142 __out_bcount(size) caddr_t data,
149 chunk = MIN(size, SIENA_NVRAM_CHUNK);
151 if ((rc = efx_mcdi_nvram_write(enp, partn, offset,
152 data, chunk)) != 0) {
164 EFSYS_PROBE1(fail1, efx_rc_t, rc);
169 __checkReturn efx_rc_t
170 siena_nvram_partn_unlock(
173 __out_opt uint32_t *verify_resultp)
179 * Reboot into the new image only for PHYs. The driver has to
180 * explicitly cope with an MC reboot after a firmware update.
182 reboot = (partn == MC_CMD_NVRAM_TYPE_PHY_PORT0 ||
183 partn == MC_CMD_NVRAM_TYPE_PHY_PORT1 ||
184 partn == MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO);
186 rc = efx_mcdi_nvram_update_finish(enp, partn, reboot, verify_resultp);
193 EFSYS_PROBE1(fail1, efx_rc_t, rc);
198 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
202 typedef struct siena_parttbl_entry_s {
205 efx_nvram_type_t nvtype;
206 } siena_parttbl_entry_t;
208 static siena_parttbl_entry_t siena_parttbl[] = {
209 {MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO, 1, EFX_NVRAM_NULLPHY},
210 {MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO, 2, EFX_NVRAM_NULLPHY},
211 {MC_CMD_NVRAM_TYPE_MC_FW, 1, EFX_NVRAM_MC_FIRMWARE},
212 {MC_CMD_NVRAM_TYPE_MC_FW, 2, EFX_NVRAM_MC_FIRMWARE},
213 {MC_CMD_NVRAM_TYPE_MC_FW_BACKUP, 1, EFX_NVRAM_MC_GOLDEN},
214 {MC_CMD_NVRAM_TYPE_MC_FW_BACKUP, 2, EFX_NVRAM_MC_GOLDEN},
215 {MC_CMD_NVRAM_TYPE_EXP_ROM, 1, EFX_NVRAM_BOOTROM},
216 {MC_CMD_NVRAM_TYPE_EXP_ROM, 2, EFX_NVRAM_BOOTROM},
217 {MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0, 1, EFX_NVRAM_BOOTROM_CFG},
218 {MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1, 2, EFX_NVRAM_BOOTROM_CFG},
219 {MC_CMD_NVRAM_TYPE_PHY_PORT0, 1, EFX_NVRAM_PHY},
220 {MC_CMD_NVRAM_TYPE_PHY_PORT1, 2, EFX_NVRAM_PHY},
221 {MC_CMD_NVRAM_TYPE_FPGA, 1, EFX_NVRAM_FPGA},
222 {MC_CMD_NVRAM_TYPE_FPGA, 2, EFX_NVRAM_FPGA},
223 {MC_CMD_NVRAM_TYPE_FPGA_BACKUP, 1, EFX_NVRAM_FPGA_BACKUP},
224 {MC_CMD_NVRAM_TYPE_FPGA_BACKUP, 2, EFX_NVRAM_FPGA_BACKUP},
225 {MC_CMD_NVRAM_TYPE_FC_FW, 1, EFX_NVRAM_FCFW},
226 {MC_CMD_NVRAM_TYPE_FC_FW, 2, EFX_NVRAM_FCFW},
227 {MC_CMD_NVRAM_TYPE_CPLD, 1, EFX_NVRAM_CPLD},
228 {MC_CMD_NVRAM_TYPE_CPLD, 2, EFX_NVRAM_CPLD},
229 {MC_CMD_NVRAM_TYPE_LICENSE, 1, EFX_NVRAM_LICENSE},
230 {MC_CMD_NVRAM_TYPE_LICENSE, 2, EFX_NVRAM_LICENSE}
233 __checkReturn efx_rc_t
234 siena_nvram_type_to_partn(
236 __in efx_nvram_type_t type,
237 __out uint32_t *partnp)
239 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
242 EFSYS_ASSERT3U(type, !=, EFX_NVRAM_INVALID);
243 EFSYS_ASSERT3U(type, <, EFX_NVRAM_NTYPES);
244 EFSYS_ASSERT(partnp != NULL);
246 for (i = 0; i < EFX_ARRAY_SIZE(siena_parttbl); i++) {
247 siena_parttbl_entry_t *entry = &siena_parttbl[i];
249 if (entry->port == emip->emi_port && entry->nvtype == type) {
250 *partnp = entry->partn;
261 __checkReturn efx_rc_t
265 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
266 siena_parttbl_entry_t *entry;
271 * Iterate over the list of supported partition types
272 * applicable to *this* port
274 for (i = 0; i < EFX_ARRAY_SIZE(siena_parttbl); i++) {
275 entry = &siena_parttbl[i];
277 if (entry->port != emip->emi_port ||
278 !(enp->en_u.siena.enu_partn_mask & (1 << entry->partn)))
281 if ((rc = efx_mcdi_nvram_test(enp, entry->partn)) != 0) {
289 EFSYS_PROBE1(fail1, efx_rc_t, rc);
294 #endif /* EFSYS_OPT_DIAG */
297 #define SIENA_DYNAMIC_CFG_SIZE(_nitems) \
298 (sizeof (siena_mc_dynamic_config_hdr_t) + ((_nitems) * \
299 sizeof (((siena_mc_dynamic_config_hdr_t *)NULL)->fw_version[0])))
301 __checkReturn efx_rc_t
302 siena_nvram_get_dynamic_cfg(
306 __out siena_mc_dynamic_config_hdr_t **dcfgp,
309 siena_mc_dynamic_config_hdr_t *dcfg = NULL;
312 unsigned int vpd_offset;
313 unsigned int vpd_length;
314 unsigned int hdr_length;
315 unsigned int nversions;
320 EFSYS_ASSERT(partn == MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 ||
321 partn == MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1);
324 * Allocate sufficient memory for the entire dynamiccfg area, even
325 * if we're not actually going to read in the VPD.
327 if ((rc = siena_nvram_partn_size(enp, partn, &size)) != 0)
330 if (size < SIENA_NVRAM_CHUNK) {
335 EFSYS_KMEM_ALLOC(enp->en_esip, size, dcfg);
341 if ((rc = siena_nvram_partn_read(enp, partn, 0,
342 (caddr_t)dcfg, SIENA_NVRAM_CHUNK)) != 0)
345 /* Verify the magic */
346 if (EFX_DWORD_FIELD(dcfg->magic, EFX_DWORD_0)
347 != SIENA_MC_DYNAMIC_CONFIG_MAGIC)
350 /* All future versions of the structure must be backwards compatible */
351 EFX_STATIC_ASSERT(SIENA_MC_DYNAMIC_CONFIG_VERSION == 0);
353 hdr_length = EFX_WORD_FIELD(dcfg->length, EFX_WORD_0);
354 nversions = EFX_DWORD_FIELD(dcfg->num_fw_version_items, EFX_DWORD_0);
355 vpd_offset = EFX_DWORD_FIELD(dcfg->dynamic_vpd_offset, EFX_DWORD_0);
356 vpd_length = EFX_DWORD_FIELD(dcfg->dynamic_vpd_length, EFX_DWORD_0);
358 /* Verify the hdr doesn't overflow the partn size */
359 if (hdr_length > size || vpd_offset > size || vpd_length > size ||
360 vpd_length + vpd_offset > size)
363 /* Verify the header has room for all it's versions */
364 if (hdr_length < SIENA_DYNAMIC_CFG_SIZE(0) ||
365 hdr_length < SIENA_DYNAMIC_CFG_SIZE(nversions))
369 * Read the remaining portion of the dcfg, either including
370 * the whole of VPD (there is no vpd length in this structure,
371 * so we have to parse each tag), or just the dcfg header itself
373 region = vpd ? vpd_offset + vpd_length : hdr_length;
374 if (region > SIENA_NVRAM_CHUNK) {
375 if ((rc = siena_nvram_partn_read(enp, partn, SIENA_NVRAM_CHUNK,
376 (caddr_t)dcfg + SIENA_NVRAM_CHUNK,
377 region - SIENA_NVRAM_CHUNK)) != 0)
381 /* Verify checksum */
383 for (pos = 0; pos < hdr_length; pos++)
384 cksum += ((uint8_t *)dcfg)[pos];
391 EFSYS_PROBE(invalid4);
393 EFSYS_PROBE(invalid3);
395 EFSYS_PROBE(invalid2);
397 EFSYS_PROBE(invalid1);
400 * Construct a new "null" dcfg, with an empty version vector,
401 * and an empty VPD chunk trailing. This has the neat side effect
402 * of testing the exception paths in the write path.
404 EFX_POPULATE_DWORD_1(dcfg->magic,
405 EFX_DWORD_0, SIENA_MC_DYNAMIC_CONFIG_MAGIC);
406 EFX_POPULATE_WORD_1(dcfg->length, EFX_WORD_0, sizeof (*dcfg));
407 EFX_POPULATE_BYTE_1(dcfg->version, EFX_BYTE_0,
408 SIENA_MC_DYNAMIC_CONFIG_VERSION);
409 EFX_POPULATE_DWORD_1(dcfg->dynamic_vpd_offset,
410 EFX_DWORD_0, sizeof (*dcfg));
411 EFX_POPULATE_DWORD_1(dcfg->dynamic_vpd_length, EFX_DWORD_0, 0);
412 EFX_POPULATE_DWORD_1(dcfg->num_fw_version_items, EFX_DWORD_0, 0);
425 EFSYS_KMEM_FREE(enp->en_esip, size, dcfg);
432 EFSYS_PROBE1(fail1, efx_rc_t, rc);
437 __checkReturn efx_rc_t
438 siena_nvram_get_subtype(
441 __out uint32_t *subtypep)
444 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_BOARD_CFG_IN_LEN,
445 MC_CMD_GET_BOARD_CFG_OUT_LENMAX);
449 req.emr_cmd = MC_CMD_GET_BOARD_CFG;
450 req.emr_in_buf = payload;
451 req.emr_in_length = MC_CMD_GET_BOARD_CFG_IN_LEN;
452 req.emr_out_buf = payload;
453 req.emr_out_length = MC_CMD_GET_BOARD_CFG_OUT_LENMAX;
455 efx_mcdi_execute(enp, &req);
457 if (req.emr_rc != 0) {
462 if (req.emr_out_length_used < MC_CMD_GET_BOARD_CFG_OUT_LENMIN) {
467 if (req.emr_out_length_used <
468 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST +
469 (partn + 1) * sizeof (efx_word_t)) {
474 fw_list = MCDI_OUT2(req, efx_word_t,
475 GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST);
476 *subtypep = EFX_WORD_FIELD(fw_list[partn], EFX_WORD_0);
485 EFSYS_PROBE1(fail1, efx_rc_t, rc);
490 __checkReturn efx_rc_t
491 siena_nvram_partn_get_version(
494 __out uint32_t *subtypep,
495 __out_ecount(4) uint16_t version[4])
497 siena_mc_dynamic_config_hdr_t *dcfg;
498 siena_parttbl_entry_t *entry;
503 if ((1 << partn) & ~enp->en_u.siena.enu_partn_mask) {
508 if ((rc = siena_nvram_get_subtype(enp, partn, subtypep)) != 0)
512 * Some partitions are accessible from both ports (for instance BOOTROM)
513 * Find the highest version reported by all dcfg structures on ports
514 * that have access to this partition.
516 version[0] = version[1] = version[2] = version[3] = 0;
517 for (i = 0; i < EFX_ARRAY_SIZE(siena_parttbl); i++) {
518 siena_mc_fw_version_t *verp;
523 entry = &siena_parttbl[i];
524 if (entry->partn != partn)
527 dcfg_partn = (entry->port == 1)
528 ? MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0
529 : MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1;
531 * Ingore missing partitions on port 2, assuming they're due
532 * to to running on a single port part.
534 if ((1 << dcfg_partn) & ~enp->en_u.siena.enu_partn_mask) {
535 if (entry->port == 2)
539 if ((rc = siena_nvram_get_dynamic_cfg(enp, dcfg_partn,
540 B_FALSE, &dcfg, &length)) != 0)
543 nitems = EFX_DWORD_FIELD(dcfg->num_fw_version_items,
545 if (nitems < entry->partn)
548 verp = &dcfg->fw_version[partn];
549 temp[0] = EFX_WORD_FIELD(verp->version_w, EFX_WORD_0);
550 temp[1] = EFX_WORD_FIELD(verp->version_x, EFX_WORD_0);
551 temp[2] = EFX_WORD_FIELD(verp->version_y, EFX_WORD_0);
552 temp[3] = EFX_WORD_FIELD(verp->version_z, EFX_WORD_0);
553 if (memcmp(version, temp, sizeof (temp)) < 0)
554 memcpy(version, temp, sizeof (temp));
557 EFSYS_KMEM_FREE(enp->en_esip, length, dcfg);
567 EFSYS_PROBE1(fail1, efx_rc_t, rc);
572 __checkReturn efx_rc_t
573 siena_nvram_partn_rw_start(
576 __out size_t *chunk_sizep)
580 if ((rc = siena_nvram_partn_lock(enp, partn)) != 0)
583 if (chunk_sizep != NULL)
584 *chunk_sizep = SIENA_NVRAM_CHUNK;
589 EFSYS_PROBE1(fail1, efx_rc_t, rc);
594 __checkReturn efx_rc_t
595 siena_nvram_partn_rw_finish(
598 __out_opt uint32_t *verify_resultp)
602 if ((rc = siena_nvram_partn_unlock(enp, partn, verify_resultp)) != 0)
608 EFSYS_PROBE1(fail1, efx_rc_t, rc);
613 __checkReturn efx_rc_t
614 siena_nvram_partn_set_version(
617 __in_ecount(4) uint16_t version[4])
619 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
620 siena_mc_dynamic_config_hdr_t *dcfg = NULL;
621 siena_mc_fw_version_t *fwverp;
624 unsigned int hdr_length;
625 unsigned int vpd_length;
626 unsigned int vpd_offset;
628 unsigned int required_hdr_length;
635 dcfg_partn = (emip->emi_port == 1)
636 ? MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0
637 : MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1;
639 if ((rc = siena_nvram_partn_size(enp, dcfg_partn, &dcfg_size)) != 0)
642 if ((rc = siena_nvram_partn_lock(enp, dcfg_partn)) != 0)
645 if ((rc = siena_nvram_get_dynamic_cfg(enp, dcfg_partn,
646 B_TRUE, &dcfg, &length)) != 0)
649 hdr_length = EFX_WORD_FIELD(dcfg->length, EFX_WORD_0);
650 nitems = EFX_DWORD_FIELD(dcfg->num_fw_version_items, EFX_DWORD_0);
651 vpd_length = EFX_DWORD_FIELD(dcfg->dynamic_vpd_length, EFX_DWORD_0);
652 vpd_offset = EFX_DWORD_FIELD(dcfg->dynamic_vpd_offset, EFX_DWORD_0);
655 * NOTE: This function will blatt any fields trailing the version
656 * vector, or the VPD chunk.
658 required_hdr_length = SIENA_DYNAMIC_CFG_SIZE(partn + 1);
659 if (required_hdr_length + vpd_length > length) {
664 if (vpd_offset < required_hdr_length) {
665 (void) memmove((caddr_t)dcfg + required_hdr_length,
666 (caddr_t)dcfg + vpd_offset, vpd_length);
667 vpd_offset = required_hdr_length;
668 EFX_POPULATE_DWORD_1(dcfg->dynamic_vpd_offset,
669 EFX_DWORD_0, vpd_offset);
672 if (hdr_length < required_hdr_length) {
673 (void) memset((caddr_t)dcfg + hdr_length, 0,
674 required_hdr_length - hdr_length);
675 hdr_length = required_hdr_length;
676 EFX_POPULATE_WORD_1(dcfg->length,
677 EFX_WORD_0, hdr_length);
680 /* Get the subtype to insert into the fw_subtype array */
681 if ((rc = siena_nvram_get_subtype(enp, partn, &subtype)) != 0)
684 /* Fill out the new version */
685 fwverp = &dcfg->fw_version[partn];
686 EFX_POPULATE_DWORD_1(fwverp->fw_subtype, EFX_DWORD_0, subtype);
687 EFX_POPULATE_WORD_1(fwverp->version_w, EFX_WORD_0, version[0]);
688 EFX_POPULATE_WORD_1(fwverp->version_x, EFX_WORD_0, version[1]);
689 EFX_POPULATE_WORD_1(fwverp->version_y, EFX_WORD_0, version[2]);
690 EFX_POPULATE_WORD_1(fwverp->version_z, EFX_WORD_0, version[3]);
692 /* Update the version count */
693 if (nitems < partn + 1) {
695 EFX_POPULATE_DWORD_1(dcfg->num_fw_version_items,
696 EFX_DWORD_0, nitems);
699 /* Update the checksum */
701 for (pos = 0; pos < hdr_length; pos++)
702 cksum += ((uint8_t *)dcfg)[pos];
703 dcfg->csum.eb_u8[0] -= cksum;
705 /* Erase and write the new partition */
706 if ((rc = siena_nvram_partn_erase(enp, dcfg_partn, 0, dcfg_size)) != 0)
709 /* Write out the new structure to nvram */
710 if ((rc = siena_nvram_partn_write(enp, dcfg_partn, 0,
711 (caddr_t)dcfg, vpd_offset + vpd_length)) != 0)
714 EFSYS_KMEM_FREE(enp->en_esip, length, dcfg);
716 siena_nvram_partn_unlock(enp, dcfg_partn, NULL);
729 EFSYS_KMEM_FREE(enp->en_esip, length, dcfg);
735 EFSYS_PROBE1(fail1, efx_rc_t, rc);
740 #endif /* EFSYS_OPT_NVRAM */
742 #endif /* EFSYS_OPT_SIENA */