2 * Copyright (c) 2009-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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28 * policies, either expressed or implied, of the FreeBSD Project.
38 __in uint32_t mcdi_cap,
39 __out uint32_t *maskp)
44 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10HDX_LBN))
45 mask |= (1 << EFX_PHY_CAP_10HDX);
46 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10FDX_LBN))
47 mask |= (1 << EFX_PHY_CAP_10FDX);
48 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100HDX_LBN))
49 mask |= (1 << EFX_PHY_CAP_100HDX);
50 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100FDX_LBN))
51 mask |= (1 << EFX_PHY_CAP_100FDX);
52 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000HDX_LBN))
53 mask |= (1 << EFX_PHY_CAP_1000HDX);
54 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN))
55 mask |= (1 << EFX_PHY_CAP_1000FDX);
56 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN))
57 mask |= (1 << EFX_PHY_CAP_10000FDX);
58 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_PAUSE_LBN))
59 mask |= (1 << EFX_PHY_CAP_PAUSE);
60 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_ASYM_LBN))
61 mask |= (1 << EFX_PHY_CAP_ASYM);
62 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
63 mask |= (1 << EFX_PHY_CAP_AN);
69 siena_phy_decode_link_mode(
71 __in uint32_t link_flags,
72 __in unsigned int speed,
73 __in unsigned int fcntl,
74 __out efx_link_mode_t *link_modep,
75 __out unsigned int *fcntlp)
77 boolean_t fd = !!(link_flags &
78 (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN));
79 boolean_t up = !!(link_flags &
80 (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN));
85 *link_modep = EFX_LINK_DOWN;
86 else if (speed == 10000 && fd)
87 *link_modep = EFX_LINK_10000FDX;
88 else if (speed == 1000)
89 *link_modep = fd ? EFX_LINK_1000FDX : EFX_LINK_1000HDX;
90 else if (speed == 100)
91 *link_modep = fd ? EFX_LINK_100FDX : EFX_LINK_100HDX;
93 *link_modep = fd ? EFX_LINK_10FDX : EFX_LINK_10HDX;
95 *link_modep = EFX_LINK_UNKNOWN;
97 if (fcntl == MC_CMD_FCNTL_OFF)
99 else if (fcntl == MC_CMD_FCNTL_RESPOND)
100 *fcntlp = EFX_FCNTL_RESPOND;
101 else if (fcntl == MC_CMD_FCNTL_BIDIR)
102 *fcntlp = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE;
104 EFSYS_PROBE1(mc_pcol_error, int, fcntl);
112 __in efx_qword_t *eqp,
113 __out efx_link_mode_t *link_modep)
115 efx_port_t *epp = &(enp->en_port);
116 unsigned int link_flags;
119 efx_link_mode_t link_mode;
120 uint32_t lp_cap_mask;
123 * Convert the LINKCHANGE speed enumeration into mbit/s, in the
124 * same way as GET_LINK encodes the speed
126 switch (MCDI_EV_FIELD(eqp, LINKCHANGE_SPEED)) {
127 case MCDI_EVENT_LINKCHANGE_SPEED_100M:
130 case MCDI_EVENT_LINKCHANGE_SPEED_1G:
133 case MCDI_EVENT_LINKCHANGE_SPEED_10G:
141 link_flags = MCDI_EV_FIELD(eqp, LINKCHANGE_LINK_FLAGS);
142 siena_phy_decode_link_mode(enp, link_flags, speed,
143 MCDI_EV_FIELD(eqp, LINKCHANGE_FCNTL),
145 siena_phy_decode_cap(MCDI_EV_FIELD(eqp, LINKCHANGE_LP_CAP),
149 * It's safe to update ep_lp_cap_mask without the driver's port lock
150 * because presumably any concurrently running efx_port_poll() is
151 * only going to arrive at the same value.
153 * ep_fcntl has two meanings. It's either the link common fcntl
154 * (if the PHY supports AN), or it's the forced link state. If
155 * the former, it's safe to update the value for the same reason as
156 * for ep_lp_cap_mask. If the latter, then just ignore the value,
157 * because we can race with efx_mac_fcntl_set().
159 epp->ep_lp_cap_mask = lp_cap_mask;
160 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN))
161 epp->ep_fcntl = fcntl;
163 *link_modep = link_mode;
166 __checkReturn efx_rc_t
169 __in boolean_t power)
176 /* Check if the PHY is a zombie */
177 if ((rc = siena_phy_verify(enp)) != 0)
180 enp->en_reset_flags |= EFX_RESET_PHY;
185 EFSYS_PROBE1(fail1, efx_rc_t, rc);
190 __checkReturn efx_rc_t
193 __out siena_link_state_t *slsp)
196 uint8_t payload[MAX(MC_CMD_GET_LINK_IN_LEN,
197 MC_CMD_GET_LINK_OUT_LEN)];
200 (void) memset(payload, 0, sizeof (payload));
201 req.emr_cmd = MC_CMD_GET_LINK;
202 req.emr_in_buf = payload;
203 req.emr_in_length = MC_CMD_GET_LINK_IN_LEN;
204 req.emr_out_buf = payload;
205 req.emr_out_length = MC_CMD_GET_LINK_OUT_LEN;
207 efx_mcdi_execute(enp, &req);
209 if (req.emr_rc != 0) {
214 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_LEN) {
219 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_CAP),
220 &slsp->sls_adv_cap_mask);
221 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_LP_CAP),
222 &slsp->sls_lp_cap_mask);
224 siena_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS),
225 MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED),
226 MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL),
227 &slsp->sls_link_mode, &slsp->sls_fcntl);
229 slsp->sls_mac_up = MCDI_OUT_DWORD(req, GET_LINK_OUT_MAC_FAULT) == 0;
236 EFSYS_PROBE1(fail1, efx_rc_t, rc);
241 __checkReturn efx_rc_t
242 siena_phy_reconfigure(
245 efx_port_t *epp = &(enp->en_port);
247 uint8_t payload[MAX(MAX(MC_CMD_SET_ID_LED_IN_LEN,
248 MC_CMD_SET_ID_LED_OUT_LEN),
249 MAX(MC_CMD_SET_LINK_IN_LEN,
250 MC_CMD_SET_LINK_OUT_LEN))];
252 unsigned int led_mode;
256 (void) memset(payload, 0, sizeof (payload));
257 req.emr_cmd = MC_CMD_SET_LINK;
258 req.emr_in_buf = payload;
259 req.emr_in_length = MC_CMD_SET_LINK_IN_LEN;
260 req.emr_out_buf = payload;
261 req.emr_out_length = MC_CMD_SET_LINK_OUT_LEN;
263 cap_mask = epp->ep_adv_cap_mask;
264 MCDI_IN_POPULATE_DWORD_10(req, SET_LINK_IN_CAP,
265 PHY_CAP_10HDX, (cap_mask >> EFX_PHY_CAP_10HDX) & 0x1,
266 PHY_CAP_10FDX, (cap_mask >> EFX_PHY_CAP_10FDX) & 0x1,
267 PHY_CAP_100HDX, (cap_mask >> EFX_PHY_CAP_100HDX) & 0x1,
268 PHY_CAP_100FDX, (cap_mask >> EFX_PHY_CAP_100FDX) & 0x1,
269 PHY_CAP_1000HDX, (cap_mask >> EFX_PHY_CAP_1000HDX) & 0x1,
270 PHY_CAP_1000FDX, (cap_mask >> EFX_PHY_CAP_1000FDX) & 0x1,
271 PHY_CAP_10000FDX, (cap_mask >> EFX_PHY_CAP_10000FDX) & 0x1,
272 PHY_CAP_PAUSE, (cap_mask >> EFX_PHY_CAP_PAUSE) & 0x1,
273 PHY_CAP_ASYM, (cap_mask >> EFX_PHY_CAP_ASYM) & 0x1,
274 PHY_CAP_AN, (cap_mask >> EFX_PHY_CAP_AN) & 0x1);
276 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, MC_CMD_LOOPBACK_NONE);
278 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_SPEED, speed);
280 #if EFSYS_OPT_PHY_FLAGS
281 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, epp->ep_phy_flags);
283 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, 0);
284 #endif /* EFSYS_OPT_PHY_FLAGS */
286 efx_mcdi_execute(enp, &req);
288 if (req.emr_rc != 0) {
293 /* And set the blink mode */
294 (void) memset(payload, 0, sizeof (payload));
295 req.emr_cmd = MC_CMD_SET_ID_LED;
296 req.emr_in_buf = payload;
297 req.emr_in_length = MC_CMD_SET_ID_LED_IN_LEN;
298 req.emr_out_buf = payload;
299 req.emr_out_length = MC_CMD_SET_ID_LED_OUT_LEN;
301 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, MC_CMD_LED_DEFAULT);
303 efx_mcdi_execute(enp, &req);
305 if (req.emr_rc != 0) {
315 EFSYS_PROBE1(fail1, efx_rc_t, rc);
320 __checkReturn efx_rc_t
325 uint8_t payload[MAX(MC_CMD_GET_PHY_STATE_IN_LEN,
326 MC_CMD_GET_PHY_STATE_OUT_LEN)];
330 (void) memset(payload, 0, sizeof (payload));
331 req.emr_cmd = MC_CMD_GET_PHY_STATE;
332 req.emr_in_buf = payload;
333 req.emr_in_length = MC_CMD_GET_PHY_STATE_IN_LEN;
334 req.emr_out_buf = payload;
335 req.emr_out_length = MC_CMD_GET_PHY_STATE_OUT_LEN;
337 efx_mcdi_execute(enp, &req);
339 if (req.emr_rc != 0) {
344 if (req.emr_out_length_used < MC_CMD_GET_PHY_STATE_OUT_LEN) {
349 state = MCDI_OUT_DWORD(req, GET_PHY_STATE_OUT_STATE);
350 if (state != MC_CMD_PHY_STATE_OK) {
351 if (state != MC_CMD_PHY_STATE_ZOMBIE)
352 EFSYS_PROBE1(mc_pcol_error, int, state);
364 EFSYS_PROBE1(fail1, efx_rc_t, rc);
369 __checkReturn efx_rc_t
372 __out uint32_t *ouip)
374 _NOTE(ARGUNUSED(enp, ouip))
379 #if EFSYS_OPT_PHY_STATS
381 #define SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \
382 _mc_record, _efx_record) \
383 if ((_vmask) & (1ULL << (_mc_record))) { \
384 (_smask) |= (1ULL << (_efx_record)); \
385 if ((_stat) != NULL && !EFSYS_MEM_IS_NULL(_esmp)) { \
387 EFSYS_MEM_READD(_esmp, (_mc_record) * 4, &dword);\
388 (_stat)[_efx_record] = \
389 EFX_DWORD_FIELD(dword, EFX_DWORD_0); \
393 #define SIENA_SIMPLE_STAT_SET2(_vmask, _esmp, _smask, _stat, _record) \
394 SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \
395 MC_CMD_ ## _record, \
396 EFX_PHY_STAT_ ## _record)
399 siena_phy_decode_stats(
402 __in_opt efsys_mem_t *esmp,
403 __out_opt uint64_t *smaskp,
404 __inout_ecount_opt(EFX_PHY_NSTATS) uint32_t *stat)
408 _NOTE(ARGUNUSED(enp))
410 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, OUI);
411 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_LINK_UP);
412 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_RX_FAULT);
413 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_TX_FAULT);
415 if (vmask & (1 << MC_CMD_PMA_PMD_SIGNAL)) {
416 smask |= ((1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_A) |
417 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_B) |
418 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_C) |
419 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_D));
420 if (stat != NULL && esmp != NULL && !EFSYS_MEM_IS_NULL(esmp)) {
423 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PMA_PMD_SIGNAL,
425 sig = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
426 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_A] = (sig >> 1) & 1;
427 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_B] = (sig >> 2) & 1;
428 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_C] = (sig >> 3) & 1;
429 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_D] = (sig >> 4) & 1;
433 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_A,
435 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_B,
437 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_C,
439 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_D,
442 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_LINK_UP);
443 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_RX_FAULT);
444 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_TX_FAULT);
445 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BER);
446 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BLOCK_ERRORS);
448 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_LINK_UP,
449 EFX_PHY_STAT_PHY_XS_LINK_UP);
450 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_RX_FAULT,
451 EFX_PHY_STAT_PHY_XS_RX_FAULT);
452 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_TX_FAULT,
453 EFX_PHY_STAT_PHY_XS_TX_FAULT);
454 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_ALIGN,
455 EFX_PHY_STAT_PHY_XS_ALIGN);
457 if (vmask & (1 << MC_CMD_PHYXS_SYNC)) {
458 smask |= ((1 << EFX_PHY_STAT_PHY_XS_SYNC_A) |
459 (1 << EFX_PHY_STAT_PHY_XS_SYNC_B) |
460 (1 << EFX_PHY_STAT_PHY_XS_SYNC_C) |
461 (1 << EFX_PHY_STAT_PHY_XS_SYNC_D));
462 if (stat != NULL && !EFSYS_MEM_IS_NULL(esmp)) {
465 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PHYXS_SYNC, &dword);
466 sync = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
467 stat[EFX_PHY_STAT_PHY_XS_SYNC_A] = (sync >> 0) & 1;
468 stat[EFX_PHY_STAT_PHY_XS_SYNC_B] = (sync >> 1) & 1;
469 stat[EFX_PHY_STAT_PHY_XS_SYNC_C] = (sync >> 2) & 1;
470 stat[EFX_PHY_STAT_PHY_XS_SYNC_D] = (sync >> 3) & 1;
474 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_LINK_UP);
475 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_COMPLETE);
477 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_CL22_LINK_UP,
478 EFX_PHY_STAT_CL22EXT_LINK_UP);
484 __checkReturn efx_rc_t
485 siena_phy_stats_update(
487 __in efsys_mem_t *esmp,
488 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat)
490 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
491 uint32_t vmask = encp->enc_mcdi_phy_stat_mask;
494 uint8_t payload[MAX(MC_CMD_PHY_STATS_IN_LEN,
495 MC_CMD_PHY_STATS_OUT_DMA_LEN)];
498 (void) memset(payload, 0, sizeof (payload));
499 req.emr_cmd = MC_CMD_PHY_STATS;
500 req.emr_in_buf = payload;
501 req.emr_in_length = MC_CMD_PHY_STATS_IN_LEN;
502 req.emr_out_buf = payload;
503 req.emr_out_length = MC_CMD_PHY_STATS_OUT_DMA_LEN;
505 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_LO,
506 EFSYS_MEM_ADDR(esmp) & 0xffffffff);
507 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_HI,
508 EFSYS_MEM_ADDR(esmp) >> 32);
510 efx_mcdi_execute(enp, &req);
512 if (req.emr_rc != 0) {
516 EFSYS_ASSERT3U(req.emr_out_length, ==, MC_CMD_PHY_STATS_OUT_DMA_LEN);
518 siena_phy_decode_stats(enp, vmask, esmp, &smask, stat);
519 EFSYS_ASSERT(smask == encp->enc_phy_stat_mask);
524 EFSYS_PROBE1(fail1, efx_rc_t, rc);
529 #endif /* EFSYS_OPT_PHY_STATS */
533 __checkReturn efx_rc_t
534 siena_phy_bist_start(
536 __in efx_bist_type_t type)
540 if ((rc = efx_mcdi_bist_start(enp, type)) != 0)
546 EFSYS_PROBE1(fail1, efx_rc_t, rc);
551 static __checkReturn unsigned long
552 siena_phy_sft9001_bist_status(
556 case MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY:
557 return (EFX_PHY_CABLE_STATUS_BUSY);
558 case MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT:
559 return (EFX_PHY_CABLE_STATUS_INTERPAIRSHORT);
560 case MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT:
561 return (EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT);
562 case MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN:
563 return (EFX_PHY_CABLE_STATUS_OPEN);
564 case MC_CMD_POLL_BIST_SFT9001_PAIR_OK:
565 return (EFX_PHY_CABLE_STATUS_OK);
567 return (EFX_PHY_CABLE_STATUS_INVALID);
571 __checkReturn efx_rc_t
574 __in efx_bist_type_t type,
575 __out efx_bist_result_t *resultp,
576 __out_opt __drv_when(count > 0, __notnull)
577 uint32_t *value_maskp,
578 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
579 unsigned long *valuesp,
582 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
583 uint8_t payload[MAX(MC_CMD_POLL_BIST_IN_LEN,
584 MCDI_CTL_SDU_LEN_MAX)];
585 uint32_t value_mask = 0;
590 (void) memset(payload, 0, sizeof (payload));
591 req.emr_cmd = MC_CMD_POLL_BIST;
592 req.emr_in_buf = payload;
593 req.emr_in_length = MC_CMD_POLL_BIST_IN_LEN;
594 req.emr_out_buf = payload;
595 req.emr_out_length = MCDI_CTL_SDU_LEN_MAX;
597 efx_mcdi_execute(enp, &req);
599 if (req.emr_rc != 0) {
604 if (req.emr_out_length_used < MC_CMD_POLL_BIST_OUT_RESULT_OFST + 4) {
610 (void) memset(valuesp, '\0', count * sizeof (unsigned long));
612 result = MCDI_OUT_DWORD(req, POLL_BIST_OUT_RESULT);
614 /* Extract PHY specific results */
615 if (result == MC_CMD_POLL_BIST_PASSED &&
616 encp->enc_phy_type == EFX_PHY_SFT9001B &&
617 req.emr_out_length_used >= MC_CMD_POLL_BIST_OUT_SFT9001_LEN &&
618 (type == EFX_BIST_TYPE_PHY_CABLE_SHORT ||
619 type == EFX_BIST_TYPE_PHY_CABLE_LONG)) {
622 if (count > EFX_BIST_PHY_CABLE_LENGTH_A) {
624 valuesp[EFX_BIST_PHY_CABLE_LENGTH_A] =
626 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A);
627 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_A);
630 if (count > EFX_BIST_PHY_CABLE_LENGTH_B) {
632 valuesp[EFX_BIST_PHY_CABLE_LENGTH_B] =
634 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B);
635 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_B);
638 if (count > EFX_BIST_PHY_CABLE_LENGTH_C) {
640 valuesp[EFX_BIST_PHY_CABLE_LENGTH_C] =
642 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C);
643 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_C);
646 if (count > EFX_BIST_PHY_CABLE_LENGTH_D) {
648 valuesp[EFX_BIST_PHY_CABLE_LENGTH_D] =
650 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D);
651 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_D);
654 if (count > EFX_BIST_PHY_CABLE_STATUS_A) {
655 if (valuesp != NULL) {
656 word = MCDI_OUT_WORD(req,
657 POLL_BIST_OUT_SFT9001_CABLE_STATUS_A);
658 valuesp[EFX_BIST_PHY_CABLE_STATUS_A] =
659 siena_phy_sft9001_bist_status(word);
661 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_A);
664 if (count > EFX_BIST_PHY_CABLE_STATUS_B) {
665 if (valuesp != NULL) {
666 word = MCDI_OUT_WORD(req,
667 POLL_BIST_OUT_SFT9001_CABLE_STATUS_B);
668 valuesp[EFX_BIST_PHY_CABLE_STATUS_B] =
669 siena_phy_sft9001_bist_status(word);
671 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_B);
674 if (count > EFX_BIST_PHY_CABLE_STATUS_C) {
675 if (valuesp != NULL) {
676 word = MCDI_OUT_WORD(req,
677 POLL_BIST_OUT_SFT9001_CABLE_STATUS_C);
678 valuesp[EFX_BIST_PHY_CABLE_STATUS_C] =
679 siena_phy_sft9001_bist_status(word);
681 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_C);
684 if (count > EFX_BIST_PHY_CABLE_STATUS_D) {
685 if (valuesp != NULL) {
686 word = MCDI_OUT_WORD(req,
687 POLL_BIST_OUT_SFT9001_CABLE_STATUS_D);
688 valuesp[EFX_BIST_PHY_CABLE_STATUS_D] =
689 siena_phy_sft9001_bist_status(word);
691 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_D);
694 } else if (result == MC_CMD_POLL_BIST_FAILED &&
695 encp->enc_phy_type == EFX_PHY_QLX111V &&
696 req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MRSFP_LEN &&
697 count > EFX_BIST_FAULT_CODE) {
699 valuesp[EFX_BIST_FAULT_CODE] =
700 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MRSFP_TEST);
701 value_mask |= 1 << EFX_BIST_FAULT_CODE;
704 if (value_maskp != NULL)
705 *value_maskp = value_mask;
707 EFSYS_ASSERT(resultp != NULL);
708 if (result == MC_CMD_POLL_BIST_RUNNING)
709 *resultp = EFX_BIST_RESULT_RUNNING;
710 else if (result == MC_CMD_POLL_BIST_PASSED)
711 *resultp = EFX_BIST_RESULT_PASSED;
713 *resultp = EFX_BIST_RESULT_FAILED;
720 EFSYS_PROBE1(fail1, efx_rc_t, rc);
728 __in efx_bist_type_t type)
730 /* There is no way to stop BIST on Siena */
731 _NOTE(ARGUNUSED(enp, type))
734 #endif /* EFSYS_OPT_BIST */
736 #endif /* EFSYS_OPT_SIENA */