2 * Copyright (c) 2009-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
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9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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40 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
42 uint32_t rx_base, tx_base;
44 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
45 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);
47 rx_base = encp->enc_buftbl_limit;
48 tx_base = rx_base + (encp->enc_rxq_limit *
49 EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
51 /* Initialize the transmit descriptor cache */
52 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, tx_base);
53 EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);
55 EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_DC_SIZE, EFX_TXQ_DC_SIZE);
56 EFX_BAR_WRITEO(enp, FR_AZ_TX_DC_CFG_REG, &oword);
58 /* Initialize the receive descriptor cache */
59 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rx_base);
60 EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);
62 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_SIZE, EFX_RXQ_DC_SIZE);
63 EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_CFG_REG, &oword);
65 /* Set receive descriptor pre-fetch low water mark */
66 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_PF_LWM, 56);
67 EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_PF_WM_REG, &oword);
69 /* Set the event queue to use for SRAM updates */
70 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_UPD_EVQ_ID, 0);
71 EFX_BAR_WRITEO(enp, FR_AZ_SRM_UPD_EVQ_REG, &oword);
74 #endif /* EFSYS_OPT_SIENA */