2 * Copyright (c) 2009-2016 Solarflare Communications Inc.
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6 * modification, are permitted provided that the following conditions are met:
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11 * this list of conditions and the following disclaimer in the documentation
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40 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
42 uint32_t rx_base, tx_base;
44 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
45 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);
47 rx_base = encp->enc_buftbl_limit;
48 tx_base = rx_base + (encp->enc_rxq_limit *
49 EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
51 /* Initialize the transmit descriptor cache */
52 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, tx_base);
53 EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);
55 EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_DC_SIZE, EFX_TXQ_DC_SIZE);
56 EFX_BAR_WRITEO(enp, FR_AZ_TX_DC_CFG_REG, &oword);
58 /* Initialize the receive descriptor cache */
59 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rx_base);
60 EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);
62 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_SIZE, EFX_RXQ_DC_SIZE);
63 EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_CFG_REG, &oword);
65 /* Set receive descriptor pre-fetch low water mark */
66 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_PF_LWM, 56);
67 EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_PF_WM_REG, &oword);
69 /* Set the event queue to use for SRAM updates */
70 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_UPD_EVQ_ID, 0);
71 EFX_BAR_WRITEO(enp, FR_AZ_SRM_UPD_EVQ_REG, &oword);
76 __checkReturn efx_rc_t
79 __in efx_sram_pattern_fn_t func)
89 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);
91 /* Reconfigure into HALF buffer table mode */
92 EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 0);
93 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
96 * Move the descriptor caches up to the top of SRAM, and test
97 * all of SRAM below them. We only miss out one row here.
99 rows = SIENA_SRAM_ROWS - 1;
100 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rows);
101 EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);
103 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, rows + 1);
104 EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);
107 * Write the pattern through BUF_HALF_TBL. Write
108 * in 64 entry batches, waiting 1us in between each batch
109 * to guarantee not to overflow the SRAM fifo
111 for (wptr = 0, rptr = 0; wptr < rows; ++wptr) {
112 func(wptr, B_FALSE, &qword);
113 EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);
115 if ((wptr - rptr) < 64 && wptr < rows - 1)
120 for (; rptr <= wptr; ++rptr) {
121 func(rptr, B_FALSE, &qword);
122 EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,
125 if (!EFX_QWORD_IS_EQUAL(verify, qword)) {
132 /* And do the same negated */
133 for (wptr = 0, rptr = 0; wptr < rows; ++wptr) {
134 func(wptr, B_TRUE, &qword);
135 EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);
137 if ((wptr - rptr) < 64 && wptr < rows - 1)
142 for (; rptr <= wptr; ++rptr) {
143 func(rptr, B_TRUE, &qword);
144 EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,
147 if (!EFX_QWORD_IS_EQUAL(verify, qword)) {
154 /* Restore back to FULL buffer table mode */
155 EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);
156 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
159 * We don't need to reconfigure SRAM again because the API
160 * requires efx_nic_fini() to be called after an sram test.
167 EFSYS_PROBE1(fail1, efx_rc_t, rc);
169 /* Restore back to FULL buffer table mode */
170 EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);
171 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
176 #endif /* EFSYS_OPT_DIAG */
178 #endif /* EFSYS_OPT_SIENA */