1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2016-2019 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
10 #ifndef _SFC_COMMON_EFSYS_H
11 #define _SFC_COMMON_EFSYS_H
15 #include <rte_spinlock.h>
16 #include <rte_byteorder.h>
17 #include <rte_debug.h>
18 #include <rte_memzone.h>
19 #include <rte_memory.h>
20 #include <rte_memcpy.h>
21 #include <rte_cycles.h>
22 #include <rte_prefetch.h>
23 #include <rte_common.h>
24 #include <rte_malloc.h>
28 #include "sfc_debug.h"
35 #define EFSYS_HAS_UINT64 1
36 #define EFSYS_USE_UINT64 1
37 #define EFSYS_HAS_SSE2_M128 1
39 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
40 #define EFSYS_IS_BIG_ENDIAN 1
41 #define EFSYS_IS_LITTLE_ENDIAN 0
42 #elif RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
43 #define EFSYS_IS_BIG_ENDIAN 0
44 #define EFSYS_IS_LITTLE_ENDIAN 1
46 #error "Cannot determine system endianness"
48 #include "efx_types.h"
51 typedef bool boolean_t;
61 * RTE_MAX() and RTE_MIN() cannot be used since braced-group within
62 * expression allowed only inside a function, but MAX() is used as
63 * a number of elements in array.
66 #define MAX(v1, v2) ((v1) > (v2) ? (v1) : (v2))
69 #define MIN(v1, v2) ((v1) < (v2) ? (v1) : (v2))
73 #define ISP2(x) rte_is_power_of_2(x)
76 #define ENOTACTIVE ENOTCONN
79 prefetch_read_many(const volatile void *addr)
85 prefetch_read_once(const volatile void *addr)
87 rte_prefetch_non_temporal(addr);
90 /* Code inclusion options */
93 #define EFSYS_OPT_NAMES 1
95 /* Disable SFN5xxx/SFN6xxx since it requires specific support in the PMD */
96 #define EFSYS_OPT_SIENA 0
97 /* Enable SFN7xxx support */
98 #define EFSYS_OPT_HUNTINGTON 1
99 /* Enable SFN8xxx support */
100 #define EFSYS_OPT_MEDFORD 1
101 /* Enable SFN2xxx support */
102 #define EFSYS_OPT_MEDFORD2 1
103 #ifdef RTE_LIBRTE_SFC_EFX_DEBUG
104 #define EFSYS_OPT_CHECK_REG 1
106 #define EFSYS_OPT_CHECK_REG 0
109 /* MCDI is required for SFN7xxx and SFN8xx */
110 #define EFSYS_OPT_MCDI 1
111 #define EFSYS_OPT_MCDI_LOGGING 1
112 #define EFSYS_OPT_MCDI_PROXY_AUTH 1
114 #define EFSYS_OPT_MAC_STATS 1
116 #define EFSYS_OPT_LOOPBACK 1
118 #define EFSYS_OPT_MON_MCDI 0
119 #define EFSYS_OPT_MON_STATS 0
121 #define EFSYS_OPT_PHY_STATS 0
122 #define EFSYS_OPT_BIST 0
123 #define EFSYS_OPT_PHY_LED_CONTROL 0
124 #define EFSYS_OPT_PHY_FLAGS 0
126 #define EFSYS_OPT_VPD 0
127 #define EFSYS_OPT_NVRAM 0
128 #define EFSYS_OPT_BOOTCFG 0
129 #define EFSYS_OPT_IMAGE_LAYOUT 0
131 #define EFSYS_OPT_DIAG 0
132 #define EFSYS_OPT_RX_SCALE 1
133 #define EFSYS_OPT_QSTATS 0
134 /* Filters support is required for SFN7xxx and SFN8xx */
135 #define EFSYS_OPT_FILTER 1
136 #define EFSYS_OPT_RX_SCATTER 0
138 #define EFSYS_OPT_EV_PREFETCH 0
140 #define EFSYS_OPT_DECODE_INTR_FATAL 0
142 #define EFSYS_OPT_LICENSING 0
144 #define EFSYS_OPT_ALLOW_UNCONFIGURED_NIC 0
146 #define EFSYS_OPT_RX_PACKED_STREAM 0
148 #define EFSYS_OPT_RX_ES_SUPER_BUFFER 1
150 #define EFSYS_OPT_TUNNEL 1
152 #define EFSYS_OPT_FW_SUBVARIANT_AWARE 1
154 #define EFSYS_OPT_EVB 0
156 #define EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 0
160 typedef struct __efsys_identifier_s efsys_identifier_t;
163 #define EFSYS_PROBE(_name) \
166 #define EFSYS_PROBE1(_name, _type1, _arg1) \
169 #define EFSYS_PROBE2(_name, _type1, _arg1, _type2, _arg2) \
172 #define EFSYS_PROBE3(_name, _type1, _arg1, _type2, _arg2, \
176 #define EFSYS_PROBE4(_name, _type1, _arg1, _type2, _arg2, \
177 _type3, _arg3, _type4, _arg4) \
180 #define EFSYS_PROBE5(_name, _type1, _arg1, _type2, _arg2, \
181 _type3, _arg3, _type4, _arg4, _type5, _arg5) \
184 #define EFSYS_PROBE6(_name, _type1, _arg1, _type2, _arg2, \
185 _type3, _arg3, _type4, _arg4, _type5, _arg5, \
189 #define EFSYS_PROBE7(_name, _type1, _arg1, _type2, _arg2, \
190 _type3, _arg3, _type4, _arg4, _type5, _arg5, \
191 _type6, _arg6, _type7, _arg7) \
197 typedef rte_iova_t efsys_dma_addr_t;
199 typedef struct efsys_mem_s {
200 const struct rte_memzone *esm_mz;
202 * Ideally it should have volatile qualifier to denote that
203 * the memory may be updated by someone else. However, it adds
204 * qualifier discard warnings when the pointer or its derivative
205 * is passed to memset() or rte_mov16().
206 * So, skip the qualifier here, but make sure that it is added
207 * below in access macros.
210 efsys_dma_addr_t esm_addr;
214 #define EFSYS_MEM_ZERO(_esmp, _size) \
216 (void)memset((void *)(_esmp)->esm_base, 0, (_size)); \
218 _NOTE(CONSTANTCONDITION); \
221 #define EFSYS_MEM_READD(_esmp, _offset, _edp) \
223 volatile uint8_t *_base = (_esmp)->esm_base; \
224 volatile uint32_t *_addr; \
226 _NOTE(CONSTANTCONDITION); \
227 SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
228 sizeof(efx_dword_t))); \
230 _addr = (volatile uint32_t *)(_base + (_offset)); \
231 (_edp)->ed_u32[0] = _addr[0]; \
233 EFSYS_PROBE2(mem_readl, unsigned int, (_offset), \
234 uint32_t, (_edp)->ed_u32[0]); \
236 _NOTE(CONSTANTCONDITION); \
239 #define EFSYS_MEM_READQ(_esmp, _offset, _eqp) \
241 volatile uint8_t *_base = (_esmp)->esm_base; \
242 volatile uint64_t *_addr; \
244 _NOTE(CONSTANTCONDITION); \
245 SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
246 sizeof(efx_qword_t))); \
248 _addr = (volatile uint64_t *)(_base + (_offset)); \
249 (_eqp)->eq_u64[0] = _addr[0]; \
251 EFSYS_PROBE3(mem_readq, unsigned int, (_offset), \
252 uint32_t, (_eqp)->eq_u32[1], \
253 uint32_t, (_eqp)->eq_u32[0]); \
255 _NOTE(CONSTANTCONDITION); \
258 #define EFSYS_MEM_READO(_esmp, _offset, _eop) \
260 volatile uint8_t *_base = (_esmp)->esm_base; \
261 volatile __m128i *_addr; \
263 _NOTE(CONSTANTCONDITION); \
264 SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
265 sizeof(efx_oword_t))); \
267 _addr = (volatile __m128i *)(_base + (_offset)); \
268 (_eop)->eo_u128[0] = _addr[0]; \
270 EFSYS_PROBE5(mem_reado, unsigned int, (_offset), \
271 uint32_t, (_eop)->eo_u32[3], \
272 uint32_t, (_eop)->eo_u32[2], \
273 uint32_t, (_eop)->eo_u32[1], \
274 uint32_t, (_eop)->eo_u32[0]); \
276 _NOTE(CONSTANTCONDITION); \
280 #define EFSYS_MEM_WRITED(_esmp, _offset, _edp) \
282 volatile uint8_t *_base = (_esmp)->esm_base; \
283 volatile uint32_t *_addr; \
285 _NOTE(CONSTANTCONDITION); \
286 SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
287 sizeof(efx_dword_t))); \
289 EFSYS_PROBE2(mem_writed, unsigned int, (_offset), \
290 uint32_t, (_edp)->ed_u32[0]); \
292 _addr = (volatile uint32_t *)(_base + (_offset)); \
293 _addr[0] = (_edp)->ed_u32[0]; \
295 _NOTE(CONSTANTCONDITION); \
298 #define EFSYS_MEM_WRITEQ(_esmp, _offset, _eqp) \
300 volatile uint8_t *_base = (_esmp)->esm_base; \
301 volatile uint64_t *_addr; \
303 _NOTE(CONSTANTCONDITION); \
304 SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
305 sizeof(efx_qword_t))); \
307 EFSYS_PROBE3(mem_writeq, unsigned int, (_offset), \
308 uint32_t, (_eqp)->eq_u32[1], \
309 uint32_t, (_eqp)->eq_u32[0]); \
311 _addr = (volatile uint64_t *)(_base + (_offset)); \
312 _addr[0] = (_eqp)->eq_u64[0]; \
314 _NOTE(CONSTANTCONDITION); \
317 #define EFSYS_MEM_WRITEO(_esmp, _offset, _eop) \
319 volatile uint8_t *_base = (_esmp)->esm_base; \
320 volatile __m128i *_addr; \
322 _NOTE(CONSTANTCONDITION); \
323 SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
324 sizeof(efx_oword_t))); \
327 EFSYS_PROBE5(mem_writeo, unsigned int, (_offset), \
328 uint32_t, (_eop)->eo_u32[3], \
329 uint32_t, (_eop)->eo_u32[2], \
330 uint32_t, (_eop)->eo_u32[1], \
331 uint32_t, (_eop)->eo_u32[0]); \
333 _addr = (volatile __m128i *)(_base + (_offset)); \
334 _addr[0] = (_eop)->eo_u128[0]; \
336 _NOTE(CONSTANTCONDITION); \
340 #define EFSYS_MEM_SIZE(_esmp) \
341 ((_esmp)->esm_mz->len)
343 #define EFSYS_MEM_ADDR(_esmp) \
346 #define EFSYS_MEM_IS_NULL(_esmp) \
347 ((_esmp)->esm_base == NULL)
349 #define EFSYS_MEM_PREFETCH(_esmp, _offset) \
351 volatile uint8_t *_base = (_esmp)->esm_base; \
353 rte_prefetch0(_base + (_offset)); \
359 typedef struct efsys_bar_s {
360 rte_spinlock_t esb_lock;
362 struct rte_pci_device *esb_dev;
364 * Ideally it should have volatile qualifier to denote that
365 * the memory may be updated by someone else. However, it adds
366 * qualifier discard warnings when the pointer or its derivative
367 * is passed to memset() or rte_mov16().
368 * So, skip the qualifier here, but make sure that it is added
369 * below in access macros.
374 #define SFC_BAR_LOCK_INIT(_esbp, _ifname) \
376 rte_spinlock_init(&(_esbp)->esb_lock); \
377 _NOTE(CONSTANTCONDITION); \
379 #define SFC_BAR_LOCK_DESTROY(_esbp) ((void)0)
380 #define SFC_BAR_LOCK(_esbp) rte_spinlock_lock(&(_esbp)->esb_lock)
381 #define SFC_BAR_UNLOCK(_esbp) rte_spinlock_unlock(&(_esbp)->esb_lock)
383 #define EFSYS_BAR_READD(_esbp, _offset, _edp, _lock) \
385 volatile uint8_t *_base = (_esbp)->esb_base; \
386 volatile uint32_t *_addr; \
388 _NOTE(CONSTANTCONDITION); \
389 SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
390 sizeof(efx_dword_t))); \
391 _NOTE(CONSTANTCONDITION); \
393 SFC_BAR_LOCK(_esbp); \
395 _addr = (volatile uint32_t *)(_base + (_offset)); \
397 (_edp)->ed_u32[0] = rte_read32_relaxed(_addr); \
399 EFSYS_PROBE2(bar_readd, unsigned int, (_offset), \
400 uint32_t, (_edp)->ed_u32[0]); \
402 _NOTE(CONSTANTCONDITION); \
404 SFC_BAR_UNLOCK(_esbp); \
405 _NOTE(CONSTANTCONDITION); \
408 #define EFSYS_BAR_READQ(_esbp, _offset, _eqp) \
410 volatile uint8_t *_base = (_esbp)->esb_base; \
411 volatile uint64_t *_addr; \
413 _NOTE(CONSTANTCONDITION); \
414 SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
415 sizeof(efx_qword_t))); \
417 SFC_BAR_LOCK(_esbp); \
419 _addr = (volatile uint64_t *)(_base + (_offset)); \
421 (_eqp)->eq_u64[0] = rte_read64_relaxed(_addr); \
423 EFSYS_PROBE3(bar_readq, unsigned int, (_offset), \
424 uint32_t, (_eqp)->eq_u32[1], \
425 uint32_t, (_eqp)->eq_u32[0]); \
427 SFC_BAR_UNLOCK(_esbp); \
428 _NOTE(CONSTANTCONDITION); \
431 #define EFSYS_BAR_READO(_esbp, _offset, _eop, _lock) \
433 volatile uint8_t *_base = (_esbp)->esb_base; \
434 volatile __m128i *_addr; \
436 _NOTE(CONSTANTCONDITION); \
437 SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
438 sizeof(efx_oword_t))); \
440 _NOTE(CONSTANTCONDITION); \
442 SFC_BAR_LOCK(_esbp); \
444 _addr = (volatile __m128i *)(_base + (_offset)); \
446 /* There is no rte_read128_relaxed() yet */ \
447 (_eop)->eo_u128[0] = _addr[0]; \
449 EFSYS_PROBE5(bar_reado, unsigned int, (_offset), \
450 uint32_t, (_eop)->eo_u32[3], \
451 uint32_t, (_eop)->eo_u32[2], \
452 uint32_t, (_eop)->eo_u32[1], \
453 uint32_t, (_eop)->eo_u32[0]); \
455 _NOTE(CONSTANTCONDITION); \
457 SFC_BAR_UNLOCK(_esbp); \
458 _NOTE(CONSTANTCONDITION); \
462 #define EFSYS_BAR_WRITED(_esbp, _offset, _edp, _lock) \
464 volatile uint8_t *_base = (_esbp)->esb_base; \
465 volatile uint32_t *_addr; \
467 _NOTE(CONSTANTCONDITION); \
468 SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
469 sizeof(efx_dword_t))); \
471 _NOTE(CONSTANTCONDITION); \
473 SFC_BAR_LOCK(_esbp); \
475 EFSYS_PROBE2(bar_writed, unsigned int, (_offset), \
476 uint32_t, (_edp)->ed_u32[0]); \
478 _addr = (volatile uint32_t *)(_base + (_offset)); \
479 rte_write32_relaxed((_edp)->ed_u32[0], _addr); \
482 _NOTE(CONSTANTCONDITION); \
484 SFC_BAR_UNLOCK(_esbp); \
485 _NOTE(CONSTANTCONDITION); \
488 #define EFSYS_BAR_WRITEQ(_esbp, _offset, _eqp) \
490 volatile uint8_t *_base = (_esbp)->esb_base; \
491 volatile uint64_t *_addr; \
493 _NOTE(CONSTANTCONDITION); \
494 SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
495 sizeof(efx_qword_t))); \
497 SFC_BAR_LOCK(_esbp); \
499 EFSYS_PROBE3(bar_writeq, unsigned int, (_offset), \
500 uint32_t, (_eqp)->eq_u32[1], \
501 uint32_t, (_eqp)->eq_u32[0]); \
503 _addr = (volatile uint64_t *)(_base + (_offset)); \
504 rte_write64_relaxed((_eqp)->eq_u64[0], _addr); \
507 SFC_BAR_UNLOCK(_esbp); \
508 _NOTE(CONSTANTCONDITION); \
512 * Guarantees 64bit aligned 64bit writes to write combined BAR mapping
513 * (required by PIO hardware).
515 * Neither VFIO, nor UIO, nor NIC UIO (on FreeBSD) support
516 * write-combined memory mapped to user-land, so just abort if used.
518 #define EFSYS_BAR_WC_WRITEQ(_esbp, _offset, _eqp) \
520 rte_panic("Write-combined BAR access not supported"); \
523 #define EFSYS_BAR_WRITEO(_esbp, _offset, _eop, _lock) \
525 volatile uint8_t *_base = (_esbp)->esb_base; \
526 volatile __m128i *_addr; \
528 _NOTE(CONSTANTCONDITION); \
529 SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
530 sizeof(efx_oword_t))); \
532 _NOTE(CONSTANTCONDITION); \
534 SFC_BAR_LOCK(_esbp); \
536 EFSYS_PROBE5(bar_writeo, unsigned int, (_offset), \
537 uint32_t, (_eop)->eo_u32[3], \
538 uint32_t, (_eop)->eo_u32[2], \
539 uint32_t, (_eop)->eo_u32[1], \
540 uint32_t, (_eop)->eo_u32[0]); \
542 _addr = (volatile __m128i *)(_base + (_offset)); \
543 /* There is no rte_write128_relaxed() yet */ \
544 _addr[0] = (_eop)->eo_u128[0]; \
547 _NOTE(CONSTANTCONDITION); \
549 SFC_BAR_UNLOCK(_esbp); \
550 _NOTE(CONSTANTCONDITION); \
553 /* Use the standard octo-word write for doorbell writes */
554 #define EFSYS_BAR_DOORBELL_WRITEO(_esbp, _offset, _eop) \
556 EFSYS_BAR_WRITEO((_esbp), (_offset), (_eop), B_FALSE); \
557 _NOTE(CONSTANTCONDITION); \
562 #define EFSYS_SPIN(_us) \
565 _NOTE(CONSTANTCONDITION); \
568 #define EFSYS_SLEEP EFSYS_SPIN
572 #define EFSYS_MEM_READ_BARRIER() rte_rmb()
573 #define EFSYS_PIO_WRITE_BARRIER() rte_io_wmb()
578 * DPDK does not provide any DMA syncing API, and no PMD drivers
579 * have any traces of explicit DMA syncing.
580 * DMA mapping is assumed to be coherent.
583 #define EFSYS_DMA_SYNC_FOR_KERNEL(_esmp, _offset, _size) ((void)0)
585 /* Just avoid store and compiler (impliciltly) reordering */
586 #define EFSYS_DMA_SYNC_FOR_DEVICE(_esmp, _offset, _size) rte_wmb()
590 typedef uint64_t efsys_timestamp_t;
592 #define EFSYS_TIMESTAMP(_usp) \
594 *(_usp) = rte_get_timer_cycles() * 1000000 / \
595 rte_get_timer_hz(); \
596 _NOTE(CONSTANTCONDITION); \
601 #define EFSYS_KMEM_ALLOC(_esip, _size, _p) \
604 (_p) = rte_zmalloc("sfc", (_size), 0); \
605 _NOTE(CONSTANTCONDITION); \
608 #define EFSYS_KMEM_FREE(_esip, _size, _p) \
613 _NOTE(CONSTANTCONDITION); \
618 typedef rte_spinlock_t efsys_lock_t;
620 #define SFC_EFSYS_LOCK_INIT(_eslp, _ifname, _label) \
621 rte_spinlock_init((_eslp))
622 #define SFC_EFSYS_LOCK_DESTROY(_eslp) ((void)0)
623 #define SFC_EFSYS_LOCK(_eslp) \
624 rte_spinlock_lock((_eslp))
625 #define SFC_EFSYS_UNLOCK(_eslp) \
626 rte_spinlock_unlock((_eslp))
627 #define SFC_EFSYS_LOCK_ASSERT_OWNED(_eslp) \
628 SFC_ASSERT(rte_spinlock_is_locked((_eslp)))
630 typedef int efsys_lock_state_t;
632 #define EFSYS_LOCK_MAGIC 0x000010c4
634 #define EFSYS_LOCK(_lockp, _state) \
636 SFC_EFSYS_LOCK(_lockp); \
637 (_state) = EFSYS_LOCK_MAGIC; \
638 _NOTE(CONSTANTCONDITION); \
641 #define EFSYS_UNLOCK(_lockp, _state) \
643 SFC_ASSERT((_state) == EFSYS_LOCK_MAGIC); \
644 SFC_EFSYS_UNLOCK(_lockp); \
645 _NOTE(CONSTANTCONDITION); \
650 typedef uint64_t efsys_stat_t;
652 #define EFSYS_STAT_INCR(_knp, _delta) \
654 *(_knp) += (_delta); \
655 _NOTE(CONSTANTCONDITION); \
658 #define EFSYS_STAT_DECR(_knp, _delta) \
660 *(_knp) -= (_delta); \
661 _NOTE(CONSTANTCONDITION); \
664 #define EFSYS_STAT_SET(_knp, _val) \
667 _NOTE(CONSTANTCONDITION); \
670 #define EFSYS_STAT_SET_QWORD(_knp, _valp) \
672 *(_knp) = rte_le_to_cpu_64((_valp)->eq_u64[0]); \
673 _NOTE(CONSTANTCONDITION); \
676 #define EFSYS_STAT_SET_DWORD(_knp, _valp) \
678 *(_knp) = rte_le_to_cpu_32((_valp)->ed_u32[0]); \
679 _NOTE(CONSTANTCONDITION); \
682 #define EFSYS_STAT_INCR_QWORD(_knp, _valp) \
684 *(_knp) += rte_le_to_cpu_64((_valp)->eq_u64[0]); \
685 _NOTE(CONSTANTCONDITION); \
688 #define EFSYS_STAT_SUBR_QWORD(_knp, _valp) \
690 *(_knp) -= rte_le_to_cpu_64((_valp)->eq_u64[0]); \
691 _NOTE(CONSTANTCONDITION); \
696 #if EFSYS_OPT_DECODE_INTR_FATAL
697 #define EFSYS_ERR(_esip, _code, _dword0, _dword1) \
700 SFC_GENERIC_LOG(ERR, "FATAL ERROR #%u (0x%08x%08x)", \
701 (_code), (_dword0), (_dword1)); \
702 _NOTE(CONSTANTCONDITION); \
708 /* RTE_VERIFY from DPDK treats expressions with % operator incorrectly,
709 * so we re-implement it here
711 #ifdef RTE_LIBRTE_SFC_EFX_DEBUG
712 #define EFSYS_ASSERT(_exp) \
714 if (unlikely(!(_exp))) \
715 rte_panic("line %d\tassert \"%s\" failed\n", \
716 __LINE__, (#_exp)); \
719 #define EFSYS_ASSERT(_exp) (void)(_exp)
722 #define EFSYS_ASSERT3(_x, _op, _y, _t) EFSYS_ASSERT((_t)(_x) _op (_t)(_y))
724 #define EFSYS_ASSERT3U(_x, _op, _y) EFSYS_ASSERT3(_x, _op, _y, uint64_t)
725 #define EFSYS_ASSERT3S(_x, _op, _y) EFSYS_ASSERT3(_x, _op, _y, int64_t)
726 #define EFSYS_ASSERT3P(_x, _op, _y) EFSYS_ASSERT3(_x, _op, _y, uintptr_t)
730 #define EFSYS_HAS_ROTL_DWORD 0
736 #endif /* _SFC_COMMON_EFSYS_H */